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diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h
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index 000000000..d8aad785d
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+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h
@@ -0,0 +1,657 @@
1#pragma once
2
3#ifndef __IO
4 #define __IO volatile
5#endif
6
7// Constants
8// /////////////////////////////////////////////////////////////////////////////
9#define AFIO_DEFAULT 0
10#define AFIO_GPIO 1
11#define AFIO_ADC 2
12#define AFIO_CMP 3
13#define AFIO_TM 4
14#define AFIO_SPI 5
15#define AFIO_USART 6
16#define AFIO_I2C 7
17#define AFIO_SMC 8
18#define AFIO_EBI 9
19#define AFIO_I2S 10
20#define AFIO_OTHER 15
21
22// Flash Memory Controller
23// /////////////////////////////////////////////////////////////////////////////
24typedef struct {
25 __IO uint32_t TADR; //!< 0x000 Flash Target Address Register
26 __IO uint32_t WRDR; //!< 0x004 Flash Write Data Register
27 uint32_t RESERVED0[1]; //!< 0x008 Reserved
28 __IO uint32_t OCMR; //!< 0x00C Flash Operation Command Register
29 __IO uint32_t OPCR; //!< 0x010 Flash Operation Control Register
30 __IO uint32_t OIER; //!< 0x014 Flash Operation Interrupt Enable Register
31 __IO uint32_t OISR; //!< 0x018 Flash Operation Interrupt and Status Register
32 uint32_t RESERVED1[1]; //!< 0x01C Reserved
33 __IO uint32_t PPSR[4]; //!< 0x020 ~ 0x02C Flash Page Erase/Program Protection Status Register
34 __IO uint32_t CPSR; //!< 0x030 Flash Security Protection Status Register
35 uint32_t RESERVED2[51]; //!< 0x034 ~ 0x0FC Reserved
36 __IO uint32_t VMCR; //!< 0x100 Flash Vector Mapping Control Register
37 uint32_t RESERVED3[31]; //!< 0x104 ~ 0x17C Reserved
38 __IO uint32_t MDID; //!< 0x180 Manufacturer and Device ID Register
39 __IO uint32_t PNSR; //!< 0x184 Flash Page Number Status Register
40 __IO uint32_t PSSR; //!< 0x188 Flash Page Size Status Register
41#if defined(HT32F165x)
42 uint32_t RESERVED4[29]; //!< 0x18C ~ 0x1FC Reserved
43#else
44 __IO uint32_t DID; //!< 0x18C Device ID Register
45 uint32_t RESERVED4[28]; //!< 0x190 ~ 0x1FC Reserved
46#endif
47 __IO uint32_t CFCR; //!< 0x200 Flash Cache and Pre-fetch Control Register
48 uint32_t RESERVED5[63]; //!< 0x204 ~ 0x2FC Reserved
49 __IO uint32_t SBVT[4]; //!< 0x300 ~ 0x30C SRAM Booting Vector (4x32Bit)
50#if defined(HT32F165x)
51#else
52 __IO uint32_t CID[4]; //!< 0x310 ~ 0x31C Custom ID Register
53#endif
54} FMC_TypeDef;
55
56#define FMC_OCMR_CMD_MASK (0xF << 0)
57#define FMC_OCMR_CMD_IDLE (0x0 << 0)
58#define FMC_OCMR_CMD_WORD_PROGRAM (0x4 << 0)
59#define FMC_OCMR_CMD_PAGE_ERASE (0x8 << 0)
60#define FMC_OCMR_CMD_MASS_ERASE (0xA << 0)
61#define FMC_OPCR_OPM_MASK (0xF << 1)
62#define FMC_OPCR_OPM_IDLE (0x6 << 1)
63#define FMC_OPCR_OPM_COMMIT (0xA << 1)
64#define FMC_OPCR_OPM_FINISHED (0xE << 1)
65#define FMC_CFCR_CE (1U << 12)
66#define FMC_CFCR_WAIT_MASK (7U << 0)
67#define FMC_CFCR_WAIT_0 (1U)
68#define FMC_CFCR_WAIT_1 (2U)
69
70// Power Control Unit
71// /////////////////////////////////////////////////////////////////////////////
72typedef struct {
73 uint32_t RESERVE0[64];
74 __IO uint32_t BAKSR; //!< 0x000 Status Register
75 __IO uint32_t BAKCR; //!< 0x004 Control Register
76 __IO uint32_t BAKTEST; //!< 0x008 Test Register
77 __IO uint32_t HSIRCR; //!< 0x00C HSI Ready Counter Control Register
78 __IO uint32_t LVDCSR; //!< 0x010 Low Voltage/Brown Out Detect Control and Status Register
79 uint32_t RESERVE1[59]; //!< 0x014 ~ 0x0FC Reserved
80 __IO uint32_t BAKREG[10]; //!< 0x100 ~ 0x124 Backup Register 0 ~ 9
81} PWRCU_TypeDef;
82
83// Clock Control Unit
84// /////////////////////////////////////////////////////////////////////////////
85typedef struct {
86 __IO uint32_t GCFGR; //!< 0x000 Global Clock Configuration Register
87 __IO uint32_t GCCR; //!< 0x004 Global Clock Control Register
88 __IO uint32_t GCSR; //!< 0x008 Global Clock Status Register
89 __IO uint32_t GCIR; //!< 0x00C Global Clock Interrupt Register
90 uint32_t RESERVED0[2]; //!< 0x010 ~ 0x014 Reserved
91 __IO uint32_t PLLCFGR; //!< 0x018 PLL Configuration Register
92 __IO uint32_t PLLCR; //!< 0x01C PLL Control Register
93 __IO uint32_t AHBCFGR; //!< 0x020 AHB Configuration Register
94 __IO uint32_t AHBCCR; //!< 0x024 AHB Clock Control Register
95 __IO uint32_t APBCFGR; //!< 0x028 APB Configuration Register
96 __IO uint32_t APBCCR0; //!< 0x02C APB Clock Control Register 0
97 __IO uint32_t APBCCR1; //!< 0x030 APB Clock Control Register 1
98 __IO uint32_t CKST; //!< 0x034 Clock source status Register
99
100 __IO uint32_t APBPCSR0; //!< 0x038 APB Peripheral Clock Selection Register 0
101 __IO uint32_t APBPCSR1; //!< 0x03C APB Peripheral Clock Selection Register 1
102 __IO uint32_t HSICR; //!< 0x040 HSI Control Register
103 __IO uint32_t HSIATCR; //!< 0x044 HSI Auto Trimming Counter Register
104
105 uint32_t RESERVED2[174]; //!< 0x048 ~ 0x2FC Reserved
106 __IO uint32_t LPCR; //!< 0x300 Low Power Control Register
107 __IO uint32_t MCUDBGCR; //!< 0x304 MCU Debug Control Register
108} CKCU_TypeDef;
109
110#define CKCU_GCFGR_LPMOD_MASK (7U << 29)
111#define CKCU_GCFGR_USBPRE_MASK (3U << 22)
112#define CKCU_GCFGR_PLLSRC (1U << 8)
113#define CKCU_GCFGR_CKOUTSRC_MASK (7U << 0)
114#define CKCU_GCFGR_CKOUTSRC_CK_REF (0U << 0)
115#define CKCU_GCFGR_CKOUTSRC_CK_AHB (1U << 0)
116#define CKCU_GCFGR_CKOUTSRC_CK_SYS (2U << 0)
117#define CKCU_GCFGR_CKOUTSRC_CK_HSE (3U << 0)
118#define CKCU_GCFGR_CKOUTSRC_CK_HSI (4U << 0)
119#define CKCU_GCFGR_CKOUTSRC_CK_LSE (5U << 0)
120#define CKCU_GCFGR_CKOUTSRC_CK_LSI (6U << 0)
121#define CKCU_GCCR_PSRCEN (1U << 17)
122#define CKCU_GCCR_CKMEN (1U << 16)
123#define CKCU_GCCR_HSIEN (1U << 11)
124#define CKCU_GCCR_HSEEN (1U << 10)
125#define CKCU_GCCR_PLLEN (1U << 9)
126#define CKCU_GCCR_SW_MASK (3U << 0)
127#define CKCU_GCCR_SW_PLL (1U << 0)
128#define CKCU_GCCR_SW_HSE (2U << 0)
129#define CKCU_GCCR_SW_HSI (3U << 0)
130#define CKCU_GCSR_LSIRDY (1U << 5)
131#define CKCU_GCSR_LSERDY (1U << 4)
132#define CKCU_GCSR_HSIRDY (1U << 3)
133#define CKCU_GCSR_HSERDY (1U << 2)
134#define CKCU_GCSR_PLLRDY (1U << 1)
135#define CKCU_PLLCFGR_PFBD_MASK (0x3fU << 23)
136#define CKCU_PLLCFGR_POTD_MASK (3U << 21)
137#define CKCU_PLLCR_PLLBPS (1U << 31)
138#define CKCU_AHBCFGR_AHBPRE_MASK (3U << 0)
139#define CKCU_AHBCCR_PAEN (1U << 16)
140#define CKCU_AHBCCR_CRCEN (1U << 13)
141#define CKCU_AHBCCR_EBIEN (1U << 12)
142#define CKCU_AHBCCR_CKREFEN (1U << 11)
143#define CKCU_AHBCCR_USBEN (1U << 10)
144#define CKCU_APBCFGR_ADCDIV_MASK (7U << 16)
145#define CKCU_APBCCR0_I2SEN (1U << 25)
146#define CKCU_APBCCR0_SCIEN (1U << 24)
147#define CKCU_APBCCR0_EXTIEN (1U << 15)
148#define CKCU_APBCCR0_AFIOEN (1U << 14)
149#define CKCU_APBCCR0_UR1EN (1U << 11)
150#define CKCU_APBCCR0_UR0EN (1U << 10)
151#define CKCU_APBCCR0_USR1EN (1U << 9)
152#define CKCU_APBCCR0_USR0EN (1U << 8)
153#define CKCU_APBCCR0_SPI1EN (1U << 5)
154#define CKCU_APBCCR0_SPI0EN (1U << 4)
155#define CKCU_APBCCR0_I2C1EN (1U << 1)
156#define CKCU_APBCCR0_I2C0EN (1U << 0)
157#define CKCU_APBCCR1_ADCEN (1U << 24)
158#define CKCU_APBCCR1_OPA1EN (1U << 23)
159#define CKCU_APBCCR1_OPA0EN (1U << 22)
160#define CKCU_APBCCR1_BFTM1EN (1U << 17)
161#define CKCU_APBCCR1_BFTM0EN (1U << 16)
162#define CKCU_APBCCR1_GPTM1EN (1U << 9)
163#define CKCU_APBCCR1_GPTM0EN (1U << 8)
164#define CKCU_APBCCR1_BKPREN (1U << 6)
165#define CKCU_APBCCR1_WDTREN (1U << 4)
166#define CKCU_APBCCR1_MCTM1EN (1U << 1)
167#define CKCU_APBCCR1_MCTM0EN (1U << 0)
168#define CKCU_CKST_CKSWST_MASK (3U << 30)
169#define CKCU_CKST_HSIST_MASK (7U << 24)
170#define CKCU_CKST_HSEST_MASK (3U << 16)
171#define CKCU_CKST_PLLST_MASK (0xfU << 8)
172#define CKCU_LPCR_USBSLEEP (1U << 8)
173#define CKCU_LPCR_BKISO (1U << 0)
174
175// Reset Control Unit
176// /////////////////////////////////////////////////////////////////////////////
177typedef struct {
178 __IO uint32_t GRSR; //!< 0x000 Global Reset Status Register
179 __IO uint32_t AHBPRSTR; //!< 0x004 AHB Peripheral Reset Register
180 __IO uint32_t APBPRSTR0; //!< 0x008 APB Peripheral Reset Register 0
181 __IO uint32_t APBPRSTR1; //!< 0x00C APB Peripheral Reset Register 1
182} RSTCU_TypeDef;
183
184#define RSTCU_GRSR_PORSTF (1U << 3)
185#define RSTCU_GRSR_WDTRSTF (1U << 2)
186#define RSTCU_GRSR_EXTRSTF (1U << 1)
187#define RSTCU_GRSR_SYSRSTF (1U << 0)
188#define RSTCU_AHBPRSTR_PxRST(n) ((1U << 8) << (n))
189#define RSTCU_AHBPRSTR_CRCRST (1U << 7)
190#define RSTCU_AHBPRSTR_EBIRST (1U << 6)
191#define RSTCU_AHBPRSTR_USBRST (1U << 5)
192#define RSTCU_AHBPRSTR_DMARST (1U << 0)
193#define RSTCU_APBPRSTR0_I2SRST (1U << 25)
194#define RSTCU_APBPRSTR0_SCIRST (1U << 24)
195#define RSTCU_APBPRSTR0_EXTIRST (1U << 15)
196#define RSTCU_APBPRSTR0_AFIORST (1U << 14)
197#define RSTCU_APBPRSTR0_UR1RST (1U << 11)
198#define RSTCU_APBPRSTR0_UR0RST (1U << 10)
199#define RSTCU_APBPRSTR0_USR1RST (1U << 9)
200#define RSTCU_APBPRSTR0_USR0RST (1U << 8)
201#define RSTCU_APBPRSTR0_SPI1RST (1U << 5)
202#define RSTCU_APBPRSTR0_SPI0RST (1U << 4)
203#define RSTCU_APBPRSTR0_I2C1RST (1U << 1)
204#define RSTCU_APBPRSTR0_I2C0RST (1U << 0)
205#define RSTCU_APBPRSTR1_ADCRST (1U << 24)
206#define RSTCU_APBPRSTR1_OPA1RST (1U << 23)
207#define RSTCU_APBPRSTR1_OPA0RST (1U << 22)
208#define RSTCU_APBPRSTR1_BFTM1RST (1U << 17)
209#define RSTCU_APBPRSTR1_BFTM0RST (1U << 16)
210#define RSTCU_APBPRSTR1_GPTM1RST (1U << 9)
211#define RSTCU_APBPRSTR1_GPTM0RST (1U << 8)
212#define RSTCU_APBPRSTR1_WDTRST (1U << 4)
213#define RSTCU_APBPRSTR1_MCTM1RST (1U << 1)
214#define RSTCU_APBPRSTR1_MCTM0RST (1U << 0)
215
216// General Purpose I/O
217// /////////////////////////////////////////////////////////////////////////////
218typedef struct {
219 __IO uint32_t DIRCR; //!< 0x000 Data Direction Control Register
220 __IO uint32_t INER; //!< 0x004 Input function enable register
221 __IO uint32_t PUR; //!< 0x008 Pull-Up Selection Register
222 __IO uint32_t PDR; //!< 0x00C Pull-Down Selection Register
223 __IO uint32_t ODR; //!< 0x010 Open Drain Selection Register
224 __IO uint32_t DRVR; //!< 0x014 Drive Current Selection Register
225 __IO uint32_t LOCKR; //!< 0x018 Lock Register
226 __IO uint32_t DINR; //!< 0x01c Data Input Register
227 __IO uint32_t DOUTR; //!< 0x020 Data Output Register
228 __IO uint32_t SRR; //!< 0x024 Output Set and Reset Control Register
229 __IO uint32_t RR; //!< 0x028 Output Reset Control Register
230} GPIO_TypeDef;
231
232// Alternate Function Input/Output
233// /////////////////////////////////////////////////////////////////////////////
234typedef struct {
235 __IO uint32_t ESSR[2]; //!< 0x000 ~ 0x004 EXTI Source Selection Register 0 ~ 1
236 uint32_t RESERVE0[6]; //!< 0x008 ~ 0x01C Reserved
237 union {
238 struct {
239 __IO uint32_t GPACFGR[2]; //!< 0x020 ~ 0x024 GPIO Port A Configuration Register 0 ~ 1
240 __IO uint32_t GPBCFGR[2]; //!< 0x028 ~ 0x02C GPIO Port B Configuration Register 0 ~ 1
241 __IO uint32_t GPCCFGR[2]; //!< 0x030 ~ 0x034 GPIO Port C Configuration Register 0 ~ 1
242 __IO uint32_t GPDCFGR[2]; //!< 0x038 ~ 0x03C GPIO Port D Configuration Register 0 ~ 1
243 };
244 // alternate mapping
245 struct {
246 __IO uint32_t GPxCFGR[0][2]; //!< 0x020 ~ 0x03C GPIO Port x Configuration Register 0 ~ 1
247 };
248 };
249} AFIO_TypeDef;
250
251// Nested Vectored Interrupt Controller
252// /////////////////////////////////////////////////////////////////////////////
253// Implemented in Cortex-M3 Headers
254
255// External Interrupt/Event Controller
256// /////////////////////////////////////////////////////////////////////////////
257typedef struct {
258 __IO uint32_t CFGR0; //!< 0x000 EXTI Interrupt 0 Configuration Register
259 __IO uint32_t CFGR1; //!< 0x004 EXTI Interrupt 1 Configuration Register
260 __IO uint32_t CFGR2; //!< 0x008 EXTI Interrupt 2 Configuration Register
261 __IO uint32_t CFGR3; //!< 0x00C EXTI Interrupt 3 Configuration Register
262 __IO uint32_t CFGR4; //!< 0x010 EXTI Interrupt 4 Configuration Register
263 __IO uint32_t CFGR5; //!< 0x014 EXTI Interrupt 5 Configuration Register
264 __IO uint32_t CFGR6; //!< 0x018 EXTI Interrupt 6 Configuration Register
265 __IO uint32_t CFGR7; //!< 0x01C EXTI Interrupt 7 Configuration Register
266 __IO uint32_t CFGR8; //!< 0x020 EXTI Interrupt 8 Configuration Register
267 __IO uint32_t CFGR9; //!< 0x024 EXTI Interrupt 9 Configuration Register
268 __IO uint32_t CFGR10; //!< 0x028 EXTI Interrupt 10 Configuration Register
269 __IO uint32_t CFGR11; //!< 0x02C EXTI Interrupt 11 Configuration Register
270 __IO uint32_t CFGR12; //!< 0x030 EXTI Interrupt 12 Configuration Register
271 __IO uint32_t CFGR13; //!< 0x034 EXTI Interrupt 13 Configuration Register
272 __IO uint32_t CFGR14; //!< 0x038 EXTI Interrupt 14 Configuration Register
273 __IO uint32_t CFGR15; //!< 0x03C EXTI Interrupt 15 Configuration Register
274 __IO uint32_t CR; //!< 0x040 EXTI Interrupt Control Register
275 __IO uint32_t EDGEFLGR; //!< 0x044 EXTI Interrupt Edge Flag Register
276 __IO uint32_t EDGESR; //!< 0x048 EXTI Interrupt Edge Status Register
277 __IO uint32_t SSCR; //!< 0x04C EXTI Interrupt Software Set Command Register
278 __IO uint32_t WAKUPCR; //!< 0x050 EXTI Interrupt Wakeup Control Register
279 __IO uint32_t WAKUPPOLR; //!< 0x054 EXTI Interrupt Wakeup Polarity Register
280 __IO uint32_t WAKUPFLG; //!< 0x058 EXTI Interrupt Wakeup Flag Register
281} EXTI_TypeDef;
282
283// Analog To Digital Converter
284// /////////////////////////////////////////////////////////////////////////////
285
286// Operational Amplifier / Comparator
287// /////////////////////////////////////////////////////////////////////////////
288typedef struct {
289 __IO uint32_t CR; //!< 0x000 Comparator Control Register
290 __IO uint32_t VALR; //!< 0x004 Comparator Voltage Reference Register
291 __IO uint32_t IER; //!< 0x008 Comparator Interrupt Enable Register
292 __IO uint32_t TFR; //!< 0x00C Comparator Transition Flag Register
293} CMP_TypeDef;
294
295
296// Basic Function Timers
297// /////////////////////////////////////////////////////////////////////////////
298typedef struct {
299 __IO uint32_t CR; //!< 0x000 Control Register
300 __IO uint32_t SR; //!< 0x004 Status Register
301 __IO uint32_t CNTR; //!< 0x008 Counter Value Register
302 __IO uint32_t CMP; //!< 0x00C Compare Value Register
303} BFTM_TypeDef;
304
305#define BFTM_CR_CEN (1U << 2)
306#define BFTM_CR_OSM (1U << 1)
307#define BFTM_CR_MIEN (1U << 0)
308#define BFTM_SR_MIF (1U << 0)
309
310// General Purpose Timers
311// Motor Control Timers
312// /////////////////////////////////////////////////////////////////////////////
313typedef struct {
314 __IO uint32_t CNTCFR; //!< 0x000 Timer Counter Configuaration Register
315 __IO uint32_t MDCFR; //!< 0x004 Timer Mode Configuration Register
316 __IO uint32_t TRCFR; //!< 0x008 Timer Trigger Configuration Register
317 uint32_t RESERVED0[1]; //!< 0x00C Reserved
318 __IO uint32_t CTR; //!< 0x010 Timer Counter Register
319 uint32_t RESERVED1[3]; //!< 0x014 ~ 0x01C Reserved
320 __IO uint32_t CHnICFR[4]; //!< 0x020 ~ 0x02C Channel n Input Configuration Register
321 uint32_t RESERVED2[4]; //!< 0x030 ~ 0x03C Reserved
322 __IO uint32_t CHnOCFR[4]; //!< 0x040 ~ 0x04C Channel n Output Configuration Register
323 __IO uint32_t CHCTR; //!< 0x050 Channel Control Register
324 __IO uint32_t CHPOLR; //!< 0x054 Channel Polarity Control Register
325 uint32_t RESERVED3[5]; //!< 0x058 ~ 0x068 Reserved
326 // note: only available as MCTM
327 __IO uint32_t CHBRKCFR; //!< 0x06C Channel Break Configuration Register
328 __IO uint32_t CHBRKCTR; //!< 0x070 Channel Break Control Register
329 // end note
330 __IO uint32_t DICTR; //!< 0x074 Timer PDMA/Interrupt Control Register
331 __IO uint32_t EVGR; //!< 0x078 Timer Event Generator Register
332 __IO uint32_t INTSR; //!< 0x07C Timer Interrupt Status Register
333 __IO uint32_t CNTR; //!< 0x080 Timer Counter Register
334 __IO uint32_t PSCR; //!< 0x084 Timer Prescaler Register
335 __IO uint32_t CRR; //!< 0x088 Timer Counter Reload Register
336 // note: only available as MCTM
337 __IO uint32_t REPR; //!< 0x08C Timer Repetition Register
338 // end note
339 __IO uint32_t CHnCCR[4]; //!< 0x090 ~ 0x09C Channel n Capture/Compare Register
340 __IO uint32_t CHnACR[4]; //!< 0x0A0 ~ 0x0AC Channel n Asymmentric Compare Register
341} TM_TypeDef;
342
343#define TM_CNTCFR_CMSEL_MASK (3U << 16)
344#define TM_CNTCFR_CMSEL_MODE_3 (3U << 16)
345#define TM_CNTCFR_CMSEL_MODE_2 (2U << 16)
346#define TM_CNTCFR_CMSEL_MODE_1 (1U << 16)
347#define TM_CNTCFR_CMSEL_MODE_0 (0U << 16)
348#define TM_CTR_CHCCDS (1U << 16)
349#define TM_CTR_COMUS (1U << 9)
350#define TM_CTR_COMPRE (1U << 8)
351#define TM_CTR_CRBE (1U << 1)
352#define TM_CTR_TME (1U << 0)
353#define TM_CHnOCFR_CHnPRE (1U << 4)
354#define TM_CHnOCFR_REFnCE (1U << 3)
355#define TM_CHnOCFR_CHnOM(n) ((((n)>>0)&7)|((((n)>>3)&1)<<8))
356#define TM_CHBRKCTR_CHMOE (1U << 4)
357
358// Real Time Clock
359// /////////////////////////////////////////////////////////////////////////////
360
361// Watchdog Timer
362// /////////////////////////////////////////////////////////////////////////////
363
364// I2C
365// /////////////////////////////////////////////////////////////////////////////
366typedef struct {
367 __IO uint32_t CR; //!< 0x000 Control Register
368 __IO uint32_t IER; //!< 0x004 Interrupt Enable Register
369 __IO uint32_t ADDR; //!< 0x008 Address Register
370 __IO uint32_t SR; //!< 0x00C Status Register
371 __IO uint32_t SHPGR; //!< 0x010 SCL High Period Generation Register
372 __IO uint32_t SLPGR; //!< 0x014 SCL Low Period Generation Register
373 __IO uint32_t DR; //!< 0x018 Data Register
374 __IO uint32_t TAR; //!< 0x01C Target Register
375 __IO uint32_t ADDMR; //!< 0x020 Address Mask Register
376 __IO uint32_t ADDSR; //!< 0x024 Address Snoop Register
377 __IO uint32_t TOUT; //!< 0x028 Timeout Register
378} I2C_TypeDef;
379
380#define I2C_CR_SEQ_FILTER_MASK (3U << 14)
381#define I2C_CR_SEQ_FILTER_2_PCLK (2U << 14)
382#define I2C_CR_SEQ_FILTER_1_PCLK (1U << 14)
383#define I2C_CR_SEQ_FILTER_DISABLE (0U << 14)
384#define I2C_CR_COMB_FILTER_En (1U << 13)
385#define I2C_CR_ENTOUT (1U << 12)
386#define I2C_CR_DMANACK (1U << 10)
387#define I2C_CR_RXDMAE (1U << 9)
388#define I2C_CR_TXDMAE (1U << 8)
389#define I2C_CR_ADRM (1U << 7)
390#define I2C_CR_I2CEN (1U << 3)
391#define I2C_CR_GCEN (1U << 2)
392#define I2C_CR_STOP (1U << 1)
393#define I2C_CR_AA (1U << 0)
394#define I2C_IER_RXBFIE (1U << 18)
395#define I2C_IER_TXDEIE (1U << 17)
396#define I2C_IER_RXDNEIE (1U << 16)
397#define I2C_IER_TOUTIE (1U << 11)
398#define I2C_IER_BUSERRIE (1U << 10)
399#define I2C_IER_RXNACKIE (1U << 9)
400#define I2C_IER_ARBLOSIE (1U << 8)
401#define I2C_IER_GCSIE (1U << 3)
402#define I2C_IER_ADRSIE (1U << 2)
403#define I2C_IER_STOIE (1U << 1)
404#define I2C_IER_STAIE (1U << 0)
405#define I2C_SR_TXNRX (1U << 21)
406#define I2C_SR_MASTER (1U << 20)
407#define I2C_SR_BUSBUSY (1U << 19)
408#define I2C_SR_RXBF (1U << 18)
409#define I2C_SR_TXDE (1U << 17)
410#define I2C_SR_RXDNE (1U << 16)
411#define I2C_SR_TOUTF (1U << 11)
412#define I2C_SR_BUSERR (1U << 10)
413#define I2C_SR_RXNACK (1U << 9)
414#define I2C_SR_ARBLOS (1U << 8)
415#define I2C_SR_GCS (1U << 3)
416#define I2C_SR_ADRS (1U << 2)
417#define I2C_SR_STO (1U << 1)
418#define I2C_SR_STA (1U << 0)
419#define I2C_TAR_RWD (1U << 10)
420
421// SPI
422// /////////////////////////////////////////////////////////////////////////////
423typedef struct {
424 __IO uint32_t CR0; //!< 0x000 Control Register 0
425 __IO uint32_t CR1; //!< 0x004 Control Register 1
426 __IO uint32_t IER; //!< 0x008 Interrupt Enable Register
427 __IO uint32_t CPR; //!< 0x00C Clock Prescaler Register
428 __IO uint32_t DR; //!< 0x010 Data Register
429 __IO uint32_t SR; //!< 0x014 Status Register
430 __IO uint32_t FCR; //!< 0x018 FIFO Control Register
431 __IO uint32_t FSR; //!< 0x01C FIFO Status Register
432 __IO uint32_t FTOCR; //!< 0x020 FIFO Time Out Counter Register
433} SPI_TypeDef;
434
435#define SPI_CR0_GUADTEN (1U << 7)
436#define SPI_CR0_DUALEN (1U << 6)
437#define SPI_CR0_SSELC (1U << 4)
438#define SPI_CR0_SELOEN (1U << 3)
439#define SPI_CR0_SPIEN (1U << 0)
440#define SPI_CR1_MODE (1U << 14)
441#define SPI_CR1_SELM (1U << 13)
442#define SPI_CR1_FIRSTBIT (1U << 12)
443#define SPI_CR1_SELAP (1U << 11)
444#define SPI_CR1_FORMAT_MASK (7U << 8)
445#define SPI_CR1_FORMAT_MODE0 (0x1U << 8)
446#define SPI_CR1_FORMAT_MODE1 (0x2U << 8)
447#define SPI_CR1_FORMAT_MODE2 (0x6U << 8)
448#define SPI_CR1_FORMAT_MODE3 (0x5U << 8)
449#define SPI_IER_RXBNEIEN (1U << 2)
450#define SPI_IER_TXBEIEN (1U << 0)
451#define SPI_SR_RXBNE (1U << 2)
452#define SPI_SR_TXE (1U << 1)
453#define SPI_SR_TXBE (1U << 0)
454#define SPI_FCR_FIFOEN (1U << 10)
455#define SPI_FSR_TXFS_MASK (0xfU << 0)
456#define SPI_FSR_RXFS_MASK (0xfU << 4)
457
458// USART
459// UART
460// /////////////////////////////////////////////////////////////////////////////
461typedef struct {
462 __IO uint32_t DR; //!< 0x000 Data Register
463 __IO uint32_t CR; //!< 0x004 Control Register
464 // Only USART
465 __IO uint32_t FCR; //!< 0x008 FIFO Control Register
466 __IO uint32_t IER; //!< 0x00C Interrupt Enable Register
467 __IO uint32_t SIFR; //!< 0x010 Status & Interrupt Flag Register
468
469 __IO uint32_t TPR; //!< 0x014 Timing Parameter Register
470
471 __IO uint32_t IrDACR; //!< 0x018 IrDA Control Register
472 __IO uint32_t RS485CR; //!< 0x01C RS485 Control Register
473 __IO uint32_t SYNCR; //!< 0x020 Synchronous Control Register
474 // end note
475 __IO uint32_t DLR; //!< 0x024 Divider Latch Register
476 __IO uint32_t TSTR; //!< 0x028 Debug/Test Register
477} USART_TypeDef;
478
479// USART CR
480#define UART_CR_MODE_MASK (0b11 << 0)
481#define UART_CR_MODE_NORMAL (0 << 0)
482#define UART_CR_TRSM (1 << 2)
483#define UART_CR_HFCEN (1 << 3)
484#define UART_CR_URTXEN (1 << 4)
485#define UART_CR_URRXEN (1 << 5)
486#define UART_CR_TXDMAEN (1 << 6)
487#define UART_CR_RXDMAEN (1 << 7)
488#define UART_CR_WLS_MASK (0b11 << 8)
489#define UART_CR_WLS_7B (0b00 << 8)
490#define UART_CR_WLS_8B (0b01 << 8)
491#define UART_CR_WLS_9B (0b10 << 8)
492#define UART_CR_NSB (1 << 10)
493#define UART_CR_PBE (1 << 11)
494#define UART_CR_EPE (1 << 12)
495#define UART_CR_SPE (1 << 13)
496#define UART_CR_BCB (1 << 14)
497#define UART_CR_RTS (1 << 15)
498// USART FCR (FIFO CR)
499#define USART_FCR_TXR (1 << 0)
500#define USART_FCR_RXR (1 << 1)
501#define USART_FCR_TXTL_MASK (0b11 << 4)
502#define USART_FCR_RXTL_MASK (0b11 << 6)
503#define USART_FCR_TXFS_MASK (0xF << 16)
504#define USART_FCR_RXFS_MASK (0xF << 24)
505// USART SIFR Status and Interrupt Flag Register
506#define USART_SIFR_RXDNE (1 << 0)
507#define USART_SIFR_OEI (1 << 1)
508#define USART_SIFR_PEI (1 << 2)
509#define USART_SIFR_FEI (1 << 3)
510#define USART_SIFR_BII (1 << 4)
511#define USART_SIFR_RXDR (1 << 5)
512#define USART_SIFR_RXTOF (1 << 6)
513#define USART_SIFR_TXDE (1 << 7)
514#define USART_SIFR_TXC (1 << 8)
515#define USART_SIFR_RSADDE (1 << 9)
516#define USART_SIFR_CTSC (1 << 10)
517#define USART_SIFR_CTSS (1 << 11)
518// USART IER
519#define USART_IER_RXDRIE (1 << 0)
520#define USART_IER_TXDEIE (1 << 1)
521#define USART_IER_TXCIE (1 << 2)
522#define USART_IER_OEIE (1 << 3)
523#define USART_IER_PEIE (1 << 4)
524#define USART_IER_FEIE (1 << 5)
525#define USART_IER_BIE (1 << 6)
526#define USART_IER_RSADDIE (1 << 7)
527#define USART_IER_RXTOIE (1 << 8)
528#define USART_IER_CTSIE (1 << 9)
529
530
531// Smart Card Interface
532// /////////////////////////////////////////////////////////////////////////////
533
534// USB
535// /////////////////////////////////////////////////////////////////////////////
536typedef struct {
537 __IO uint32_t CSR; //!< 0x000 USB Control and Status Register
538 __IO uint32_t IER; //!< 0x004 USB Interrupt Enable Register
539 __IO uint32_t ISR; //!< 0x008 USB Interrupt Status Register
540 __IO uint32_t FCR; //!< 0x00C USB Frame Count Register
541 __IO uint32_t DEVAR; //!< 0x010 USB Device Address Register
542 struct {
543 __IO uint32_t CSR; //!< 0x014 USB Endpoint n Control and Status Register
544 __IO uint32_t IER; //!< 0x018 USB Endpoint n Interrupt Enable Register
545 __IO uint32_t ISR; //!< 0x01C USB Endpoint n Interrupt Status Register
546 __IO uint32_t TCR; //!< 0x020 USB Endpoint n Transfer Count Register
547 __IO uint32_t CFGR; //!< 0x024 USB Endpoint n Configuration Register
548 } EP[8];
549} USB_TypeDef;
550
551// USBCSR
552#define USBCSR_FRES (0x002) // Force USB Reset Control
553#define USBCSR_PDWN (0x004) // Power Down Mode Control
554#define USBCSR_LPMODE (0x008) // Low-Power Mode Control
555#define USBCSR_GENRSM (0x020) // Resume Request Generation Control
556#define USBCSR_RXDP (0x040) // Received DP Line Status
557#define USBCSR_RXDM (0x080) // Received DM Line Status
558#define USBCSR_ADRSET (0x100) // Device Address Setting Control
559#define USBCSR_SRAMRSTC (0x200) // USB SRAM Reset Condition
560#define USBCSR_DPPUEN (0x400) // DP Pull Up Enable
561#define USBCSR_DPWKEN (0x800) // DP Wake Up Enable
562
563// USBIER
564#define USBIER_UGIE (0x0001) // USB global Interrupt Enable
565#define USBIER_SOFIE (0x0002) // Start Of Frame Interrupt Enable
566#define USBIER_URSTIE (0x0004) // USB Reset Interrupt Enable
567#define USBIER_RSMIE (0x0008) // Resume Interrupt Enable
568#define USBIER_SUSPIE (0x0010) // Suspend Interrupt Enable
569#define USBIER_ESOFIE (0x0020) // Expected Start Of Frame Enable
570#define USBIER_EP0IE (0x0100) // Endpoint 0 Interrupt Enable
571#define USBIER_EP1IE (0x0200) // Endpoint 1 Interrupt Enable
572#define USBIER_EP2IE (0x0400) // Endpoint 2 Interrupt Enable
573#define USBIER_EP3IE (0x0800) // Endpoint 3 Interrupt Enable
574#define USBIER_EP4IE (0x1000) // Endpoint 4 Interrupt Enable
575#define USBIER_EP5IE (0x2000) // Endpoint 5 Interrupt Enable
576#define USBIER_EP6IE (0x4000) // Endpoint 6 Interrupt Enable
577#define USBIER_EP7IE (0x8000) // Endpoint 7 Interrupt Enable
578
579// USBISR
580#define USBISR_SOFIF (0x0002) // Start Of Frame Interrupt Flag
581#define USBISR_URSTIF (0x0004) // USB Reset Interrupt Flag
582#define USBISR_RSMIF (0x0008) // Resume Interrupt Flag
583#define USBISR_SUSPIF (0x0010) // Suspend Interrupt Flag
584#define USBISR_ESOFIF (0x0020) // Expected Start Of Frame Interrupt
585#define USBISR_EP0IF (1U << 8) // Endpoint 0 Interrupt Flag
586#define USBISR_EP1IF (1U << 9) // Endpoint 1 Interrupt Flag
587#define USBISR_EP2IF (1U << 10) // Endpoint 2 Interrupt Flag
588#define USBISR_EP3IF (1U << 11) // Endpoint 3 Interrupt Flag
589#define USBISR_EP4IF (1U << 12) // Endpoint 4 Interrupt Flag
590#define USBISR_EP5IF (1U << 13) // Endpoint 5 Interrupt Flag
591#define USBISR_EP6IF (1U << 14) // Endpoint 6 Interrupt Flag
592#define USBISR_EP7IF (1U << 15) // Endpoint 7 Interrupt Flag
593#define USBISR_EPnIF (0xFF00) // Endpoint Interrupt Mask
594
595// USBFCR
596#define USBFCR_FRNUM (0x7FF) // Frame Number
597#define USBFCR_SOFLCK (1U << 16) // Start-of-Frame Lock Flag
598#define USBFCR_LSOF (0x3U << 17) // Lost Start-of-Frame Number
599
600// USBEPnCSR
601#define USBEPnCSR_DTGTX (0x01) // Data Toggle Status, for IN transfer
602#define USBEPnCSR_NAKTX (0x02) // NAK Status, for IN transfer
603#define USBEPnCSR_STLTX (0x04) // STALL Status, for IN transfer
604#define USBEPnCSR_DTGRX (0x08) // Data Toggle Status, for OUT transfer
605#define USBEPnCSR_NAKRX (0x10) // NAK Status, for OUT transfer
606#define USBEPnCSR_STLRX (0x20) // STALL Status, for OUT transfer
607
608// USBEPnIER
609#define USBEPnIER_OTRXIE (0x001) // OUT Token Received Interrupt Enable
610#define USBEPnIER_ODRXIE (0x002) // OUT Data Received Interrupt Enable
611#define USBEPnIER_ODOVIE (0x004) // OUT Data Buffer Overrun Interrupt Enable
612#define USBEPnIER_ITRXIE (0x008) // IN Token Received Interrupt Enable
613#define USBEPnIER_IDTXIE (0x010) // IN Data Transmitted Interrupt Enable
614#define USBEPnIER_NAKIE (0x020) // NAK Transmitted Interrupt Enable
615#define USBEPnIER_STLIE (0x040) // STALL Transmitted Interrupt Enable
616#define USBEPnIER_UERIE (0x080) // USB Error Interrupt Enable
617#define USBEPnIER_STRXIE (0x100) // SETUP Token Received Interrupt Enable
618#define USBEPnIER_SDRXIE (0x200) // SETUP Data Received Interrupt Enable
619#define USBEPnIER_SDERIE (0x400) // SETUP Data Error Interrupt Enable
620#define USBEPnIER_ZLRXIE (0x800) // Zero Length Data Received Interrupt Enable
621
622// USBEPnISR
623#define USBEPnISR_OTRXIF (0x001) // OUT Token Received Interrupt Flag
624#define USBEPnISR_ODRXIF (0x002) // OUT Data Received Interrupt Flag
625#define USBEPnISR_ODOVIF (0x004) // OUT Data Buffer Overrun Interrupt Flag
626#define USBEPnISR_ITRXIF (0x008) // IN Token Received Interrupt Flag
627#define USBEPnISR_IDTXIF (0x010) // IN Data Transmitted Interrupt Flag
628#define USBEPnISR_NAKIF (0x020) // NAK Transmitted Interrupt Flag
629#define USBEPnISR_STLIF (0x040) // STALL Transmitted Interrupt Flag
630#define USBEPnISR_UERIF (0x080) // USB Error Interrupt Flag
631#define USBEPnISR_STRXIF (0x100) // SETUP Token Received Interrupt Flag
632#define USBEPnISR_SDRXIF (0x200) // SETUP Data Received Interrupt Flag
633#define USBEPnISR_SDERIF (0x400) // SETUP Data Error Interrupt Flag
634#define USBEPnISR_ZLRXIF (0x800) // Zero Length Data Received Interrupt Flag
635
636// USBEPnTCR
637#define USBEPnTCR_TCNT (0x1FF) // Transfer Byte Count
638
639// USBEPnCFGR
640#define USBEPnCFGR_EPEN (1U << 31) // Endpoint Enable
641#define USBEPnCFGR_EPTYPE (1U << 29) // Transfer Type
642#define USBEPnCFGR_EPDIR (1U << 28) // Transfer Direction
643#define USBEPnCFGR_EPADR (0xFU << 24) // Endpoint Address
644#define USBEPnCFGR_EPLEN (0x7FU << 10) // Buffer Length
645#define USBEPnCFGR_EPBUFA (0x3FF) // Endpoint Buffer Address
646
647// Peripheral Direct Memory Access
648// /////////////////////////////////////////////////////////////////////////////
649
650// Extend Bus Interface
651// /////////////////////////////////////////////////////////////////////////////
652
653// Inter-IC Sound
654// /////////////////////////////////////////////////////////////////////////////
655
656// CRC
657// /////////////////////////////////////////////////////////////////////////////
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 23:02:28 +0100