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diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/k20x7.h b/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/k20x7.h
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1/*
2 * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23#ifndef _K20x7_H_
24#define _K20x7_H_
25
26/*
27 * ==============================================================
28 * ---------- Interrupt Number Definition -----------------------
29 * ==============================================================
30 */
31typedef enum IRQn
32{
33/****** Cortex-M0 Processor Exceptions Numbers ****************/
34 InitialSP_IRQn = -15,
35 InitialPC_IRQn = -15,
36 NonMaskableInt_IRQn = -14,
37 HardFault_IRQn = -13,
38 MemoryManagement_IRQn = -12,
39 BusFault_IRQn = -11,
40 UsageFault_IRQn = -10,
41 SVCall_IRQn = -5,
42 DebugMonitor_IRQn = -4,
43 PendSV_IRQn = -2,
44 SysTick_IRQn = -1,
45
46/****** K20x Specific Interrupt Numbers ***********************/
47 DMA0_IRQn = 0, // Vector40
48 DMA1_IRQn = 1, // Vector44
49 DMA2_IRQn = 2, // Vector48
50 DMA3_IRQn = 3, // Vector4C
51 DMA4_IRQn = 4, // Vector50
52 DMA5_IRQn = 5, // Vector54
53 DMA6_IRQn = 6, // Vector58
54 DMA7_IRQn = 7, // Vector5C
55 DMA8_IRQn = 8, // Vector60
56 DMA9_IRQn = 9, // Vector64
57 DMA10_IRQn = 10, // Vector68
58 DMA11_IRQn = 11, // Vector6C
59 DMA12_IRQn = 12, // Vector70
60 DMA13_IRQn = 13, // Vector74
61 DMA14_IRQn = 14, // Vector78
62 DMA15_IRQn = 15, // Vector7C
63 DMAError_IRQn = 16, // Vector80
64 //~ DMA_IRQn = 17, // Vector84
65 FlashMemComplete_IRQn = 18, // Vector88
66 FlashMemReadCollision_IRQn = 19, // Vector8C
67 LowVoltageWarning_IRQn = 20, // Vector90
68 LLWU_IRQn = 21, // Vector94
69 WDOG_IRQn = 22, // Vector98
70 I2C0_IRQn = 24, // VectorA0
71 I2C1_IRQn = 25, // VectorA4
72 SPI0_IRQn = 26, // VectorA8
73 SPI1_IRQn = 27, // VectorAC
74 CANMessage_IRQn = 29, // VectorB4
75 CANBusOff = 30, // VectorB8
76 CANError = 31, // VectorBC
77 CANTxWarning = 32, // VectorC0
78 CANRxWarning = 33, // VectorC4
79 CANWakeUp = 34, // VectorC8
80 I2S0Tx_IRQn = 35, // VectorCC
81 I2S1Rx_IRQn = 36, // VectorD0
82 UART0LON_IRQn = 44, // VectorF0
83 UART0Status_IRQn = 45, // VectorF4
84 UART0Error_IRQn = 46, // VectorF8
85 UART1Status_IRQn = 47, // VectorFC
86 UART1Error_IRQn = 48, // Vector100
87 UART2Status_IRQn = 49, // Vector104
88 UART2Error_IRQn = 50, // Vector108
89 ADC0_IRQn = 57, // Vector124
90 ADC1_IRQn = 58, // Vector128
91 CMP0_IRQn = 59, // Vector12C
92 CMP1_IRQn = 60, // Vector130
93 CMP2_IRQn = 61, // Vector134
94 FTM0_IRQn = 62, // Vector138
95 FTM1_IRQn = 63, // Vector13C
96 FTM2_IRQn = 64, // Vector140
97 CMT_IRQn = 65, // Vector144
98 RTCAlarm_IRQn = 66, // Vector148
99 RTCSeconds_IRQn = 67, // Vector14C
100 PITChannel0_IRQn = 68, // Vector150
101 PITChannel1_IRQn = 69, // Vector154
102 PITChannel2_IRQn = 70, // Vector158
103 PITChannel3_IRQn = 71, // Vector15C
104 PDB_IRQn = 72, // Vector160
105 USB_OTG_IRQn = 73, // Vector164
106 USBChargerDetect_IRQn = 74, // Vector168
107 DAC0_IRQn = 81, // Vector184
108 TSI_IRQn = 83, // Vector18C
109 MCG_IRQn = 84, // Vector190
110 LPTMR0_IRQn = 85, // Vector194
111 PINA_IRQn = 87, // Vector19C
112 PINB_IRQn = 88, // Vector1A0
113 PINC_IRQn = 89, // Vector1A4
114 PIND_IRQn = 90, // Vector1A8
115 PINE_IRQn = 91, // Vector1AC
116 SoftInitInt_IRQn = 94, // Vector1B8
117} IRQn_Type;
118
119/*
120 * ==========================================================================
121 * ----------- Processor and Core Peripheral Section ------------------------
122 * ==========================================================================
123 */
124
125/**
126 * @brief K20x Interrupt Number Definition, according to the selected device
127 * in @ref Library_configuration_section
128 */
129#define __FPU_PRESENT 0
130#define __MPU_PRESENT 0
131#define __NVIC_PRIO_BITS 4
132#define __Vendor_SysTickConfig 0
133
134#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
135
136#include "k20xx.h"
137
138typedef struct
139{
140 __IO uint32_t SOPT1;
141 __IO uint32_t SOPT1CFG;
142 uint32_t RESERVED0[1023];
143 __IO uint32_t SOPT2;
144 uint32_t RESERVED1[1];
145 __IO uint32_t SOPT4;
146 __IO uint32_t SOPT5;
147 uint32_t RESERVED2[1];
148 __IO uint32_t SOPT7;
149 uint32_t RESERVED3[2];
150 __I uint32_t SDID;
151 uint32_t RESERVED4[1];
152 __IO uint32_t SCGC2;
153 __IO uint32_t SCGC3;
154 __IO uint32_t SCGC4;
155 __IO uint32_t SCGC5;
156 __IO uint32_t SCGC6;
157 __IO uint32_t SCGC7;
158 __IO uint32_t CLKDIV1;
159 __IO uint32_t CLKDIV2;
160 __I uint32_t FCFG1;
161 __I uint32_t FCFG2;
162 __I uint32_t UIDH;
163 __I uint32_t UIDMH;
164 __I uint32_t UIDML;
165 __I uint32_t UIDL;
166} SIM_TypeDef;
167
168/****************************************************************/
169/* Peripheral memory map */
170/****************************************************************/
171#define AXBS_BASE ((uint32_t)0x40004000) //
172#define DMA_BASE ((uint32_t)0x40008000)
173#define FTFL_BASE ((uint32_t)0x40020000)
174#define DMAMUX_BASE ((uint32_t)0x40021000)
175#define FCAN0_BASE ((uint32_t)0x40024000) //
176#define SPI0_BASE ((uint32_t)0x4002C000)
177#define SPI1_BASE ((uint32_t)0x4002D000) //
178#define I2S0_BASE ((uint32_t)0x4002F000) //
179#define USBDCD_BASE ((uint32_t)0x40035000) //
180#define PDB_BASE ((uint32_t)0x40036000) //
181#define PIT_BASE ((uint32_t)0x40037000)
182#define FTM0_BASE ((uint32_t)0x40038000)
183#define FTM1_BASE ((uint32_t)0x40039000)
184#define ADC0_BASE ((uint32_t)0x4003B000)
185#define RTC_BASE ((uint32_t)0x4003D000) //
186#define VBAT_BASE ((uint32_t)0x4003E000)
187#define LPTMR0_BASE ((uint32_t)0x40040000)
188#define SRF_BASE ((uint32_t)0x40041000)
189#define TSI0_BASE ((uint32_t)0x40045000)
190#define SIM_BASE ((uint32_t)0x40047000)
191#define PORTA_BASE ((uint32_t)0x40049000)
192#define PORTB_BASE ((uint32_t)0x4004A000)
193#define PORTC_BASE ((uint32_t)0x4004B000)
194#define PORTD_BASE ((uint32_t)0x4004C000)
195#define PORTE_BASE ((uint32_t)0x4004D000)
196#define WDOG_BASE ((uint32_t)0x40052000)
197#define EWDOG_BASE ((uint32_t)0x40061000) //
198#define CMT_BASE ((uint32_t)0x40062000) //
199#define MCG_BASE ((uint32_t)0x40064000)
200#define OSC0_BASE ((uint32_t)0x40065000)
201#define I2C0_BASE ((uint32_t)0x40066000)
202#define I2C1_BASE ((uint32_t)0x40067000) //
203#define UART0_BASE ((uint32_t)0x4006A000)
204#define UART1_BASE ((uint32_t)0x4006B000)
205#define UART2_BASE ((uint32_t)0x4006C000)
206#define USBOTG_BASE ((uint32_t)0x40072000)
207#define CMP0_BASE ((uint32_t)0x40073000) //
208#define VREF_BASE ((uint32_t)0x40074000) //
209#define LLWU_BASE ((uint32_t)0x4007C000)
210#define PMC_BASE ((uint32_t)0x4007D000)
211#define SMC_BASE ((uint32_t)0x4007E000) //
212#define RCM_BASE ((uint32_t)0x4007F000) //
213#define FTM2_BASE ((uint32_t)0x400B8000) //
214#define ADC1_BASE ((uint32_t)0x400BB000) //
215#define DAC0_BASE ((uint32_t)0x400CC000) //
216#define GPIOA_BASE ((uint32_t)0x400FF000)
217#define GPIOB_BASE ((uint32_t)0x400FF040)
218#define GPIOC_BASE ((uint32_t)0x400FF080)
219#define GPIOD_BASE ((uint32_t)0x400FF0C0)
220#define GPIOE_BASE ((uint32_t)0x400FF100)
221
222/****************************************************************/
223/* Peripheral declaration */
224/****************************************************************/
225#define DMA ((DMA_TypeDef *) DMA_BASE)
226#define FTFL ((FTFL_TypeDef *) FTFL_BASE)
227#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
228#define PIT ((PIT_TypeDef *) PIT_BASE)
229#define FTM0 ((FTM_TypeDef *) FTM0_BASE)
230#define FTM1 ((FTM_TypeDef *) FTM1_BASE)
231#define FTM2 ((FTM_TypeDef *) FTM2_BASE)
232#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
233#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
234#define VBAT ((volatile uint8_t *)VBAT_BASE) /* 32 bytes */
235#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
236#define SYSTEM_REGISTER_FILE ((volatile uint8_t *)SRF_BASE) /* 32 bytes */
237#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
238#define SIM ((SIM_TypeDef *) SIM_BASE)
239#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
240#define PMC ((PMC_TypeDef *) PMC_BASE)
241#define PORTA ((PORT_TypeDef *) PORTA_BASE)
242#define PORTB ((PORT_TypeDef *) PORTB_BASE)
243#define PORTC ((PORT_TypeDef *) PORTC_BASE)
244#define PORTD ((PORT_TypeDef *) PORTD_BASE)
245#define PORTE ((PORT_TypeDef *) PORTE_BASE)
246#define WDOG ((WDOG_TypeDef *) WDOG_BASE)
247#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE)
248#define MCG ((MCG_TypeDef *) MCG_BASE)
249#define OSC0 ((OSC_TypeDef *) OSC0_BASE)
250#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
251#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
252#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
253#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
254#define UART0 ((UART_TypeDef *) UART0_BASE)
255#define UART1 ((UART_TypeDef *) UART1_BASE)
256#define UART2 ((UART_TypeDef *) UART2_BASE)
257#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
258#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
259#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
260#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
261#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
262
263/****************************************************************/
264/* Peripheral Registers Bits Definition */
265/****************************************************************/
266
267/****************************************************************/
268/* */
269/* System Integration Module (SIM) */
270/* */
271/****************************************************************/
272/********* Bits definition for SIM_SOPT1 register *************/
273#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
274#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
275#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
276#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
277#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x3 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
278#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
279#define SIM_SOPT1_RAMSIZE_SHIFT 12
280#define SIM_SOPT1_RAMSIZE_MASK ((uint32_t)((uint32_t)0xf << SIM_SOPT1_RAMSIZE_SHIFT))
281#define SIM_SOPT1_RAMSIZE(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_RAMSIZE_SHIFT) & SIM_SOPT1_RAMSIZE_MASK))
282
283/******* Bits definition for SIM_SOPT1CFG register ************/
284#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
285#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
286#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
287
288/******* Bits definition for SIM_SOPT2 register ************/
289#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
290#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
291#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000)
292#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800)
293#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
294#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x7 << SIM_SOPT2_CLKOUTSEL_SHIFT))
295#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK))
296#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
297
298/******* Bits definition for SIM_SCGC2 register ************/
299#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) /*!< DAC0 Clock Gate Control */
300
301/******* Bits definition for SIM_SCGC3 register ************/
302#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) /*!< ADC1 Clock Gate Control */
303#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) /*!< FTM2 Clock Gate Control */
304
305/******* Bits definition for SIM_SCGC4 register ************/
306#define SIM_SCGC4_VREF ((uint32_t)0x00100000) /*!< VREF Clock Gate Control */
307#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
308#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
309#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
310#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
311#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
312#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */
313#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
314#define SIM_SCGC4_CMT ((uint32_t)0x00000004) /*!< CMT Clock Gate Control */
315#define SIM_SCGC4_EMW ((uint32_t)0x00000002) /*!< EWM Clock Gate Control */
316
317/******* Bits definition for SIM_SCGC5 register ************/
318#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
319#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
320#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
321#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
322#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
323#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
324#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
325
326/******* Bits definition for SIM_SCGC6 register ************/
327#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */
328#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */
329#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) /*!< FTM1 Clock Gate Control */
330#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) /*!< FTM0 Clock Gate Control */
331#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */
332#define SIM_SCGC6_PDB ((uint32_t)0x00400000) /*!< PDB Clock Gate Control */
333#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) /*!< USB DCD Clock Gate Control */
334#define SIM_SCGC6_CRC ((uint32_t)0x00040000) /*!< Low Power Timer Access Control */
335#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< CRC Clock Gate Control */
336#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) /*!< SPI1 Clock Gate Control */
337#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) /*!< SPI0 Clock Gate Control */
338#define SIM_SCGC6_FCAN0 ((uint32_t)0x00000010) /*!< FlexCAN 0 Clock Gate Control */
339#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */
340#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */
341
342/******* Bits definition for SIM_SCGC6 register ************/
343#define SIM_SCGC7_DMA ((uint32_t)0x00000002) /*!< DMA Clock Gate Control */
344
345/****** Bits definition for SIM_CLKDIV1 register ***********/
346#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
347#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV1_SHIFT))
348#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK))
349#define SIM_CLKDIV1_OUTDIV2_SHIFT 24
350#define SIM_CLKDIV1_OUTDIV2_MASK ((uint32_t)((uint32_t)0xF << SIM_CLKDIV1_OUTDIV2_SHIFT))
351#define SIM_CLKDIV1_OUTDIV2(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV2_SHIFT) & SIM_CLKDIV1_OUTDIV2_MASK))
352#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
353#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV1_OUTDIV4_SHIFT))
354#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK))
355
356/****** Bits definition for SIM_CLKDIV2 register ***********/
357#define SIM_CLKDIV2_USBDIV_SHIFT 1
358#define SIM_CLKDIV2_USBDIV_MASK ((uint32_t)((uint32_t)0x7 << SIM_CLKDIV2_USBDIV_SHIFT))
359#define SIM_CLKDIV2_USBDIV(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV2_USBDIV_SHIFT) & SIM_CLKDIV2_USBDIV_MASK))
360#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x00000001)
361
362#endif
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:05:07 +0100