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diff --git a/lib/chibios-contrib/os/hal/include/hal_fsmc.h b/lib/chibios-contrib/os/hal/include/hal_fsmc.h
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1/*
2 ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
3
4 Licensed under the Apache License, Version 2.0 (the "License");
5 you may not use this file except in compliance with the License.
6 You may obtain a copy of the License at
7
8 http://www.apache.org/licenses/LICENSE-2.0
9
10 Unless required by applicable law or agreed to in writing, software
11 distributed under the License is distributed on an "AS IS" BASIS,
12 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13 See the License for the specific language governing permissions and
14 limitations under the License.
15*/
16
17/**
18 * @file hal_fsmc.h
19 * @brief FSMC Driver subsystem low level driver header.
20 *
21 * @addtogroup FSMC
22 * @{
23 */
24
25#ifndef HAL_FSMC_H_
26#define HAL_FSMC_H_
27
28#include "hal.h"
29
30#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__)
31
32/*===========================================================================*/
33/* Driver constants. */
34/*===========================================================================*/
35
36/*
37 * (Re)define if needed base address constants supplied in ST's CMSIS
38 */
39#if (defined(STM32F427xx) || defined(STM32F437xx) || \
40 defined(STM32F429xx) || defined(STM32F439xx) || \
41 defined(STM32F722xx) || defined(STM32F723xx) || \
42 defined(STM32F732xx) || defined(STM32F733xx) || \
43 defined(STM32F745xx) || defined(STM32F746xx) || \
44 defined(STM32F756xx) || defined(STM32F767xx) || \
45 defined(STM32F769xx) || defined(STM32F777xx) || \
46 defined(STM32F779xx))
47 #if !defined(FSMC_Bank1_R_BASE)
48 #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000)
49 #endif
50 #if !defined(FSMC_Bank1E_R_BASE)
51 #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104)
52 #endif
53 #if !defined(FSMC_Bank2_R_BASE)
54 #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060)
55 #endif
56 #if !defined(FSMC_Bank3_R_BASE)
57 #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080)
58 #endif
59 #if !defined(FSMC_Bank4_R_BASE)
60 #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0)
61 #endif
62 #if !defined(FSMC_Bank5_R_BASE)
63 #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140)
64 #endif
65#else
66 #if !defined(FSMC_Bank1_R_BASE)
67 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000)
68 #endif
69 #if !defined(FSMC_Bank1E_R_BASE)
70 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104)
71 #endif
72 #if !defined(FSMC_Bank2_R_BASE)
73 #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060)
74 #endif
75 #if !defined(FSMC_Bank3_R_BASE)
76 #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080)
77 #endif
78 #if !defined(FSMC_Bank4_R_BASE)
79 #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0)
80 #endif
81#endif
82
83/*
84 * Base bank mappings
85 */
86#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000)
87#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000)
88#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000)
89#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000)
90#if (defined(STM32F427xx) || defined(STM32F437xx) || \
91 defined(STM32F429xx) || defined(STM32F439xx) || \
92 defined(STM32F7))
93 #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000)
94 #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000)
95#endif
96
97/*
98 * Subbunks of bank1
99 */
100#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64)
101#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE)
102#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET)
103#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET)
104#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET)
105
106/*
107 * Bank 2 (NAND)
108 */
109#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0)
110#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000)
111
112#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0)
113#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000)
114#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000)
115
116#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0)
117#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000)
118#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000)
119
120/*
121 * Bank 3 (NAND)
122 */
123#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0)
124#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000)
125
126#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0)
127#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000)
128#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000)
129
130#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0)
131#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000)
132#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000)
133
134/*
135 * Bank 4 (PC card)
136 */
137#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0)
138#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000)
139#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000)
140
141/*
142 * More convenient typedefs than CMSIS has
143 */
144typedef struct {
145 __IO uint32_t PCR; /**< NAND Flash control */
146 __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */
147 __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */
148 __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */
149 uint32_t RESERVED0; /**< Reserved, 0x70 */
150 __IO uint32_t ECCR; /**< NAND Flash ECC result registers */
151} FSMC_NAND_TypeDef;
152
153typedef struct {
154 __IO uint32_t PCR; /**< PC Card control */
155 __IO uint32_t SR; /**< PC Card FIFO status and interrupt */
156 __IO uint32_t PMEM; /**< PC Card Common memory space timing */
157 __IO uint32_t PATT; /**< PC Card Attribute memory space timing */
158 __IO uint32_t PIO; /**< PC Card I/O space timing */
159} FSMC_PCCard_TypeDef;
160
161typedef struct {
162 __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */
163 __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */
164 uint32_t RESERVED[63]; /**< Reserved */
165 __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */
166} FSMC_SRAM_TypeDef;
167
168#if (defined(STM32F427xx) || defined(STM32F437xx) || \
169 defined(STM32F429xx) || defined(STM32F439xx) || \
170 defined(STM32F7))
171
172typedef struct {
173 __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */
174 __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */
175 __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */
176 __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */
177 __IO uint32_t SDCMR; /**< SDRAM comand mode register */
178 __IO uint32_t SDRTR; /**< SDRAM refresh timer register */
179 __IO uint32_t SDSR; /**< SDRAM status register */
180} FSMC_SDRAM_TypeDef;
181
182#endif
183
184/**
185 * @brief PCR register
186 */
187#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1)
188#define FSMC_PCR_PBKEN ((uint32_t)1 << 2)
189#define FSMC_PCR_PTYP ((uint32_t)1 << 3)
190#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4)
191#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4)
192#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4)
193#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4)
194#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4)
195#define FSMC_PCR_ECCEN ((uint32_t)1 << 6)
196#define FSMC_PCR_PTYP_PCCARD 0
197#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP
198
199/**
200 * @brief SR register
201 */
202#define FSMC_SR_IRS ((uint8_t)0x01)
203#define FSMC_SR_ILS ((uint8_t)0x02)
204#define FSMC_SR_IFS ((uint8_t)0x04)
205#define FSMC_SR_IREN ((uint8_t)0x08)
206#define FSMC_SR_ILEN ((uint8_t)0x10)
207#define FSMC_SR_IFEN ((uint8_t)0x20)
208#define FSMC_SR_FEMPT ((uint8_t)0x40)
209#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS)
210
211/**
212 * @brief BCR register
213 */
214#define FSMC_BCR_MBKEN ((uint32_t)1 << 0)
215#define FSMC_BCR_MUXEN ((uint32_t)1 << 1)
216#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2)
217#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2)
218#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2)
219#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2)
220#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4)
221#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4)
222#if (defined(STM32F427xx) || defined(STM32F437xx) || \
223 defined(STM32F429xx) || defined(STM32F439xx) || \
224 defined(STM32F7))
225#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4)
226#else
227#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4)
228#endif
229#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4)
230#define FSMC_BCR_FACCEN ((uint32_t)1 << 6)
231#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8)
232#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9)
233#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10)
234#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11)
235#define FSMC_BCR_WREN ((uint32_t)1 << 12)
236#define FSMC_BCR_WAITEN ((uint32_t)1 << 13)
237#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14)
238#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15)
239#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19)
240#if (defined(STM32F427xx) || defined(STM32F437xx) || \
241 defined(STM32F429xx) || defined(STM32F439xx) || \
242 defined(STM32F7))
243#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20)
244#endif
245#if (defined(STM32F7))
246#define FSMC_BCR_WFDIS ((uint32_t)1 << 21)
247#endif
248
249/*===========================================================================*/
250/* Driver pre-compile time settings. */
251/*===========================================================================*/
252
253#if !defined(STM32_DMA_REQUIRED)
254#define STM32_DMA_REQUIRED
255#endif
256
257/**
258 * @name Configuration options
259 * @{
260 */
261
262/**
263 * @brief FSMC driver enable switch.
264 * @details If set to @p TRUE the support for FSMC is included.
265 */
266#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__)
267#define STM32_FSMC_USE_FSMC1 FALSE
268#endif
269
270/** @} */
271
272/*===========================================================================*/
273/* Derived constants and error checks. */
274/*===========================================================================*/
275#if !STM32_FSMC_USE_FSMC1
276#error "FSMC driver activated but no FSMC peripheral assigned"
277#endif
278
279/*===========================================================================*/
280/* Driver data structures and types. */
281/*===========================================================================*/
282
283/**
284 * @brief Type of a structure representing an FSMC driver.
285 */
286typedef struct FSMCDriver FSMCDriver;
287
288/**
289 * @brief Driver state machine possible states.
290 */
291typedef enum {
292 FSMC_UNINIT = 0, /**< Not initialized. */
293 FSMC_STOP = 1, /**< Stopped. */
294 FSMC_READY = 2, /**< Ready. */
295} fsmcstate_t;
296
297/**
298 * @brief Structure representing an FSMC driver.
299 */
300struct FSMCDriver {
301 /**
302 * @brief Driver state.
303 */
304 fsmcstate_t state;
305 /* End of the mandatory fields.*/
306
307#if HAL_USE_SRAM
308 #if STM32_SRAM_USE_SRAM1
309 FSMC_SRAM_TypeDef *sram1;
310 #endif
311 #if STM32_SRAM_USE_SRAM2
312 FSMC_SRAM_TypeDef *sram2;
313 #endif
314 #if STM32_SRAM_USE_SRAM3
315 FSMC_SRAM_TypeDef *sram3;
316 #endif
317 #if STM32_SRAM_USE_SRAM4
318 FSMC_SRAM_TypeDef *sram4;
319 #endif
320#endif
321
322#if HAL_USE_NAND
323 #if STM32_NAND_USE_NAND1
324 FSMC_NAND_TypeDef *nand1;
325 #endif
326 #if STM32_NAND_USE_NAND2
327 FSMC_NAND_TypeDef *nand2;
328 #endif
329#endif
330
331#if (defined(STM32F427xx) || defined(STM32F437xx) || \
332 defined(STM32F429xx) || defined(STM32F439xx) || \
333 defined(STM32F7))
334 #if HAL_USE_SDRAM
335 FSMC_SDRAM_TypeDef *sdram;
336 #endif
337#endif
338};
339
340/*===========================================================================*/
341/* Driver macros. */
342/*===========================================================================*/
343
344/*===========================================================================*/
345/* External declarations. */
346/*===========================================================================*/
347
348#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__)
349extern FSMCDriver FSMCD1;
350#endif
351
352#ifdef __cplusplus
353extern "C" {
354#endif
355 void fsmcInit(void);
356 void fsmcStart(FSMCDriver *fsmcp);
357 void fsmcStop(FSMCDriver *fsmcp);
358#ifdef __cplusplus
359}
360#endif
361
362#endif /* HAL_USE_FSMC */
363
364#endif /* HAL_FSMC_H_ */
365
366/** @} */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 21:01:40 +0100