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Diffstat (limited to 'lib/chibios-contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h')
| -rw-r--r-- | lib/chibios-contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 912 |
1 files changed, 912 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/lib/chibios-contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h new file mode 100644 index 000000000..8f2aacff3 --- /dev/null +++ b/lib/chibios-contrib/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | |||
| @@ -0,0 +1,912 @@ | |||
| 1 | /* | ||
| 2 | Copyright (C) 2014..2017 Marco Veeneman | ||
| 3 | |||
| 4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
| 5 | you may not use this file except in compliance with the License. | ||
| 6 | You may obtain a copy of the License at | ||
| 7 | |||
| 8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
| 9 | |||
| 10 | Unless required by applicable law or agreed to in writing, software | ||
| 11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
| 12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
| 13 | See the License for the specific language governing permissions and | ||
| 14 | limitations under the License. | ||
| 15 | */ | ||
| 16 | |||
| 17 | #ifndef BOARD_H | ||
| 18 | #define BOARD_H | ||
| 19 | |||
| 20 | /* | ||
| 21 | * Setup for Texas Instruments TM4C123G Launchpad Board. | ||
| 22 | */ | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Board identifier. | ||
| 26 | */ | ||
| 27 | #define BOARD_TI_TM4C123G_LAUNCHPAD | ||
| 28 | #define BOARD_NAME "Texas Instruments TM4C123G Launchpad" | ||
| 29 | |||
| 30 | /* | ||
| 31 | * MCU type and revision as defined in the TI header. | ||
| 32 | */ | ||
| 33 | #define PART_TM4C123GH6PM | ||
| 34 | #define TARGET_IS_TM4C123_RB1 | ||
| 35 | |||
| 36 | /* | ||
| 37 | * Board oscillators-related settings. | ||
| 38 | */ | ||
| 39 | #define TIVA_XTAL_VALUE 16000000 | ||
| 40 | |||
| 41 | /* | ||
| 42 | * IO pins assignments. | ||
| 43 | */ | ||
| 44 | #define GPIOA_UART0_RX 0 | ||
| 45 | #define GPIOA_UART0_TX 1 | ||
| 46 | #define GPIOA_SSI0_CLK 2 | ||
| 47 | #define GPIOA_PIN3 3 | ||
| 48 | #define GPIOA_SSI0_RX 4 | ||
| 49 | #define GPIOA_SSI0_TX 5 | ||
| 50 | #define GPIOA_PIN6 6 | ||
| 51 | #define GPIOA_PIN7 7 | ||
| 52 | |||
| 53 | #define GPIOB_PIN0 0 | ||
| 54 | #define GPIOB_PIN1 1 | ||
| 55 | #define GPIOB_I2C0_SCL 2 | ||
| 56 | #define GPIOB_I2C0_SDA 3 | ||
| 57 | #define GPIOB_PIN4 4 | ||
| 58 | #define GPIOB_PIN5 5 | ||
| 59 | #define GPIOB_PIN6 6 | ||
| 60 | #define GPIOB_PIN7 7 | ||
| 61 | |||
| 62 | #define GPIOC_TCK_SWCLK 0 | ||
| 63 | #define GPIOC_TMS_SWDIO 1 | ||
| 64 | #define GPIOC_TDI 2 | ||
| 65 | #define GPIOC_TDO_SWO 3 | ||
| 66 | #define GPIOC_PIN4 4 | ||
| 67 | #define GPIOC_PIN5 5 | ||
| 68 | #define GPIOC_PIN6 6 | ||
| 69 | #define GPIOC_PIN7 7 | ||
| 70 | |||
| 71 | #define GPIOD_PIN0 0 | ||
| 72 | #define GPIOD_PIN1 1 | ||
| 73 | #define GPIOD_PIN2 2 | ||
| 74 | #define GPIOD_PIN3 3 | ||
| 75 | #define GPIOD_PIN4 4 | ||
| 76 | #define GPIOD_PIN5 5 | ||
| 77 | #define GPIOD_PIN6 6 | ||
| 78 | #define GPIOD_PIN7 7 | ||
| 79 | |||
| 80 | #define GPIOE_PIN0 0 | ||
| 81 | #define GPIOE_PIN1 1 | ||
| 82 | #define GPIOE_PIN2 2 | ||
| 83 | #define GPIOE_PIN3 3 | ||
| 84 | #define GPIOE_PIN4 4 | ||
| 85 | #define GPIOE_PIN5 5 | ||
| 86 | #define GPIOE_PIN6 6 | ||
| 87 | #define GPIOE_PIN7 7 | ||
| 88 | |||
| 89 | #define GPIOF_SW2 0 | ||
| 90 | #define GPIOF_LED_RED 1 | ||
| 91 | #define GPIOF_LED_BLUE 2 | ||
| 92 | #define GPIOF_LED_GREEN 3 | ||
| 93 | #define GPIOF_SW1 4 | ||
| 94 | #define GPIOF_PIN5 5 | ||
| 95 | #define GPIOF_PIN6 6 | ||
| 96 | #define GPIOF_PIN7 7 | ||
| 97 | |||
| 98 | /* | ||
| 99 | * IO lines assignments. | ||
| 100 | */ | ||
| 101 | #define LINE_UART0_RX PAL_LINE(GPIOA, 0U) | ||
| 102 | #define LINE_UART0_TX PAL_LINE(GPIOA, 1U) | ||
| 103 | #define LINE_SSI0_CLK PAL_LINE(GPIOA, 2U) | ||
| 104 | #define LINE_SSI0_RX PAL_LINE(GPIOA, 4U) | ||
| 105 | #define LINE_SSI0_TX PAL_LINE(GPIOA, 5U) | ||
| 106 | |||
| 107 | #define LINE_I2C0_SCL PAL_LINE(GPIOB, 2U) | ||
| 108 | #define LINE_I2C0_SDA PAL_LINE(GPIOB, 3U) | ||
| 109 | |||
| 110 | #define LINE_SW2 PAL_LINE(GPIOF, 0U) | ||
| 111 | #define LINE_LED_RED PAL_LINE(GPIOF, 1U) | ||
| 112 | #define LINE_LED_BLUE PAL_LINE(GPIOF, 2U) | ||
| 113 | #define LINE_LED_GREEN PAL_LINE(GPIOF, 3U) | ||
| 114 | #define LINE_SW1 PAL_LINE(GPIOF, 4U) | ||
| 115 | |||
| 116 | /* | ||
| 117 | * I/O ports initial setup, this configuration is established soon after reset | ||
| 118 | * in the initialization code. | ||
| 119 | */ | ||
| 120 | #define PIN_DATA_LOW(n) (0U << (n)) | ||
| 121 | #define PIN_DATA_HIGH(n) (1U << (n)) | ||
| 122 | |||
| 123 | #define PIN_DIR_IN(n) (0U << (n)) | ||
| 124 | #define PIN_DIR_OUT(n) (1U << (n)) | ||
| 125 | |||
| 126 | #define PIN_AFSEL_GPIO(n) (0U << (n)) | ||
| 127 | #define PIN_AFSEL_ALTERNATE(n) (1U << (n)) | ||
| 128 | |||
| 129 | #define PIN_ODR_DISABLE(n) (0U << (n)) | ||
| 130 | #define PIN_ODR_ENABLE(n) (1U << (n)) | ||
| 131 | |||
| 132 | #define PIN_PxR_DISABLE(n) (0U << (n)) | ||
| 133 | #define PIN_PxR_ENABLE(n) (1U << (n)) | ||
| 134 | |||
| 135 | #define PIN_DEN_DISABLE(n) (0U << (n)) | ||
| 136 | #define PIN_DEN_ENABLE(n) (1U << (n)) | ||
| 137 | |||
| 138 | #define PIN_AMSEL_DISABLE(n) (0U << (n)) | ||
| 139 | #define PIN_AMSEL_ENABLE(n) (1U << (n)) | ||
| 140 | |||
| 141 | #define PIN_DRxR_DISABLE(n) (0U << (n)) | ||
| 142 | #define PIN_DRxR_ENABLE(n) (1U << (n)) | ||
| 143 | |||
| 144 | #define PIN_SLR_DISABLE(n) (0U << (n)) | ||
| 145 | #define PIN_SLR_ENABLE(n) (1U << (n)) | ||
| 146 | |||
| 147 | #define PIN_PCTL_MODE(n, mode) (mode << ((n) * 4)) | ||
| 148 | |||
| 149 | /* | ||
| 150 | * GPIOA Setup: | ||
| 151 | * | ||
| 152 | * PA0 - UART0 RX () | ||
| 153 | * PA1 - UART0 TX () | ||
| 154 | * PA2 - PIN2 () | ||
| 155 | * PA3 - PIN3 () | ||
| 156 | * PA4 - PIN4 () | ||
| 157 | * PA5 - PIN5 () | ||
| 158 | * PA6 - PIN6 () | ||
| 159 | * PA7 - PIN7 () | ||
| 160 | */ | ||
| 161 | #define VAL_GPIOA_DATA (PIN_DATA_LOW(GPIOA_UART0_RX) | \ | ||
| 162 | PIN_DATA_LOW(GPIOA_UART0_TX) | \ | ||
| 163 | PIN_DATA_LOW(GPIOA_SSI0_CLK) | \ | ||
| 164 | PIN_DATA_LOW(GPIOA_PIN3) | \ | ||
| 165 | PIN_DATA_LOW(GPIOA_SSI0_RX) | \ | ||
| 166 | PIN_DATA_LOW(GPIOA_SSI0_TX) | \ | ||
| 167 | PIN_DATA_LOW(GPIOA_PIN6) | \ | ||
| 168 | PIN_DATA_LOW(GPIOA_PIN7)) | ||
| 169 | |||
| 170 | #define VAL_GPIOA_DIR (PIN_DIR_IN(GPIOA_UART0_RX) | \ | ||
| 171 | PIN_DIR_IN(GPIOA_UART0_TX) | \ | ||
| 172 | PIN_DIR_IN(GPIOA_SSI0_CLK) | \ | ||
| 173 | PIN_DIR_IN(GPIOA_PIN3) | \ | ||
| 174 | PIN_DIR_IN(GPIOA_SSI0_RX) | \ | ||
| 175 | PIN_DIR_IN(GPIOA_SSI0_TX) | \ | ||
| 176 | PIN_DIR_IN(GPIOA_PIN6) | \ | ||
| 177 | PIN_DIR_IN(GPIOA_PIN7)) | ||
| 178 | |||
| 179 | #define VAL_GPIOA_AFSEL (PIN_AFSEL_GPIO(GPIOA_UART0_RX) | \ | ||
| 180 | PIN_AFSEL_GPIO(GPIOA_UART0_TX) | \ | ||
| 181 | PIN_AFSEL_GPIO(GPIOA_SSI0_CLK) | \ | ||
| 182 | PIN_AFSEL_GPIO(GPIOA_PIN3) | \ | ||
| 183 | PIN_AFSEL_GPIO(GPIOA_SSI0_RX) | \ | ||
| 184 | PIN_AFSEL_GPIO(GPIOA_SSI0_TX) | \ | ||
| 185 | PIN_AFSEL_GPIO(GPIOA_PIN6) | \ | ||
| 186 | PIN_AFSEL_GPIO(GPIOA_PIN7)) | ||
| 187 | |||
| 188 | #define VAL_GPIOA_ODR (PIN_ODR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 189 | PIN_ODR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 190 | PIN_ODR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 191 | PIN_ODR_DISABLE(GPIOA_PIN3) | \ | ||
| 192 | PIN_ODR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 193 | PIN_ODR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 194 | PIN_ODR_DISABLE(GPIOA_PIN6) | \ | ||
| 195 | PIN_ODR_DISABLE(GPIOA_PIN7)) | ||
| 196 | |||
| 197 | #define VAL_GPIOA_PUR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 198 | PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 199 | PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 200 | PIN_PxR_DISABLE(GPIOA_PIN3) | \ | ||
| 201 | PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 202 | PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 203 | PIN_PxR_DISABLE(GPIOA_PIN6) | \ | ||
| 204 | PIN_PxR_DISABLE(GPIOA_PIN7)) | ||
| 205 | |||
| 206 | #define VAL_GPIOA_PDR (PIN_PxR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 207 | PIN_PxR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 208 | PIN_PxR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 209 | PIN_PxR_DISABLE(GPIOA_PIN3) | \ | ||
| 210 | PIN_PxR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 211 | PIN_PxR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 212 | PIN_PxR_DISABLE(GPIOA_PIN6) | \ | ||
| 213 | PIN_PxR_DISABLE(GPIOA_PIN7)) | ||
| 214 | |||
| 215 | #define VAL_GPIOA_DEN (PIN_DEN_ENABLE(GPIOA_UART0_RX) | \ | ||
| 216 | PIN_DEN_ENABLE(GPIOA_UART0_TX) | \ | ||
| 217 | PIN_DEN_ENABLE(GPIOA_SSI0_CLK) | \ | ||
| 218 | PIN_DEN_ENABLE(GPIOA_PIN3) | \ | ||
| 219 | PIN_DEN_ENABLE(GPIOA_SSI0_RX) | \ | ||
| 220 | PIN_DEN_ENABLE(GPIOA_SSI0_TX) | \ | ||
| 221 | PIN_DEN_ENABLE(GPIOA_PIN6) | \ | ||
| 222 | PIN_DEN_ENABLE(GPIOA_PIN7)) | ||
| 223 | |||
| 224 | #define VAL_GPIOA_AMSEL (PIN_AMSEL_DISABLE(GPIOA_UART0_RX) | \ | ||
| 225 | PIN_AMSEL_DISABLE(GPIOA_UART0_TX) | \ | ||
| 226 | PIN_AMSEL_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 227 | PIN_AMSEL_DISABLE(GPIOA_PIN3)) | ||
| 228 | |||
| 229 | #define VAL_GPIOA_DR2R (PIN_DRxR_ENABLE(GPIOA_UART0_RX) | \ | ||
| 230 | PIN_DRxR_ENABLE(GPIOA_UART0_TX) | \ | ||
| 231 | PIN_DRxR_ENABLE(GPIOA_SSI0_CLK) | \ | ||
| 232 | PIN_DRxR_ENABLE(GPIOA_PIN3) | \ | ||
| 233 | PIN_DRxR_ENABLE(GPIOA_SSI0_RX) | \ | ||
| 234 | PIN_DRxR_ENABLE(GPIOA_SSI0_TX) | \ | ||
| 235 | PIN_DRxR_ENABLE(GPIOA_PIN6) | \ | ||
| 236 | PIN_DRxR_ENABLE(GPIOA_PIN7)) | ||
| 237 | |||
| 238 | #define VAL_GPIOA_DR4R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 239 | PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 240 | PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 241 | PIN_DRxR_DISABLE(GPIOA_PIN3) | \ | ||
| 242 | PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 243 | PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 244 | PIN_DRxR_DISABLE(GPIOA_PIN6) | \ | ||
| 245 | PIN_DRxR_DISABLE(GPIOA_PIN7)) | ||
| 246 | |||
| 247 | #define VAL_GPIOA_DR8R (PIN_DRxR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 248 | PIN_DRxR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 249 | PIN_DRxR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 250 | PIN_DRxR_DISABLE(GPIOA_PIN3) | \ | ||
| 251 | PIN_DRxR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 252 | PIN_DRxR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 253 | PIN_DRxR_DISABLE(GPIOA_PIN6) | \ | ||
| 254 | PIN_DRxR_DISABLE(GPIOA_PIN7)) | ||
| 255 | |||
| 256 | |||
| 257 | #define VAL_GPIOA_SLR (PIN_SLR_DISABLE(GPIOA_UART0_RX) | \ | ||
| 258 | PIN_SLR_DISABLE(GPIOA_UART0_TX) | \ | ||
| 259 | PIN_SLR_DISABLE(GPIOA_SSI0_CLK) | \ | ||
| 260 | PIN_SLR_DISABLE(GPIOA_PIN3) | \ | ||
| 261 | PIN_SLR_DISABLE(GPIOA_SSI0_RX) | \ | ||
| 262 | PIN_SLR_DISABLE(GPIOA_SSI0_TX) | \ | ||
| 263 | PIN_SLR_DISABLE(GPIOA_PIN6) | \ | ||
| 264 | PIN_SLR_DISABLE(GPIOA_PIN7)) | ||
| 265 | |||
| 266 | #define VAL_GPIOA_PCTL (PIN_PCTL_MODE(GPIOA_UART0_RX, 0) | \ | ||
| 267 | PIN_PCTL_MODE(GPIOA_UART0_TX, 0) | \ | ||
| 268 | PIN_PCTL_MODE(GPIOA_SSI0_CLK, 0) | \ | ||
| 269 | PIN_PCTL_MODE(GPIOA_PIN3, 0) | \ | ||
| 270 | PIN_PCTL_MODE(GPIOA_SSI0_RX, 0) | \ | ||
| 271 | PIN_PCTL_MODE(GPIOA_SSI0_TX, 0) | \ | ||
| 272 | PIN_PCTL_MODE(GPIOA_PIN6, 0) | \ | ||
| 273 | PIN_PCTL_MODE(GPIOA_PIN7, 0)) | ||
| 274 | |||
| 275 | /* | ||
| 276 | * GPIOB Setup: | ||
| 277 | * | ||
| 278 | * PB0 - PIN0 () | ||
| 279 | * PB1 - PIN1 () | ||
| 280 | * PB2 - I2C0_SCL () | ||
| 281 | * PB3 - I2C0_SDA () | ||
| 282 | * PB4 - PIN4 () | ||
| 283 | * PB5 - PIN5 () | ||
| 284 | * PB6 - PIN6 () | ||
| 285 | * PB7 - PIN7 () | ||
| 286 | */ | ||
| 287 | #define VAL_GPIOB_DATA (PIN_DATA_LOW(GPIOB_PIN0) | \ | ||
| 288 | PIN_DATA_LOW(GPIOB_PIN1) | \ | ||
| 289 | PIN_DATA_LOW(GPIOB_I2C0_SCL) | \ | ||
| 290 | PIN_DATA_LOW(GPIOB_I2C0_SDA) | \ | ||
| 291 | PIN_DATA_LOW(GPIOB_PIN4) | \ | ||
| 292 | PIN_DATA_LOW(GPIOB_PIN5) | \ | ||
| 293 | PIN_DATA_LOW(GPIOB_PIN6) | \ | ||
| 294 | PIN_DATA_LOW(GPIOB_PIN7)) | ||
| 295 | |||
| 296 | #define VAL_GPIOB_DIR (PIN_DIR_IN(GPIOB_PIN0) | \ | ||
| 297 | PIN_DIR_IN(GPIOB_PIN1) | \ | ||
| 298 | PIN_DIR_IN(GPIOB_I2C0_SCL) | \ | ||
| 299 | PIN_DIR_IN(GPIOB_I2C0_SDA) | \ | ||
| 300 | PIN_DIR_IN(GPIOB_PIN4) | \ | ||
| 301 | PIN_DIR_IN(GPIOB_PIN5) | \ | ||
| 302 | PIN_DIR_IN(GPIOB_PIN6) | \ | ||
| 303 | PIN_DIR_IN(GPIOB_PIN7)) | ||
| 304 | |||
| 305 | #define VAL_GPIOB_AFSEL (PIN_AFSEL_GPIO(GPIOB_PIN0) | \ | ||
| 306 | PIN_AFSEL_GPIO(GPIOB_PIN1) | \ | ||
| 307 | PIN_AFSEL_GPIO(GPIOB_I2C0_SCL) | \ | ||
| 308 | PIN_AFSEL_GPIO(GPIOB_I2C0_SDA) | \ | ||
| 309 | PIN_AFSEL_GPIO(GPIOB_PIN4) | \ | ||
| 310 | PIN_AFSEL_GPIO(GPIOB_PIN5) | \ | ||
| 311 | PIN_AFSEL_GPIO(GPIOB_PIN6) | \ | ||
| 312 | PIN_AFSEL_GPIO(GPIOB_PIN7)) | ||
| 313 | |||
| 314 | #define VAL_GPIOB_DR2R (PIN_DRxR_ENABLE(GPIOB_PIN0) | \ | ||
| 315 | PIN_DRxR_ENABLE(GPIOB_PIN1) | \ | ||
| 316 | PIN_DRxR_ENABLE(GPIOB_I2C0_SCL) | \ | ||
| 317 | PIN_DRxR_ENABLE(GPIOB_I2C0_SDA) | \ | ||
| 318 | PIN_DRxR_ENABLE(GPIOB_PIN4) | \ | ||
| 319 | PIN_DRxR_ENABLE(GPIOB_PIN5) | \ | ||
| 320 | PIN_DRxR_ENABLE(GPIOB_PIN6) | \ | ||
| 321 | PIN_DRxR_ENABLE(GPIOB_PIN7)) | ||
| 322 | |||
| 323 | #define VAL_GPIOB_DR4R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \ | ||
| 324 | PIN_DRxR_DISABLE(GPIOB_PIN1) | \ | ||
| 325 | PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 326 | PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 327 | PIN_DRxR_DISABLE(GPIOB_PIN4) | \ | ||
| 328 | PIN_DRxR_DISABLE(GPIOB_PIN5) | \ | ||
| 329 | PIN_DRxR_DISABLE(GPIOB_PIN6) | \ | ||
| 330 | PIN_DRxR_DISABLE(GPIOB_PIN7)) | ||
| 331 | |||
| 332 | #define VAL_GPIOB_DR8R (PIN_DRxR_DISABLE(GPIOB_PIN0) | \ | ||
| 333 | PIN_DRxR_DISABLE(GPIOB_PIN1) | \ | ||
| 334 | PIN_DRxR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 335 | PIN_DRxR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 336 | PIN_DRxR_DISABLE(GPIOB_PIN4) | \ | ||
| 337 | PIN_DRxR_DISABLE(GPIOB_PIN5) | \ | ||
| 338 | PIN_DRxR_DISABLE(GPIOB_PIN6) | \ | ||
| 339 | PIN_DRxR_DISABLE(GPIOB_PIN7)) | ||
| 340 | |||
| 341 | #define VAL_GPIOB_ODR (PIN_ODR_DISABLE(GPIOB_PIN0) | \ | ||
| 342 | PIN_ODR_DISABLE(GPIOB_PIN1) | \ | ||
| 343 | PIN_ODR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 344 | PIN_ODR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 345 | PIN_ODR_DISABLE(GPIOB_PIN4) | \ | ||
| 346 | PIN_ODR_DISABLE(GPIOB_PIN5) | \ | ||
| 347 | PIN_ODR_DISABLE(GPIOB_PIN6) | \ | ||
| 348 | PIN_ODR_DISABLE(GPIOB_PIN7)) | ||
| 349 | |||
| 350 | #define VAL_GPIOB_PUR (PIN_PxR_DISABLE(GPIOB_PIN0) | \ | ||
| 351 | PIN_PxR_DISABLE(GPIOB_PIN1) | \ | ||
| 352 | PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 353 | PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 354 | PIN_PxR_DISABLE(GPIOB_PIN4) | \ | ||
| 355 | PIN_PxR_DISABLE(GPIOB_PIN5) | \ | ||
| 356 | PIN_PxR_DISABLE(GPIOB_PIN6) | \ | ||
| 357 | PIN_PxR_DISABLE(GPIOB_PIN7)) | ||
| 358 | |||
| 359 | #define VAL_GPIOB_PDR (PIN_PxR_DISABLE(GPIOB_PIN0) | \ | ||
| 360 | PIN_PxR_DISABLE(GPIOB_PIN1) | \ | ||
| 361 | PIN_PxR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 362 | PIN_PxR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 363 | PIN_PxR_DISABLE(GPIOB_PIN4) | \ | ||
| 364 | PIN_PxR_DISABLE(GPIOB_PIN5) | \ | ||
| 365 | PIN_PxR_DISABLE(GPIOB_PIN6) | \ | ||
| 366 | PIN_PxR_DISABLE(GPIOB_PIN7)) | ||
| 367 | |||
| 368 | #define VAL_GPIOB_SLR (PIN_SLR_DISABLE(GPIOB_PIN0) | \ | ||
| 369 | PIN_SLR_DISABLE(GPIOB_PIN1) | \ | ||
| 370 | PIN_SLR_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 371 | PIN_SLR_DISABLE(GPIOB_I2C0_SDA) | \ | ||
| 372 | PIN_SLR_DISABLE(GPIOB_PIN4) | \ | ||
| 373 | PIN_SLR_DISABLE(GPIOB_PIN5) | \ | ||
| 374 | PIN_SLR_DISABLE(GPIOB_PIN6) | \ | ||
| 375 | PIN_SLR_DISABLE(GPIOB_PIN7)) | ||
| 376 | |||
| 377 | #define VAL_GPIOB_DEN (PIN_DEN_ENABLE(GPIOB_PIN0) | \ | ||
| 378 | PIN_DEN_ENABLE(GPIOB_PIN1) | \ | ||
| 379 | PIN_DEN_ENABLE(GPIOB_I2C0_SCL) | \ | ||
| 380 | PIN_DEN_ENABLE(GPIOB_I2C0_SDA) | \ | ||
| 381 | PIN_DEN_ENABLE(GPIOB_PIN4) | \ | ||
| 382 | PIN_DEN_ENABLE(GPIOB_PIN5) | \ | ||
| 383 | PIN_DEN_ENABLE(GPIOB_PIN6) | \ | ||
| 384 | PIN_DEN_ENABLE(GPIOB_PIN7)) | ||
| 385 | |||
| 386 | #define VAL_GPIOB_AMSEL (PIN_AMSEL_DISABLE(GPIOB_PIN0) | \ | ||
| 387 | PIN_AMSEL_DISABLE(GPIOB_PIN1) | \ | ||
| 388 | PIN_AMSEL_DISABLE(GPIOB_I2C0_SCL) | \ | ||
| 389 | PIN_AMSEL_DISABLE(GPIOB_I2C0_SDA)) | ||
| 390 | |||
| 391 | #define VAL_GPIOB_PCTL (PIN_PCTL_MODE(GPIOB_PIN0, 0) | \ | ||
| 392 | PIN_PCTL_MODE(GPIOB_PIN1, 0) | \ | ||
| 393 | PIN_PCTL_MODE(GPIOB_I2C0_SCL, 0) | \ | ||
| 394 | PIN_PCTL_MODE(GPIOB_I2C0_SDA, 0) | \ | ||
| 395 | PIN_PCTL_MODE(GPIOB_PIN4, 0) | \ | ||
| 396 | PIN_PCTL_MODE(GPIOB_PIN5, 0) | \ | ||
| 397 | PIN_PCTL_MODE(GPIOB_PIN6, 0) | \ | ||
| 398 | PIN_PCTL_MODE(GPIOB_PIN7, 0)) | ||
| 399 | |||
| 400 | /* | ||
| 401 | * GPIOC Setup: | ||
| 402 | * | ||
| 403 | * PC0 - TCK_SWCLK (alternate 1) | ||
| 404 | * PC1 - TMS_SWDIO (alternate 1) | ||
| 405 | * PC2 - TDI (alternate 1) | ||
| 406 | * PC3 - TDO_SWO (alternate 1) | ||
| 407 | * PC4 - PIN4 () | ||
| 408 | * PC5 - PIN5 () | ||
| 409 | * PC6 - PIN6 () | ||
| 410 | * PC7 - PIN7 () | ||
| 411 | */ | ||
| 412 | |||
| 413 | #define VAL_GPIOC_DATA (PIN_DATA_LOW(GPIOC_TCK_SWCLK) | \ | ||
| 414 | PIN_DATA_LOW(GPIOC_TMS_SWDIO) | \ | ||
| 415 | PIN_DATA_LOW(GPIOC_TDI) | \ | ||
| 416 | PIN_DATA_LOW(GPIOC_TDO_SWO) | \ | ||
| 417 | PIN_DATA_LOW(GPIOC_PIN4) | \ | ||
| 418 | PIN_DATA_LOW(GPIOC_PIN5) | \ | ||
| 419 | PIN_DATA_LOW(GPIOC_PIN6) | \ | ||
| 420 | PIN_DATA_LOW(GPIOC_PIN7)) | ||
| 421 | |||
| 422 | #define VAL_GPIOC_DIR (PIN_DIR_IN(GPIOC_TCK_SWCLK) | \ | ||
| 423 | PIN_DIR_IN(GPIOC_TMS_SWDIO) | \ | ||
| 424 | PIN_DIR_IN(GPIOC_TDI) | \ | ||
| 425 | PIN_DIR_OUT(GPIOC_TDO_SWO) | \ | ||
| 426 | PIN_DIR_IN(GPIOC_PIN4) | \ | ||
| 427 | PIN_DIR_IN(GPIOC_PIN5) | \ | ||
| 428 | PIN_DIR_IN(GPIOC_PIN6) | \ | ||
| 429 | PIN_DIR_IN(GPIOC_PIN7)) | ||
| 430 | |||
| 431 | #define VAL_GPIOC_AFSEL (PIN_AFSEL_ALTERNATE(GPIOC_TCK_SWCLK) | \ | ||
| 432 | PIN_AFSEL_ALTERNATE(GPIOC_TMS_SWDIO) | \ | ||
| 433 | PIN_AFSEL_ALTERNATE(GPIOC_TDI) | \ | ||
| 434 | PIN_AFSEL_ALTERNATE(GPIOC_TDO_SWO) | \ | ||
| 435 | PIN_AFSEL_GPIO(GPIOC_PIN4) | \ | ||
| 436 | PIN_AFSEL_GPIO(GPIOC_PIN5) | \ | ||
| 437 | PIN_AFSEL_GPIO(GPIOC_PIN6) | \ | ||
| 438 | PIN_AFSEL_GPIO(GPIOC_PIN7)) | ||
| 439 | |||
| 440 | #define VAL_GPIOC_DR2R (PIN_DRxR_ENABLE(GPIOC_TCK_SWCLK) | \ | ||
| 441 | PIN_DRxR_ENABLE(GPIOC_TMS_SWDIO) | \ | ||
| 442 | PIN_DRxR_ENABLE(GPIOC_TDI) | \ | ||
| 443 | PIN_DRxR_ENABLE(GPIOC_TDO_SWO) | \ | ||
| 444 | PIN_DRxR_ENABLE(GPIOC_PIN4) | \ | ||
| 445 | PIN_DRxR_ENABLE(GPIOC_PIN5) | \ | ||
| 446 | PIN_DRxR_ENABLE(GPIOC_PIN6) | \ | ||
| 447 | PIN_DRxR_ENABLE(GPIOC_PIN7)) | ||
| 448 | |||
| 449 | #define VAL_GPIOC_DR4R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 450 | PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 451 | PIN_DRxR_DISABLE(GPIOC_TDI) | \ | ||
| 452 | PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 453 | PIN_DRxR_DISABLE(GPIOC_PIN4) | \ | ||
| 454 | PIN_DRxR_DISABLE(GPIOC_PIN5) | \ | ||
| 455 | PIN_DRxR_DISABLE(GPIOC_PIN6) | \ | ||
| 456 | PIN_DRxR_DISABLE(GPIOC_PIN7)) | ||
| 457 | |||
| 458 | #define VAL_GPIOC_DR8R (PIN_DRxR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 459 | PIN_DRxR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 460 | PIN_DRxR_DISABLE(GPIOC_TDI) | \ | ||
| 461 | PIN_DRxR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 462 | PIN_DRxR_DISABLE(GPIOC_PIN4) | \ | ||
| 463 | PIN_DRxR_DISABLE(GPIOC_PIN5) | \ | ||
| 464 | PIN_DRxR_DISABLE(GPIOC_PIN6) | \ | ||
| 465 | PIN_DRxR_DISABLE(GPIOC_PIN7)) | ||
| 466 | |||
| 467 | #define VAL_GPIOC_ODR (PIN_ODR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 468 | PIN_ODR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 469 | PIN_ODR_DISABLE(GPIOC_TDI) | \ | ||
| 470 | PIN_ODR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 471 | PIN_ODR_DISABLE(GPIOC_PIN4) | \ | ||
| 472 | PIN_ODR_DISABLE(GPIOC_PIN5) | \ | ||
| 473 | PIN_ODR_DISABLE(GPIOC_PIN6) | \ | ||
| 474 | PIN_ODR_DISABLE(GPIOC_PIN7)) | ||
| 475 | |||
| 476 | #define VAL_GPIOC_PUR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 477 | PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 478 | PIN_PxR_DISABLE(GPIOC_TDI) | \ | ||
| 479 | PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 480 | PIN_PxR_DISABLE(GPIOC_PIN4) | \ | ||
| 481 | PIN_PxR_DISABLE(GPIOC_PIN5) | \ | ||
| 482 | PIN_PxR_DISABLE(GPIOC_PIN6) | \ | ||
| 483 | PIN_PxR_DISABLE(GPIOC_PIN7)) | ||
| 484 | |||
| 485 | #define VAL_GPIOC_PDR (PIN_PxR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 486 | PIN_PxR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 487 | PIN_PxR_DISABLE(GPIOC_TDI) | \ | ||
| 488 | PIN_PxR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 489 | PIN_PxR_DISABLE(GPIOC_PIN4) | \ | ||
| 490 | PIN_PxR_DISABLE(GPIOC_PIN5) | \ | ||
| 491 | PIN_PxR_DISABLE(GPIOC_PIN6) | \ | ||
| 492 | PIN_PxR_DISABLE(GPIOC_PIN7)) | ||
| 493 | |||
| 494 | #define VAL_GPIOC_SLR (PIN_SLR_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 495 | PIN_SLR_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 496 | PIN_SLR_DISABLE(GPIOC_TDI) | \ | ||
| 497 | PIN_SLR_DISABLE(GPIOC_TDO_SWO) | \ | ||
| 498 | PIN_SLR_DISABLE(GPIOC_PIN4) | \ | ||
| 499 | PIN_SLR_DISABLE(GPIOC_PIN5) | \ | ||
| 500 | PIN_SLR_DISABLE(GPIOC_PIN6) | \ | ||
| 501 | PIN_SLR_DISABLE(GPIOC_PIN7)) | ||
| 502 | |||
| 503 | #define VAL_GPIOC_DEN (PIN_DEN_ENABLE(GPIOC_TCK_SWCLK) | \ | ||
| 504 | PIN_DEN_ENABLE(GPIOC_TMS_SWDIO) | \ | ||
| 505 | PIN_DEN_ENABLE(GPIOC_TDI) | \ | ||
| 506 | PIN_DEN_ENABLE(GPIOC_TDO_SWO) | \ | ||
| 507 | PIN_DEN_ENABLE(GPIOC_PIN4) | \ | ||
| 508 | PIN_DEN_ENABLE(GPIOC_PIN5) | \ | ||
| 509 | PIN_DEN_ENABLE(GPIOC_PIN6) | \ | ||
| 510 | PIN_DEN_ENABLE(GPIOC_PIN7)) | ||
| 511 | |||
| 512 | #define VAL_GPIOC_AMSEL (PIN_AMSEL_DISABLE(GPIOC_TCK_SWCLK) | \ | ||
| 513 | PIN_AMSEL_DISABLE(GPIOC_TMS_SWDIO) | \ | ||
| 514 | PIN_AMSEL_DISABLE(GPIOC_TDI) | \ | ||
| 515 | PIN_AMSEL_DISABLE(GPIOC_TDO_SWO)) | ||
| 516 | |||
| 517 | #define VAL_GPIOC_PCTL (PIN_PCTL_MODE(GPIOC_TCK_SWCLK, 1) | \ | ||
| 518 | PIN_PCTL_MODE(GPIOC_TMS_SWDIO, 1) | \ | ||
| 519 | PIN_PCTL_MODE(GPIOC_TDI, 1) | \ | ||
| 520 | PIN_PCTL_MODE(GPIOC_TDO_SWO, 1) | \ | ||
| 521 | PIN_PCTL_MODE(GPIOC_PIN4, 0) | \ | ||
| 522 | PIN_PCTL_MODE(GPIOC_PIN5, 0) | \ | ||
| 523 | PIN_PCTL_MODE(GPIOC_PIN6, 0) | \ | ||
| 524 | PIN_PCTL_MODE(GPIOC_PIN7, 0)) | ||
| 525 | |||
| 526 | /* | ||
| 527 | * GPIOD Setup: | ||
| 528 | * | ||
| 529 | * PD0 - PIN0 () | ||
| 530 | * PD1 - PIN1 () | ||
| 531 | * PD2 - PIN2 () | ||
| 532 | * PD3 - PIN3 () | ||
| 533 | * PD4 - PIN4 () | ||
| 534 | * PD5 - PIN5 () | ||
| 535 | * PD6 - PIN6 () | ||
| 536 | * PD7 - PIN7 () | ||
| 537 | */ | ||
| 538 | #define VAL_GPIOD_DATA (PIN_DATA_LOW(GPIOD_PIN0) | \ | ||
| 539 | PIN_DATA_LOW(GPIOD_PIN1) | \ | ||
| 540 | PIN_DATA_LOW(GPIOD_PIN2) | \ | ||
| 541 | PIN_DATA_LOW(GPIOD_PIN3) | \ | ||
| 542 | PIN_DATA_LOW(GPIOD_PIN4) | \ | ||
| 543 | PIN_DATA_LOW(GPIOD_PIN5) | \ | ||
| 544 | PIN_DATA_LOW(GPIOD_PIN6) | \ | ||
| 545 | PIN_DATA_LOW(GPIOD_PIN7)) | ||
| 546 | |||
| 547 | #define VAL_GPIOD_DIR (PIN_DIR_IN(GPIOD_PIN0) | \ | ||
| 548 | PIN_DIR_IN(GPIOD_PIN1) | \ | ||
| 549 | PIN_DIR_IN(GPIOD_PIN2) | \ | ||
| 550 | PIN_DIR_IN(GPIOD_PIN3) | \ | ||
| 551 | PIN_DIR_IN(GPIOD_PIN4) | \ | ||
| 552 | PIN_DIR_IN(GPIOD_PIN5) | \ | ||
| 553 | PIN_DIR_IN(GPIOD_PIN6) | \ | ||
| 554 | PIN_DIR_IN(GPIOD_PIN7)) | ||
| 555 | |||
| 556 | #define VAL_GPIOD_AFSEL (PIN_AFSEL_GPIO(GPIOD_PIN0) | \ | ||
| 557 | PIN_AFSEL_GPIO(GPIOD_PIN1) | \ | ||
| 558 | PIN_AFSEL_GPIO(GPIOD_PIN2) | \ | ||
| 559 | PIN_AFSEL_GPIO(GPIOD_PIN3) | \ | ||
| 560 | PIN_AFSEL_GPIO(GPIOD_PIN4) | \ | ||
| 561 | PIN_AFSEL_GPIO(GPIOD_PIN5) | \ | ||
| 562 | PIN_AFSEL_GPIO(GPIOD_PIN6) | \ | ||
| 563 | PIN_AFSEL_GPIO(GPIOD_PIN7)) | ||
| 564 | |||
| 565 | #define VAL_GPIOD_DR2R (PIN_DRxR_ENABLE(GPIOD_PIN0) | \ | ||
| 566 | PIN_DRxR_ENABLE(GPIOD_PIN1) | \ | ||
| 567 | PIN_DRxR_ENABLE(GPIOD_PIN2) | \ | ||
| 568 | PIN_DRxR_ENABLE(GPIOD_PIN3) | \ | ||
| 569 | PIN_DRxR_ENABLE(GPIOD_PIN4) | \ | ||
| 570 | PIN_DRxR_ENABLE(GPIOD_PIN5) | \ | ||
| 571 | PIN_DRxR_ENABLE(GPIOD_PIN6) | \ | ||
| 572 | PIN_DRxR_ENABLE(GPIOD_PIN7)) | ||
| 573 | |||
| 574 | #define VAL_GPIOD_DR4R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \ | ||
| 575 | PIN_DRxR_DISABLE(GPIOD_PIN1) | \ | ||
| 576 | PIN_DRxR_DISABLE(GPIOD_PIN2) | \ | ||
| 577 | PIN_DRxR_DISABLE(GPIOD_PIN3) | \ | ||
| 578 | PIN_DRxR_DISABLE(GPIOD_PIN4) | \ | ||
| 579 | PIN_DRxR_DISABLE(GPIOD_PIN5) | \ | ||
| 580 | PIN_DRxR_DISABLE(GPIOD_PIN6) | \ | ||
| 581 | PIN_DRxR_DISABLE(GPIOD_PIN7)) | ||
| 582 | |||
| 583 | #define VAL_GPIOD_DR8R (PIN_DRxR_DISABLE(GPIOD_PIN0) | \ | ||
| 584 | PIN_DRxR_DISABLE(GPIOD_PIN1) | \ | ||
| 585 | PIN_DRxR_DISABLE(GPIOD_PIN2) | \ | ||
| 586 | PIN_DRxR_DISABLE(GPIOD_PIN3) | \ | ||
| 587 | PIN_DRxR_DISABLE(GPIOD_PIN4) | \ | ||
| 588 | PIN_DRxR_DISABLE(GPIOD_PIN5) | \ | ||
| 589 | PIN_DRxR_DISABLE(GPIOD_PIN6) | \ | ||
| 590 | PIN_DRxR_DISABLE(GPIOD_PIN7)) | ||
| 591 | |||
| 592 | #define VAL_GPIOD_ODR (PIN_ODR_DISABLE(GPIOD_PIN0) | \ | ||
| 593 | PIN_ODR_DISABLE(GPIOD_PIN1) | \ | ||
| 594 | PIN_ODR_DISABLE(GPIOD_PIN2) | \ | ||
| 595 | PIN_ODR_DISABLE(GPIOD_PIN3) | \ | ||
| 596 | PIN_ODR_DISABLE(GPIOD_PIN4) | \ | ||
| 597 | PIN_ODR_DISABLE(GPIOD_PIN5) | \ | ||
| 598 | PIN_ODR_DISABLE(GPIOD_PIN6) | \ | ||
| 599 | PIN_ODR_DISABLE(GPIOD_PIN7)) | ||
| 600 | |||
| 601 | #define VAL_GPIOD_PUR (PIN_PxR_DISABLE(GPIOD_PIN0) | \ | ||
| 602 | PIN_PxR_DISABLE(GPIOD_PIN1) | \ | ||
| 603 | PIN_PxR_DISABLE(GPIOD_PIN2) | \ | ||
| 604 | PIN_PxR_DISABLE(GPIOD_PIN3) | \ | ||
| 605 | PIN_PxR_DISABLE(GPIOD_PIN4) | \ | ||
| 606 | PIN_PxR_DISABLE(GPIOD_PIN5) | \ | ||
| 607 | PIN_PxR_DISABLE(GPIOD_PIN6) | \ | ||
| 608 | PIN_PxR_DISABLE(GPIOD_PIN7)) | ||
| 609 | |||
| 610 | #define VAL_GPIOD_PDR (PIN_PxR_DISABLE(GPIOD_PIN0) | \ | ||
| 611 | PIN_PxR_DISABLE(GPIOD_PIN1) | \ | ||
| 612 | PIN_PxR_DISABLE(GPIOD_PIN2) | \ | ||
| 613 | PIN_PxR_DISABLE(GPIOD_PIN3) | \ | ||
| 614 | PIN_PxR_DISABLE(GPIOD_PIN4) | \ | ||
| 615 | PIN_PxR_DISABLE(GPIOD_PIN5) | \ | ||
| 616 | PIN_PxR_DISABLE(GPIOD_PIN6) | \ | ||
| 617 | PIN_PxR_DISABLE(GPIOD_PIN7)) | ||
| 618 | |||
| 619 | #define VAL_GPIOD_SLR (PIN_SLR_DISABLE(GPIOD_PIN0) | \ | ||
| 620 | PIN_SLR_DISABLE(GPIOD_PIN1) | \ | ||
| 621 | PIN_SLR_DISABLE(GPIOD_PIN2) | \ | ||
| 622 | PIN_SLR_DISABLE(GPIOD_PIN3) | \ | ||
| 623 | PIN_SLR_DISABLE(GPIOD_PIN4) | \ | ||
| 624 | PIN_SLR_DISABLE(GPIOD_PIN5) | \ | ||
| 625 | PIN_SLR_DISABLE(GPIOD_PIN6) | \ | ||
| 626 | PIN_SLR_DISABLE(GPIOD_PIN7)) | ||
| 627 | |||
| 628 | #define VAL_GPIOD_DEN (PIN_DEN_ENABLE(GPIOD_PIN0) | \ | ||
| 629 | PIN_DEN_ENABLE(GPIOD_PIN1) | \ | ||
| 630 | PIN_DEN_ENABLE(GPIOD_PIN2) | \ | ||
| 631 | PIN_DEN_ENABLE(GPIOD_PIN3) | \ | ||
| 632 | PIN_DEN_ENABLE(GPIOD_PIN4) | \ | ||
| 633 | PIN_DEN_ENABLE(GPIOD_PIN5) | \ | ||
| 634 | PIN_DEN_ENABLE(GPIOD_PIN6) | \ | ||
| 635 | PIN_DEN_ENABLE(GPIOD_PIN7)) | ||
| 636 | |||
| 637 | #define VAL_GPIOD_AMSEL (PIN_AMSEL_DISABLE(GPIOD_PIN0) | \ | ||
| 638 | PIN_AMSEL_DISABLE(GPIOD_PIN1) | \ | ||
| 639 | PIN_AMSEL_DISABLE(GPIOD_PIN2) | \ | ||
| 640 | PIN_AMSEL_DISABLE(GPIOD_PIN3)) | ||
| 641 | |||
| 642 | #define VAL_GPIOD_PCTL (PIN_PCTL_MODE(GPIOD_PIN0, 0) | \ | ||
| 643 | PIN_PCTL_MODE(GPIOD_PIN1, 0) | \ | ||
| 644 | PIN_PCTL_MODE(GPIOD_PIN2, 0) | \ | ||
| 645 | PIN_PCTL_MODE(GPIOD_PIN3, 0) | \ | ||
| 646 | PIN_PCTL_MODE(GPIOD_PIN4, 0) | \ | ||
| 647 | PIN_PCTL_MODE(GPIOD_PIN5, 0) | \ | ||
| 648 | PIN_PCTL_MODE(GPIOD_PIN6, 0) | \ | ||
| 649 | PIN_PCTL_MODE(GPIOD_PIN7, 0)) | ||
| 650 | |||
| 651 | /* | ||
| 652 | * GPIOE Setup: | ||
| 653 | * | ||
| 654 | * PE0 - PIN0 () | ||
| 655 | * PE1 - PIN1 () | ||
| 656 | * PE2 - PIN2 () | ||
| 657 | * PE3 - PIN3 () | ||
| 658 | * PE4 - PIN4 () | ||
| 659 | * PE5 - PIN5 () | ||
| 660 | * PE6 - PIN6 () | ||
| 661 | * PE7 - PIN7 () | ||
| 662 | */ | ||
| 663 | #define VAL_GPIOE_DATA (PIN_DATA_LOW(GPIOE_PIN0) | \ | ||
| 664 | PIN_DATA_LOW(GPIOE_PIN1) | \ | ||
| 665 | PIN_DATA_LOW(GPIOE_PIN2) | \ | ||
| 666 | PIN_DATA_LOW(GPIOE_PIN3) | \ | ||
| 667 | PIN_DATA_LOW(GPIOE_PIN4) | \ | ||
| 668 | PIN_DATA_LOW(GPIOE_PIN5) | \ | ||
| 669 | PIN_DATA_LOW(GPIOE_PIN6) | \ | ||
| 670 | PIN_DATA_LOW(GPIOE_PIN7)) | ||
| 671 | |||
| 672 | #define VAL_GPIOE_DIR (PIN_DIR_IN(GPIOE_PIN0) | \ | ||
| 673 | PIN_DIR_IN(GPIOE_PIN1) | \ | ||
| 674 | PIN_DIR_IN(GPIOE_PIN2) | \ | ||
| 675 | PIN_DIR_IN(GPIOE_PIN3) | \ | ||
| 676 | PIN_DIR_IN(GPIOE_PIN4) | \ | ||
| 677 | PIN_DIR_IN(GPIOE_PIN5) | \ | ||
| 678 | PIN_DIR_IN(GPIOE_PIN6) | \ | ||
| 679 | PIN_DIR_IN(GPIOE_PIN7)) | ||
| 680 | |||
| 681 | #define VAL_GPIOE_AFSEL (PIN_AFSEL_GPIO(GPIOE_PIN0) | \ | ||
| 682 | PIN_AFSEL_GPIO(GPIOE_PIN1) | \ | ||
| 683 | PIN_AFSEL_GPIO(GPIOE_PIN2) | \ | ||
| 684 | PIN_AFSEL_GPIO(GPIOE_PIN3) | \ | ||
| 685 | PIN_AFSEL_GPIO(GPIOE_PIN4) | \ | ||
| 686 | PIN_AFSEL_GPIO(GPIOE_PIN5) | \ | ||
| 687 | PIN_AFSEL_GPIO(GPIOE_PIN6) | \ | ||
| 688 | PIN_AFSEL_GPIO(GPIOE_PIN7)) | ||
| 689 | |||
| 690 | #define VAL_GPIOE_DR2R (PIN_DRxR_ENABLE(GPIOE_PIN0) | \ | ||
| 691 | PIN_DRxR_ENABLE(GPIOE_PIN1) | \ | ||
| 692 | PIN_DRxR_ENABLE(GPIOE_PIN2) | \ | ||
| 693 | PIN_DRxR_ENABLE(GPIOE_PIN3) | \ | ||
| 694 | PIN_DRxR_ENABLE(GPIOE_PIN4) | \ | ||
| 695 | PIN_DRxR_ENABLE(GPIOE_PIN5) | \ | ||
| 696 | PIN_DRxR_ENABLE(GPIOE_PIN6) | \ | ||
| 697 | PIN_DRxR_ENABLE(GPIOE_PIN7)) | ||
| 698 | |||
| 699 | #define VAL_GPIOE_DR4R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \ | ||
| 700 | PIN_DRxR_DISABLE(GPIOE_PIN1) | \ | ||
| 701 | PIN_DRxR_DISABLE(GPIOE_PIN2) | \ | ||
| 702 | PIN_DRxR_DISABLE(GPIOE_PIN3) | \ | ||
| 703 | PIN_DRxR_DISABLE(GPIOE_PIN4) | \ | ||
| 704 | PIN_DRxR_DISABLE(GPIOE_PIN5) | \ | ||
| 705 | PIN_DRxR_DISABLE(GPIOE_PIN6) | \ | ||
| 706 | PIN_DRxR_DISABLE(GPIOE_PIN7)) | ||
| 707 | |||
| 708 | #define VAL_GPIOE_DR8R (PIN_DRxR_DISABLE(GPIOE_PIN0) | \ | ||
| 709 | PIN_DRxR_DISABLE(GPIOE_PIN1) | \ | ||
| 710 | PIN_DRxR_DISABLE(GPIOE_PIN2) | \ | ||
| 711 | PIN_DRxR_DISABLE(GPIOE_PIN3) | \ | ||
| 712 | PIN_DRxR_DISABLE(GPIOE_PIN4) | \ | ||
| 713 | PIN_DRxR_DISABLE(GPIOE_PIN5) | \ | ||
| 714 | PIN_DRxR_DISABLE(GPIOE_PIN6) | \ | ||
| 715 | PIN_DRxR_DISABLE(GPIOE_PIN7)) | ||
| 716 | |||
| 717 | #define VAL_GPIOE_ODR (PIN_ODR_DISABLE(GPIOE_PIN0) | \ | ||
| 718 | PIN_ODR_DISABLE(GPIOE_PIN1) | \ | ||
| 719 | PIN_ODR_DISABLE(GPIOE_PIN2) | \ | ||
| 720 | PIN_ODR_DISABLE(GPIOE_PIN3) | \ | ||
| 721 | PIN_ODR_DISABLE(GPIOE_PIN4) | \ | ||
| 722 | PIN_ODR_DISABLE(GPIOE_PIN5) | \ | ||
| 723 | PIN_ODR_DISABLE(GPIOE_PIN6) | \ | ||
| 724 | PIN_ODR_DISABLE(GPIOE_PIN7)) | ||
| 725 | |||
| 726 | #define VAL_GPIOE_PUR (PIN_PxR_DISABLE(GPIOE_PIN0) | \ | ||
| 727 | PIN_PxR_DISABLE(GPIOE_PIN1) | \ | ||
| 728 | PIN_PxR_DISABLE(GPIOE_PIN2) | \ | ||
| 729 | PIN_PxR_DISABLE(GPIOE_PIN3) | \ | ||
| 730 | PIN_PxR_DISABLE(GPIOE_PIN4) | \ | ||
| 731 | PIN_PxR_DISABLE(GPIOE_PIN5) | \ | ||
| 732 | PIN_PxR_DISABLE(GPIOE_PIN6) | \ | ||
| 733 | PIN_PxR_DISABLE(GPIOE_PIN7)) | ||
| 734 | |||
| 735 | #define VAL_GPIOE_PDR (PIN_PxR_DISABLE(GPIOE_PIN0) | \ | ||
| 736 | PIN_PxR_DISABLE(GPIOE_PIN1) | \ | ||
| 737 | PIN_PxR_DISABLE(GPIOE_PIN2) | \ | ||
| 738 | PIN_PxR_DISABLE(GPIOE_PIN3) | \ | ||
| 739 | PIN_PxR_DISABLE(GPIOE_PIN4) | \ | ||
| 740 | PIN_PxR_DISABLE(GPIOE_PIN5) | \ | ||
| 741 | PIN_PxR_DISABLE(GPIOE_PIN6) | \ | ||
| 742 | PIN_PxR_DISABLE(GPIOE_PIN7)) | ||
| 743 | |||
| 744 | #define VAL_GPIOE_SLR (PIN_SLR_DISABLE(GPIOE_PIN0) | \ | ||
| 745 | PIN_SLR_DISABLE(GPIOE_PIN1) | \ | ||
| 746 | PIN_SLR_DISABLE(GPIOE_PIN2) | \ | ||
| 747 | PIN_SLR_DISABLE(GPIOE_PIN3) | \ | ||
| 748 | PIN_SLR_DISABLE(GPIOE_PIN4) | \ | ||
| 749 | PIN_SLR_DISABLE(GPIOE_PIN5) | \ | ||
| 750 | PIN_SLR_DISABLE(GPIOE_PIN6) | \ | ||
| 751 | PIN_SLR_DISABLE(GPIOE_PIN7)) | ||
| 752 | |||
| 753 | #define VAL_GPIOE_DEN (PIN_DEN_ENABLE(GPIOE_PIN0) | \ | ||
| 754 | PIN_DEN_ENABLE(GPIOE_PIN1) | \ | ||
| 755 | PIN_DEN_ENABLE(GPIOE_PIN2) | \ | ||
| 756 | PIN_DEN_ENABLE(GPIOE_PIN3) | \ | ||
| 757 | PIN_DEN_ENABLE(GPIOE_PIN4) | \ | ||
| 758 | PIN_DEN_ENABLE(GPIOE_PIN5) | \ | ||
| 759 | PIN_DEN_ENABLE(GPIOE_PIN6) | \ | ||
| 760 | PIN_DEN_ENABLE(GPIOE_PIN7)) | ||
| 761 | |||
| 762 | #define VAL_GPIOE_AMSEL (PIN_AMSEL_DISABLE(GPIOE_PIN0) | \ | ||
| 763 | PIN_AMSEL_DISABLE(GPIOE_PIN1) | \ | ||
| 764 | PIN_AMSEL_DISABLE(GPIOE_PIN2) | \ | ||
| 765 | PIN_AMSEL_DISABLE(GPIOE_PIN3)) | ||
| 766 | |||
| 767 | #define VAL_GPIOE_PCTL (PIN_PCTL_MODE(GPIOE_PIN0, 0) | \ | ||
| 768 | PIN_PCTL_MODE(GPIOE_PIN1, 0) | \ | ||
| 769 | PIN_PCTL_MODE(GPIOE_PIN2, 0) | \ | ||
| 770 | PIN_PCTL_MODE(GPIOE_PIN3, 0) | \ | ||
| 771 | PIN_PCTL_MODE(GPIOE_PIN4, 0) | \ | ||
| 772 | PIN_PCTL_MODE(GPIOE_PIN5, 0) | \ | ||
| 773 | PIN_PCTL_MODE(GPIOE_PIN6, 0) | \ | ||
| 774 | PIN_PCTL_MODE(GPIOE_PIN7, 0)) | ||
| 775 | |||
| 776 | /* | ||
| 777 | * GPIOF Setup: | ||
| 778 | * | ||
| 779 | * PF0 - SW2 () | ||
| 780 | * PF1 - LED_RED () | ||
| 781 | * PF2 - LED_BLUE () | ||
| 782 | * PF3 - LED_GREEN () | ||
| 783 | * PF4 - SW1 () | ||
| 784 | * PF5 - PIN5 () | ||
| 785 | * PF6 - PIN6 () | ||
| 786 | * PF7 - PIN7 () | ||
| 787 | */ | ||
| 788 | |||
| 789 | #define VAL_GPIOF_DATA (PIN_DATA_LOW(GPIOF_SW2) | \ | ||
| 790 | PIN_DATA_LOW(GPIOF_LED_RED) | \ | ||
| 791 | PIN_DATA_LOW(GPIOF_LED_BLUE) | \ | ||
| 792 | PIN_DATA_LOW(GPIOF_LED_GREEN) | \ | ||
| 793 | PIN_DATA_LOW(GPIOF_SW1) | \ | ||
| 794 | PIN_DATA_LOW(GPIOF_PIN5) | \ | ||
| 795 | PIN_DATA_LOW(GPIOF_PIN6) | \ | ||
| 796 | PIN_DATA_LOW(GPIOF_PIN7)) | ||
| 797 | |||
| 798 | #define VAL_GPIOF_DIR (PIN_DIR_IN(GPIOF_SW2) | \ | ||
| 799 | PIN_DIR_IN(GPIOF_LED_RED) | \ | ||
| 800 | PIN_DIR_IN(GPIOF_LED_BLUE) | \ | ||
| 801 | PIN_DIR_IN(GPIOF_LED_GREEN) | \ | ||
| 802 | PIN_DIR_IN(GPIOF_SW1) | \ | ||
| 803 | PIN_DIR_IN(GPIOF_PIN5) | \ | ||
| 804 | PIN_DIR_IN(GPIOF_PIN6) | \ | ||
| 805 | PIN_DIR_IN(GPIOF_PIN7)) | ||
| 806 | |||
| 807 | #define VAL_GPIOF_AFSEL (PIN_AFSEL_GPIO(GPIOF_SW2) | \ | ||
| 808 | PIN_AFSEL_GPIO(GPIOF_LED_RED) | \ | ||
| 809 | PIN_AFSEL_GPIO(GPIOF_LED_BLUE) | \ | ||
| 810 | PIN_AFSEL_GPIO(GPIOF_LED_GREEN) | \ | ||
| 811 | PIN_AFSEL_GPIO(GPIOF_SW1) | \ | ||
| 812 | PIN_AFSEL_GPIO(GPIOF_PIN5) | \ | ||
| 813 | PIN_AFSEL_GPIO(GPIOF_PIN6) | \ | ||
| 814 | PIN_AFSEL_GPIO(GPIOF_PIN7)) | ||
| 815 | |||
| 816 | #define VAL_GPIOF_DR2R (PIN_DRxR_ENABLE(GPIOF_SW2) | \ | ||
| 817 | PIN_DRxR_ENABLE(GPIOF_LED_RED) | \ | ||
| 818 | PIN_DRxR_ENABLE(GPIOF_LED_BLUE) | \ | ||
| 819 | PIN_DRxR_ENABLE(GPIOF_LED_GREEN) | \ | ||
| 820 | PIN_DRxR_ENABLE(GPIOF_SW1) | \ | ||
| 821 | PIN_DRxR_ENABLE(GPIOF_PIN5) | \ | ||
| 822 | PIN_DRxR_ENABLE(GPIOF_PIN6) | \ | ||
| 823 | PIN_DRxR_ENABLE(GPIOF_PIN7)) | ||
| 824 | |||
| 825 | #define VAL_GPIOF_DR4R (PIN_DRxR_DISABLE(GPIOF_SW2) | \ | ||
| 826 | PIN_DRxR_DISABLE(GPIOF_LED_RED) | \ | ||
| 827 | PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 828 | PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 829 | PIN_DRxR_DISABLE(GPIOF_SW1) | \ | ||
| 830 | PIN_DRxR_DISABLE(GPIOF_PIN5) | \ | ||
| 831 | PIN_DRxR_DISABLE(GPIOF_PIN6) | \ | ||
| 832 | PIN_DRxR_DISABLE(GPIOF_PIN7)) | ||
| 833 | |||
| 834 | #define VAL_GPIOF_DR8R (PIN_DRxR_DISABLE(GPIOF_SW2) | \ | ||
| 835 | PIN_DRxR_DISABLE(GPIOF_LED_RED) | \ | ||
| 836 | PIN_DRxR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 837 | PIN_DRxR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 838 | PIN_DRxR_DISABLE(GPIOF_SW1) | \ | ||
| 839 | PIN_DRxR_DISABLE(GPIOF_PIN5) | \ | ||
| 840 | PIN_DRxR_DISABLE(GPIOF_PIN6) | \ | ||
| 841 | PIN_DRxR_DISABLE(GPIOF_PIN7)) | ||
| 842 | |||
| 843 | #define VAL_GPIOF_ODR (PIN_ODR_DISABLE(GPIOF_SW2) | \ | ||
| 844 | PIN_ODR_DISABLE(GPIOF_LED_RED) | \ | ||
| 845 | PIN_ODR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 846 | PIN_ODR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 847 | PIN_ODR_DISABLE(GPIOF_SW1) | \ | ||
| 848 | PIN_ODR_DISABLE(GPIOF_PIN5) | \ | ||
| 849 | PIN_ODR_DISABLE(GPIOF_PIN6) | \ | ||
| 850 | PIN_ODR_DISABLE(GPIOF_PIN7)) | ||
| 851 | |||
| 852 | #define VAL_GPIOF_PUR (PIN_PxR_DISABLE(GPIOF_SW2) | \ | ||
| 853 | PIN_PxR_DISABLE(GPIOF_LED_RED) | \ | ||
| 854 | PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 855 | PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 856 | PIN_PxR_DISABLE(GPIOF_SW1) | \ | ||
| 857 | PIN_PxR_DISABLE(GPIOF_PIN5) | \ | ||
| 858 | PIN_PxR_DISABLE(GPIOF_PIN6) | \ | ||
| 859 | PIN_PxR_DISABLE(GPIOF_PIN7)) | ||
| 860 | |||
| 861 | #define VAL_GPIOF_PDR (PIN_PxR_DISABLE(GPIOF_SW2) | \ | ||
| 862 | PIN_PxR_DISABLE(GPIOF_LED_RED) | \ | ||
| 863 | PIN_PxR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 864 | PIN_PxR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 865 | PIN_PxR_DISABLE(GPIOF_SW1) | \ | ||
| 866 | PIN_PxR_DISABLE(GPIOF_PIN5) | \ | ||
| 867 | PIN_PxR_DISABLE(GPIOF_PIN6) | \ | ||
| 868 | PIN_PxR_DISABLE(GPIOF_PIN7)) | ||
| 869 | |||
| 870 | #define VAL_GPIOF_SLR (PIN_SLR_DISABLE(GPIOF_SW2) | \ | ||
| 871 | PIN_SLR_DISABLE(GPIOF_LED_RED) | \ | ||
| 872 | PIN_SLR_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 873 | PIN_SLR_DISABLE(GPIOF_LED_GREEN) | \ | ||
| 874 | PIN_SLR_DISABLE(GPIOF_SW1) | \ | ||
| 875 | PIN_SLR_DISABLE(GPIOF_PIN5) | \ | ||
| 876 | PIN_SLR_DISABLE(GPIOF_PIN6) | \ | ||
| 877 | PIN_SLR_DISABLE(GPIOF_PIN7)) | ||
| 878 | |||
| 879 | #define VAL_GPIOF_DEN (PIN_DEN_ENABLE(GPIOF_SW2) | \ | ||
| 880 | PIN_DEN_ENABLE(GPIOF_LED_RED) | \ | ||
| 881 | PIN_DEN_ENABLE(GPIOF_LED_BLUE) | \ | ||
| 882 | PIN_DEN_ENABLE(GPIOF_LED_GREEN) | \ | ||
| 883 | PIN_DEN_ENABLE(GPIOF_SW1) | \ | ||
| 884 | PIN_DEN_ENABLE(GPIOF_PIN5) | \ | ||
| 885 | PIN_DEN_ENABLE(GPIOF_PIN6) | \ | ||
| 886 | PIN_DEN_ENABLE(GPIOF_PIN7)) | ||
| 887 | |||
| 888 | #define VAL_GPIOF_AMSEL (PIN_AMSEL_DISABLE(GPIOF_SW2) | \ | ||
| 889 | PIN_AMSEL_DISABLE(GPIOF_LED_RED) | \ | ||
| 890 | PIN_AMSEL_DISABLE(GPIOF_LED_BLUE) | \ | ||
| 891 | PIN_AMSEL_DISABLE(GPIOF_LED_GREEN)) | ||
| 892 | |||
| 893 | #define VAL_GPIOF_PCTL (PIN_PCTL_MODE(GPIOF_SW2, 0) | \ | ||
| 894 | PIN_PCTL_MODE(GPIOF_LED_RED, 0) | \ | ||
| 895 | PIN_PCTL_MODE(GPIOF_LED_BLUE, 0) | \ | ||
| 896 | PIN_PCTL_MODE(GPIOF_LED_GREEN, 0) | \ | ||
| 897 | PIN_PCTL_MODE(GPIOF_SW1, 0) | \ | ||
| 898 | PIN_PCTL_MODE(GPIOF_PIN5, 0) | \ | ||
| 899 | PIN_PCTL_MODE(GPIOF_PIN6, 0) | \ | ||
| 900 | PIN_PCTL_MODE(GPIOF_PIN7, 0)) | ||
| 901 | |||
| 902 | #if !defined(_FROM_ASM_) | ||
| 903 | #ifdef __cplusplus | ||
| 904 | extern "C" { | ||
| 905 | #endif | ||
| 906 | void boardInit(void); | ||
| 907 | #ifdef __cplusplus | ||
| 908 | } | ||
| 909 | #endif | ||
| 910 | #endif /* _FROM_ASM_ */ | ||
| 911 | |||
| 912 | #endif /* BOARD_H */ | ||