75 files changed, 11546 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.c b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.c
new file mode 100644
index 000000000..08c71112f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.c
@@ -0,0 +1,46 @@
+/*
+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 
+    VAL_IOPORT1_SEL1},
+  {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 
+    VAL_IOPORT2_SEL1},
+  {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 
+    VAL_IOPORT0_SEL1}
+}; /* Set UART TX pin correctly */
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  _disable_interrupts();
+}
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.h b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.h
new file mode 100644
index 000000000..a0ed8f792
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.h
@@ -0,0 +1,123 @@
+/*
+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the EXP430FR5969 LaunchPad board
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_EXP430FR5959
+#define BOARD_NAME "MSP430FR5969 LaunchPad"
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED_G                                PAL_LINE(IOPORT1, 0U)
+#define LINE_LED_R                                PAL_LINE(IOPORT2, 14U)
+#define LINE_SW_S1                                PAL_LINE(IOPORT2, 13U)
+#define LINE_SW_S2                                PAL_LINE(IOPORT1, 1U)
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the MSP430X Family Users Guide for details.
+ */
+/*
+ * Port A setup:
+ * 
+ * P1.0 - Green LED               (output low)
+ * P1.1 - Switch S2               (input pullup)
+ * P1.2 - BoosterPack BP19        (input pullup)
+ * P1.3 - BoosterPack BP11        (input pullup)
+ * P1.4 - BoosterPack BP12        (input pullup)
+ * P1.5 - BoosterPack BP13        (input pullup)
+ * P1.6 - BoosterPack BP15        (input pullup)
+ * P1.7 - BoosterPack BP14        (input pullup)
+ * P2.0 - Application UART TX     (alternate 2)
+ * P2.1 - Application UART RX     (alternate 2)
+ * P2.2 - BoosterPack BP7         (input pullup)
+ * P2.3 - N/C                     (input pullup)
+ * P2.4 - BoosterPack BP6         (input pullup)
+ * P2.5 - BoosterPack BP4         (input pullup)
+ * P2.6 - BoosterPack BP3         (input pullup)
+ * P2.7 - N/C                     (input pullup)
+ */
+#define VAL_IOPORT1_OUT   0xFCFE
+#define VAL_IOPORT1_DIR   0x0001
+#define VAL_IOPORT1_REN   0xFCFE
+#define VAL_IOPORT1_SEL0  0x0000
+#define VAL_IOPORT1_SEL1  0x0300
+/*
+ * Port B setup:
+ * 
+ * P3.0 - BoosterPack BP18        (input pullup)
+ * P3.1 - N/C                     (input pullup)
+ * P3.2 - N/C                     (input pullup)
+ * P3.3 - N/C                     (input pullup)
+ * P3.4 - BoosterPack BP8         (input pullup)
+ * P3.5 - BoosterPack BP9         (input pullup)
+ * P3.6 - BoosterPack BP10        (input pullup)
+ * P3.7 - N/C                     (input pullup)
+ * P4.0 - Application UART CTS    (input pullup)
+ * P4.1 - Application UART RTS    (output high)
+ * P4.2 - BoosterPack BP2         (input pullup)
+ * P4.3 - BoosterPack BP5         (input pullup)
+ * P4.4 - N/C                     (input pullup)
+ * P4.5 - Switch S1               (input pullup)
+ * P4.6 - Red LED                 (output low)
+ * P4.7 - N/C                     (input pullup)
+ */
+#define VAL_IOPORT2_OUT   0xBFFF
+#define VAL_IOPORT2_DIR   0x4200
+#define VAL_IOPORT2_REN   0xBDFF
+#define VAL_IOPORT2_SEL0  0x0000
+#define VAL_IOPORT2_SEL1  0x0000
+/*
+ * Port J setup:
+ * 
+ * PJ.0 - TDO                     (input pullup)
+ * PJ.1 - TDI                     (input pullup)
+ * PJ.2 - TMS                     (input pullup)
+ * PJ.3 - TCK                     (input pullup)
+ * PJ.4 - LFXIN                   (alternate 1)
+ * PJ.5 - LFXOUT                  (alternate 1)
+ * PJ.6 - HFXIN (N/C)             (input pullup)
+ * PJ.7 - HFXOUT (N/C)            (input pullup)
+ */
+#define VAL_IOPORT0_OUT   0x00FF
+#define VAL_IOPORT0_DIR   0x0000
+#define VAL_IOPORT0_REN   0x00CF
+#define VAL_IOPORT0_SEL0  0x0030
+#define VAL_IOPORT0_SEL1  0x0000
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.mk b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.mk
new file mode 100644
index 000000000..9b0d0e11f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR5969/board.mk
@@ -0,0 +1,8 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR5969/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR5969
+ALLINC += $(BOARDINC)
+ALLSRC += $(BOARDSRC)
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.c b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.c
new file mode 100644
index 000000000..309491152
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.c
@@ -0,0 +1,52 @@
+/*
+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, 
+    VAL_IOPORT1_SEL1},
+  {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, 
+    VAL_IOPORT2_SEL1},
+  {VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0, 
+    VAL_IOPORT3_SEL1},
+  {VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0, 
+    VAL_IOPORT4_SEL1},
+  {VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0, 
+    VAL_IOPORT5_SEL1},
+  {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, 
+    VAL_IOPORT0_SEL1}
+}; /* Set UART TX pin correctly */
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  _disable_interrupts();
+}
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.h b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.h
new file mode 100644
index 000000000..4561feacc
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.h
@@ -0,0 +1,205 @@
+/*
+    ChibiOS - Copyright (C) 2016 Andrew Wygle aka awygle
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the EXP430FR6989 LaunchPad board
+ */
+/* NOTE: LCD segment pins configured as unused - controlled by LCD driver if
+ * present
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_EXP430FR6989
+#define BOARD_NAME "MSP430FR6989 LaunchPad"
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED_R                                PAL_LINE(IOPORT1, 0U)
+#define LINE_LED_G                                PAL_LINE(IOPORT5, 7U)
+#define LINE_SW_S1                                PAL_LINE(IOPORT1, 1U)
+#define LINE_SW_S2                                PAL_LINE(IOPORT1, 2U)
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the MSP430X Family Users Guide for details.
+ */
+/*
+ * Port A setup:
+ * 
+ * P1.0 - Red LED                 (output low)
+ * P1.1 - Switch S1               (input pullup falling-edge interrupt)
+ * P1.2 - Switch S2               (input pullup falling-edge interrupt)
+ * P1.3 - BoosterPack BP34        (input pullup)
+ * P1.4 - BoosterPack BP7         (input pullup)
+ * P1.5 - BoosterPack BP18        (input pullup)
+ * P1.6 - BoosterPack BP15        (input pullup)
+ * P1.7 - BoosterPack BP14        (input pullup)
+ * P2.0 - BoosterPack BP8         (input pullup)
+ * P2.1 - BoosterPack BP19        (input pullup)
+ * P2.2 - BoosterPack BP35        (input pullup)
+ * P2.3 - BoosterPack BP31        (input pullup)
+ * P2.4 - BoosterPack BP12        (input pullup)
+ * P2.5 - BoosterPack BP13        (input pullup)
+ * P2.6 - BoosterPack BP39        (input pullup)
+ * P2.7 - BoosterPack BP40        (input pullup)
+ */
+#define VAL_IOPORT1_OUT   0xFFFE
+#define VAL_IOPORT1_DIR   0x0001
+#define VAL_IOPORT1_REN   0xFFFE
+#define VAL_IOPORT1_SEL0  0x0000
+#define VAL_IOPORT1_SEL1  0x0000
+/*
+ * Port B setup:
+ * 
+ * P3.0 - BoosterPack BP33        (input pullup)
+ * P3.1 - BoosterPack BP32        (input pullup)
+ * P3.2 - BoosterPack BP5         (input pullup)
+ * P3.3 - BoosterPack BP38        (input pullup)
+ * P3.4 - Application UART TX     (alternate 1)
+ * P3.5 - Application UART RX     (alternate 1)
+ * P3.6 - BoosterPack BP37        (input pullup)
+ * P3.7 - BoosterPack BP36        (input pullup)
+ * P4.0 - BoosterPack BP10        (input pullup)
+ * P4.1 - BoosterPack BP9         (input pullup)
+ * P4.2 - BoosterPack BP4         (input pullup)
+ * P4.3 - BoosterPack BP3         (input pullup)
+ * P4.4 - LCD S8                  (input pullup)
+ * P4.5 - LCD S7                  (input pullup)
+ * P4.6 - LCD S6                  (input pullup)
+ * P4.7 - BoosterPack BP11        (input pullup)
+ */
+#define VAL_IOPORT2_OUT   0xFFCF
+#define VAL_IOPORT2_DIR   0x0000
+#define VAL_IOPORT2_REN   0xFFCF
+#define VAL_IOPORT2_SEL0  0x0030
+#define VAL_IOPORT2_SEL1  0x0000
+/*
+ * Port C setup:
+ * 
+ * P5.0 - LCD S38                 (input pullup)
+ * P5.1 - LCD S37                 (input pullup)
+ * P5.2 - LCD S36                 (input pullup)
+ * P5.3 - LCD S35                 (input pullup)
+ * P5.4 - LCD S12                 (input pullup)
+ * P5.5 - LCD S11                 (input pullup)
+ * P5.6 - LCD S10                 (input pullup)
+ * P5.7 - LCD S9                  (input pullup)
+ * P6.0 - LCD R23                 (input pullup)
+ * P6.1 - LCD R13                 (input pullup)
+ * P6.2 - LCD R03                 (input pullup)
+ * P6.3 - LCD COM0                (input pullup)
+ * P6.4 - LCD COM1                (input pullup)
+ * P6.5 - LCD COM2                (input pullup)
+ * P6.6 - LCD COM3                (input pullup)
+ * P6.7 - LCD S31                 (input pullup)
+ */
+#define VAL_IOPORT3_OUT   0xFFFF
+#define VAL_IOPORT3_DIR   0x0000
+#define VAL_IOPORT3_REN   0xFFFF
+#define VAL_IOPORT3_SEL0  0x0000
+#define VAL_IOPORT3_SEL1  0x0000
+/*
+ * Port D setup:
+ * 
+ * P7.0 - LCD S17                 (input pullup)
+ * P7.1 - LCD S16                 (input pullup)
+ * P7.2 - LCD S15                 (input pullup)
+ * P7.3 - LCD S14                 (input pullup)
+ * P7.4 - LCD S13                 (input pullup)
+ * P7.5 - LCD S30                 (input pullup)
+ * P7.6 - LCD S29                 (input pullup)
+ * P7.7 - LCD S27                 (input pullup)
+ * P8.0 - LCD S21                 (input pullup)
+ * P8.1 - LCD S20                 (input pullup)
+ * P8.2 - LCD S19                 (input pullup)
+ * P8.3 - LCD S18                 (input pullup)
+ * P8.4 - BoosterPack BP23        (input pullup)
+ * P8.5 - BoosterPack BP24        (input pullup)
+ * P8.6 - BoosterPack BP25        (input pullup)
+ * P8.7 - BoosterPack BP26        (input pullup)
+ */
+#define VAL_IOPORT4_OUT   0xFFFF
+#define VAL_IOPORT4_DIR   0x0000
+#define VAL_IOPORT4_REN   0xFFFF
+#define VAL_IOPORT4_SEL0  0x0000
+#define VAL_IOPORT4_SEL1  0x0000
+/*
+ * Port E setup:
+ * 
+ * P9.0 - BoosterPack BP27        (input pullup)
+ * P9.1 - BoosterPack BP28        (input pullup)
+ * P9.2 - BoosterPack BP2         (input pullup)
+ * P9.3 - BoosterPack BP6         (input pullup)
+ * P9.4 - BoosterPack BP17        (input pullup)
+ * P9.5 - BoosterPack BP29        (input pullup)
+ * P9.6 - BoosterPack BP30        (input pullup)
+ * P9.7 - Green LED               (output low)
+ * P10.0 - LCD S4                 (input pullup)
+ * P10.1 - LCD S28                (input pullup)
+ * P10.2 - LCD S39                (input pullup)
+ * P10.3 - N/C Internally         (input pullup)
+ * P10.4 - N/C Internally         (input pullup)
+ * P10.5 - N/C Internally         (input pullup)
+ * P10.6 - N/C Internally         (input pullup)
+ * P10.7 - N/C Internally         (input pullup)
+ */
+#define VAL_IOPORT5_OUT   0xFF7F
+#define VAL_IOPORT5_DIR   0x0080
+#define VAL_IOPORT5_REN   0xFF7F
+#define VAL_IOPORT5_SEL0  0x0000
+#define VAL_IOPORT5_SEL1  0x0000
+/*
+ * Port J setup:
+ * 
+ * PJ.0 - TDO                     (input pullup)
+ * PJ.1 - TDI                     (input pullup)
+ * PJ.2 - TMS                     (input pullup)
+ * PJ.3 - TCK                     (input pullup)
+ * PJ.4 - LFXIN                   (alternate 1)
+ * PJ.5 - LFXOUT                  (alternate 1)
+ * PJ.6 - HFXIN (N/C)             (input pullup)
+ * PJ.7 - HFXOUT (N/C)            (input pullup)
+ */
+#define VAL_IOPORT0_OUT   0x00FF
+#define VAL_IOPORT0_DIR   0x0000
+#define VAL_IOPORT0_REN   0x00CF
+#define VAL_IOPORT0_SEL0  0x0030
+#define VAL_IOPORT0_SEL1  0x0000
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.mk b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.mk
new file mode 100644
index 000000000..80fbb4cf6
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/EXP430FR6989/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR6989/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/EXP430FR6989
+ALLINC += $(BOARDINC)
+ALLSRC += $(BOARDSRC)
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
new file mode 100644
index 000000000..afa1b8101
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
@@ -0,0 +1,127 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .ports = {
+    {
+      .port = IOPORT1,  // PORTA
+      .pads = {
+        /* PTA0*/ PAL_MODE_ALTERNATIVE_7,   /* PTA1*/ PAL_MODE_UNCONNECTED,     /* PTA2*/ PAL_MODE_OUTPUT_PUSHPULL,
+        /* PTA3*/ PAL_MODE_ALTERNATIVE_7,   /* PTA4*/ PAL_MODE_UNCONNECTED,     /* PTA5*/ PAL_MODE_UNCONNECTED,
+        /* PTA6*/ PAL_MODE_UNCONNECTED,     /* PTA7*/ PAL_MODE_UNCONNECTED,     /* PTA8*/ PAL_MODE_UNCONNECTED,
+        /* PTA9*/ PAL_MODE_UNCONNECTED,     /*PTA10*/ PAL_MODE_UNCONNECTED,     /*PTA11*/ PAL_MODE_UNCONNECTED,
+        /*PTA12*/ PAL_MODE_UNCONNECTED,     /*PTA13*/ PAL_MODE_UNCONNECTED,     /*PTA14*/ PAL_MODE_UNCONNECTED,
+        /*PTA15*/ PAL_MODE_UNCONNECTED,     /*PTA16*/ PAL_MODE_UNCONNECTED,     /*PTA17*/ PAL_MODE_UNCONNECTED,
+        /*PTA18*/ PAL_MODE_INPUT_ANALOG,    /*PTA19*/ PAL_MODE_INPUT_ANALOG,    /*PTA20*/ PAL_MODE_UNCONNECTED,
+        /*PTA21*/ PAL_MODE_UNCONNECTED,     /*PTA22*/ PAL_MODE_UNCONNECTED,     /*PTA23*/ PAL_MODE_UNCONNECTED,
+        /*PTA24*/ PAL_MODE_UNCONNECTED,     /*PTA25*/ PAL_MODE_UNCONNECTED,     /*PTA26*/ PAL_MODE_UNCONNECTED,
+        /*PTA27*/ PAL_MODE_UNCONNECTED,     /*PTA28*/ PAL_MODE_UNCONNECTED,     /*PTA29*/ PAL_MODE_UNCONNECTED,
+        /*PTA30*/ PAL_MODE_UNCONNECTED,     /*PTA31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT2,  // PORTB
+      .pads = {
+        /* PTB0*/ PAL_MODE_ALTERNATIVE_2,   /* PTB1*/ PAL_MODE_ALTERNATIVE_2,   /* PTB2*/ PAL_MODE_UNCONNECTED,
+        /* PTB3*/ PAL_MODE_UNCONNECTED,     /* PTB4*/ PAL_MODE_UNCONNECTED,     /* PTB5*/ PAL_MODE_UNCONNECTED,
+        /* PTB6*/ PAL_MODE_UNCONNECTED,     /* PTB7*/ PAL_MODE_UNCONNECTED,     /* PTB8*/ PAL_MODE_UNCONNECTED,
+        /* PTB9*/ PAL_MODE_UNCONNECTED,     /*PTB10*/ PAL_MODE_UNCONNECTED,     /*PTB11*/ PAL_MODE_UNCONNECTED,
+        /*PTB12*/ PAL_MODE_UNCONNECTED,     /*PTB13*/ PAL_MODE_UNCONNECTED,     /*PTB14*/ PAL_MODE_UNCONNECTED,
+        /*PTB15*/ PAL_MODE_UNCONNECTED,     /*PTB16*/ PAL_MODE_ALTERNATIVE_3,   /*PTB17*/ PAL_MODE_ALTERNATIVE_3,
+        /*PTB18*/ PAL_MODE_UNCONNECTED,     /*PTB19*/ PAL_MODE_UNCONNECTED,     /*PTB20*/ PAL_MODE_UNCONNECTED,
+        /*PTB21*/ PAL_MODE_UNCONNECTED,     /*PTB22*/ PAL_MODE_UNCONNECTED,     /*PTB23*/ PAL_MODE_UNCONNECTED,
+        /*PTB24*/ PAL_MODE_UNCONNECTED,     /*PTB25*/ PAL_MODE_UNCONNECTED,     /*PTB26*/ PAL_MODE_UNCONNECTED,
+        /*PTB27*/ PAL_MODE_UNCONNECTED,     /*PTB28*/ PAL_MODE_UNCONNECTED,     /*PTB29*/ PAL_MODE_UNCONNECTED,
+        /*PTB30*/ PAL_MODE_UNCONNECTED,     /*PTB31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT3,  // PORTC
+      .pads = {
+        /* PTC0*/ PAL_MODE_UNCONNECTED,     /* PTC1*/ PAL_MODE_UNCONNECTED,     /* PTC2*/ PAL_MODE_UNCONNECTED,
+        /* PTC3*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTC4*/ PAL_MODE_UNCONNECTED,     /* PTC5*/ PAL_MODE_UNCONNECTED,
+        /* PTC6*/ PAL_MODE_UNCONNECTED,     /* PTC7*/ PAL_MODE_UNCONNECTED,     /* PTC8*/ PAL_MODE_UNCONNECTED,
+        /* PTC9*/ PAL_MODE_UNCONNECTED,     /*PTC10*/ PAL_MODE_UNCONNECTED,     /*PTC11*/ PAL_MODE_UNCONNECTED,
+        /*PTC12*/ PAL_MODE_UNCONNECTED,     /*PTC13*/ PAL_MODE_UNCONNECTED,     /*PTC14*/ PAL_MODE_UNCONNECTED,
+        /*PTC15*/ PAL_MODE_UNCONNECTED,     /*PTC16*/ PAL_MODE_UNCONNECTED,     /*PTC17*/ PAL_MODE_UNCONNECTED,
+        /*PTC18*/ PAL_MODE_UNCONNECTED,     /*PTC19*/ PAL_MODE_UNCONNECTED,     /*PTC20*/ PAL_MODE_UNCONNECTED,
+        /*PTC21*/ PAL_MODE_UNCONNECTED,     /*PTC22*/ PAL_MODE_UNCONNECTED,     /*PTC23*/ PAL_MODE_UNCONNECTED,
+        /*PTC24*/ PAL_MODE_UNCONNECTED,     /*PTC25*/ PAL_MODE_UNCONNECTED,     /*PTC26*/ PAL_MODE_UNCONNECTED,
+        /*PTC27*/ PAL_MODE_UNCONNECTED,     /*PTC28*/ PAL_MODE_UNCONNECTED,     /*PTC29*/ PAL_MODE_UNCONNECTED,
+        /*PTC30*/ PAL_MODE_UNCONNECTED,     /*PTC31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT4,  // PORTD
+      .pads = {
+        /* PTD0*/ PAL_MODE_UNCONNECTED,     /* PTD1*/ PAL_MODE_UNCONNECTED,     /* PTD2*/ PAL_MODE_UNCONNECTED,
+        /* PTD3*/ PAL_MODE_UNCONNECTED,     /* PTD4*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD5*/ PAL_MODE_UNCONNECTED,
+        /* PTD6*/ PAL_MODE_UNCONNECTED,     /* PTD7*/ PAL_MODE_UNCONNECTED,     /* PTD8*/ PAL_MODE_UNCONNECTED,
+        /* PTD9*/ PAL_MODE_UNCONNECTED,     /*PTD10*/ PAL_MODE_UNCONNECTED,     /*PTD11*/ PAL_MODE_UNCONNECTED,
+        /*PTD12*/ PAL_MODE_UNCONNECTED,     /*PTD13*/ PAL_MODE_UNCONNECTED,     /*PTD14*/ PAL_MODE_UNCONNECTED,
+        /*PTD15*/ PAL_MODE_UNCONNECTED,     /*PTD16*/ PAL_MODE_UNCONNECTED,     /*PTD17*/ PAL_MODE_UNCONNECTED,
+        /*PTD18*/ PAL_MODE_UNCONNECTED,     /*PTD19*/ PAL_MODE_UNCONNECTED,     /*PTD20*/ PAL_MODE_UNCONNECTED,
+        /*PTD21*/ PAL_MODE_UNCONNECTED,     /*PTD22*/ PAL_MODE_UNCONNECTED,     /*PTD23*/ PAL_MODE_UNCONNECTED,
+        /*PTD24*/ PAL_MODE_UNCONNECTED,     /*PTD25*/ PAL_MODE_UNCONNECTED,     /*PTD26*/ PAL_MODE_UNCONNECTED,
+        /*PTD27*/ PAL_MODE_UNCONNECTED,     /*PTD28*/ PAL_MODE_UNCONNECTED,     /*PTD29*/ PAL_MODE_UNCONNECTED,
+        /*PTD30*/ PAL_MODE_UNCONNECTED,     /*PTD31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT5,  // PORTE
+      .pads = {
+        /* PTE0*/ PAL_MODE_UNCONNECTED,     /* PTE1*/ PAL_MODE_UNCONNECTED,     /* PTE2*/ PAL_MODE_UNCONNECTED,
+        /* PTE3*/ PAL_MODE_UNCONNECTED,     /* PTE4*/ PAL_MODE_UNCONNECTED,     /* PTE5*/ PAL_MODE_UNCONNECTED,
+        /* PTE6*/ PAL_MODE_UNCONNECTED,     /* PTE7*/ PAL_MODE_UNCONNECTED,     /* PTE8*/ PAL_MODE_UNCONNECTED,
+        /* PTE9*/ PAL_MODE_UNCONNECTED,     /*PTE10*/ PAL_MODE_UNCONNECTED,     /*PTE11*/ PAL_MODE_UNCONNECTED,
+        /*PTE12*/ PAL_MODE_UNCONNECTED,     /*PTE13*/ PAL_MODE_UNCONNECTED,     /*PTE14*/ PAL_MODE_UNCONNECTED,
+        /*PTE15*/ PAL_MODE_UNCONNECTED,     /*PTE16*/ PAL_MODE_UNCONNECTED,     /*PTE17*/ PAL_MODE_UNCONNECTED,
+        /*PTE18*/ PAL_MODE_UNCONNECTED,     /*PTE19*/ PAL_MODE_UNCONNECTED,     /*PTE20*/ PAL_MODE_UNCONNECTED,
+        /*PTE21*/ PAL_MODE_UNCONNECTED,     /*PTE22*/ PAL_MODE_UNCONNECTED,     /*PTE23*/ PAL_MODE_UNCONNECTED,
+        /*PTE24*/ PAL_MODE_UNCONNECTED,     /*PTE25*/ PAL_MODE_UNCONNECTED,     /*PTE26*/ PAL_MODE_UNCONNECTED,
+        /*PTE27*/ PAL_MODE_UNCONNECTED,     /*PTE28*/ PAL_MODE_UNCONNECTED,     /*PTE29*/ PAL_MODE_UNCONNECTED,
+        /*PTE30*/ PAL_MODE_UNCONNECTED,     /*PTE31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  k20x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h
new file mode 100644
index 000000000..262d06de0
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.h
@@ -0,0 +1,70 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Freescale Freedom K20D50M board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_K20D50M
+#define BOARD_NAME                  "Freescale Freedom K20D50M"
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY      8000000UL
+/*
+ * MCU type
+ */
+#define K20x5
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED    IOPORT3
+#define PIN_LED_RED     3
+#define GPIO_LED_GREEN  IOPORT4
+#define PIN_LED_GREEN   4
+#define GPIO_LED_BLUE   IOPORT1
+#define PIN_LED_BLUE    2
+/* Inertial sensor: MMA8451Q */
+/* Default I2C address 0x1D */
+#define I2C_GYRO I2C0
+#define LINE_LED_RED    PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
+#define LINE_LED_GREEN  PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
+#define LINE_LED_BLUE   PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
+#define LINE_GYRO_SCL   PAL_LINE(GPIOB, 0U)
+#define LINE_GYRO_SDA   PAL_LINE(GPIOB, 1U)
+#define LINE_GYRO_INT1  PAL_LINE(GPIOC, 11U)
+#define LINE_GYRO_INT2  PAL_LINE(GPIOC, 6U)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
new file mode 100644
index 000000000..9e8a23601
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_K20D50M
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
new file mode 100644
index 000000000..574e6279f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
@@ -0,0 +1,127 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .ports = {
+    {
+      .port = IOPORT1,  // PORTA
+      .pads = {
+        /* PTA0*/ PAL_MODE_ALTERNATIVE_7,   /* PTA1*/ PAL_MODE_ALTERNATIVE_2,   /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
+        /* PTA3*/ PAL_MODE_ALTERNATIVE_7,   /* PTA4*/ PAL_MODE_INPUT_ANALOG,    /* PTA5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTA6*/ PAL_MODE_UNCONNECTED,     /* PTA7*/ PAL_MODE_UNCONNECTED,     /* PTA8*/ PAL_MODE_UNCONNECTED,
+        /* PTA9*/ PAL_MODE_UNCONNECTED,     /*PTA10*/ PAL_MODE_UNCONNECTED,     /*PTA11*/ PAL_MODE_UNCONNECTED,
+        /*PTA12*/ PAL_MODE_INPUT_ANALOG,    /*PTA13*/ PAL_MODE_INPUT_ANALOG,    /*PTA14*/ PAL_MODE_INPUT_ANALOG,
+        /*PTA15*/ PAL_MODE_INPUT_ANALOG,    /*PTA16*/ PAL_MODE_INPUT_ANALOG,    /*PTA17*/ PAL_MODE_INPUT_ANALOG,
+        /*PTA18*/ PAL_MODE_INPUT_ANALOG,    /*PTA19*/ PAL_MODE_INPUT_ANALOG,    /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
+        /*PTA21*/ PAL_MODE_UNCONNECTED,     /*PTA22*/ PAL_MODE_UNCONNECTED,     /*PTA23*/ PAL_MODE_UNCONNECTED,
+        /*PTA24*/ PAL_MODE_UNCONNECTED,     /*PTA25*/ PAL_MODE_UNCONNECTED,     /*PTA26*/ PAL_MODE_UNCONNECTED,
+        /*PTA27*/ PAL_MODE_UNCONNECTED,     /*PTA28*/ PAL_MODE_UNCONNECTED,     /*PTA29*/ PAL_MODE_UNCONNECTED,
+        /*PTA30*/ PAL_MODE_UNCONNECTED,     /*PTA31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT2,  // PORTB
+      .pads = {
+        /* PTB0*/ PAL_MODE_INPUT_ANALOG,    /* PTB1*/ PAL_MODE_INPUT_ANALOG,    /* PTB2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTB3*/ PAL_MODE_INPUT_ANALOG,    /* PTB4*/ PAL_MODE_UNCONNECTED,     /* PTB5*/ PAL_MODE_UNCONNECTED,
+        /* PTB6*/ PAL_MODE_UNCONNECTED,     /* PTB7*/ PAL_MODE_UNCONNECTED,     /* PTB8*/ PAL_MODE_INPUT_ANALOG,
+        /* PTB9*/ PAL_MODE_INPUT_ANALOG,    /*PTB10*/ PAL_MODE_INPUT_ANALOG,    /*PTB11*/ PAL_MODE_INPUT_ANALOG,
+        /*PTB12*/ PAL_MODE_UNCONNECTED,     /*PTB13*/ PAL_MODE_UNCONNECTED,     /*PTB14*/ PAL_MODE_UNCONNECTED,
+        /*PTB15*/ PAL_MODE_UNCONNECTED,     /*PTB16*/ PAL_MODE_INPUT_ANALOG,    /*PTB17*/ PAL_MODE_INPUT_ANALOG,
+        /*PTB18*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB19*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB20*/ PAL_MODE_UNCONNECTED,
+        /*PTB21*/ PAL_MODE_UNCONNECTED,     /*PTB22*/ PAL_MODE_UNCONNECTED,     /*PTB23*/ PAL_MODE_UNCONNECTED,
+        /*PTB24*/ PAL_MODE_UNCONNECTED,     /*PTB25*/ PAL_MODE_UNCONNECTED,     /*PTB26*/ PAL_MODE_UNCONNECTED,
+        /*PTB27*/ PAL_MODE_UNCONNECTED,     /*PTB28*/ PAL_MODE_UNCONNECTED,     /*PTB29*/ PAL_MODE_UNCONNECTED,
+        /*PTB30*/ PAL_MODE_UNCONNECTED,     /*PTB31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT3,  // PORTC
+      .pads = {
+        /* PTC0*/ PAL_MODE_INPUT_ANALOG,    /* PTC1*/ PAL_MODE_INPUT_ANALOG,    /* PTC2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC3*/ PAL_MODE_INPUT_ANALOG,    /* PTC4*/ PAL_MODE_INPUT_ANALOG,    /* PTC5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC6*/ PAL_MODE_INPUT_ANALOG,    /* PTC7*/ PAL_MODE_INPUT_ANALOG,    /* PTC8*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC9*/ PAL_MODE_INPUT_ANALOG,    /*PTC10*/ PAL_MODE_INPUT_ANALOG,    /*PTC11*/ PAL_MODE_INPUT_ANALOG,
+        /*PTC12*/ PAL_MODE_INPUT_ANALOG,    /*PTC13*/ PAL_MODE_INPUT_ANALOG,    /*PTC14*/ PAL_MODE_INPUT_ANALOG,
+        /*PTC15*/ PAL_MODE_INPUT_ANALOG,    /*PTC16*/ PAL_MODE_INPUT_ANALOG,    /*PTC17*/ PAL_MODE_INPUT_ANALOG,
+        /*PTC18*/ PAL_MODE_UNCONNECTED,     /*PTC19*/ PAL_MODE_UNCONNECTED,     /*PTC20*/ PAL_MODE_UNCONNECTED,
+        /*PTC21*/ PAL_MODE_UNCONNECTED,     /*PTC22*/ PAL_MODE_UNCONNECTED,     /*PTC23*/ PAL_MODE_UNCONNECTED,
+        /*PTC24*/ PAL_MODE_UNCONNECTED,     /*PTC25*/ PAL_MODE_UNCONNECTED,     /*PTC26*/ PAL_MODE_UNCONNECTED,
+        /*PTC27*/ PAL_MODE_UNCONNECTED,     /*PTC28*/ PAL_MODE_UNCONNECTED,     /*PTC29*/ PAL_MODE_UNCONNECTED,
+        /*PTC30*/ PAL_MODE_UNCONNECTED,     /*PTC31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT4,  // PORTD
+      .pads = {
+        /* PTD0*/ PAL_MODE_INPUT_ANALOG,    /* PTD1*/ PAL_MODE_OUTPUT_PUSHPULL, /* PTD2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTD3*/ PAL_MODE_INPUT_ANALOG,    /* PTD4*/ PAL_MODE_INPUT_ANALOG,    /* PTD5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTD6*/ PAL_MODE_INPUT_ANALOG,    /* PTD7*/ PAL_MODE_INPUT_ANALOG,    /* PTD8*/ PAL_MODE_INPUT_ANALOG,
+        /* PTD9*/ PAL_MODE_UNCONNECTED,     /*PTD10*/ PAL_MODE_UNCONNECTED,     /*PTD11*/ PAL_MODE_UNCONNECTED,
+        /*PTD12*/ PAL_MODE_UNCONNECTED,     /*PTD13*/ PAL_MODE_UNCONNECTED,     /*PTD14*/ PAL_MODE_UNCONNECTED,
+        /*PTD15*/ PAL_MODE_UNCONNECTED,     /*PTD16*/ PAL_MODE_UNCONNECTED,     /*PTD17*/ PAL_MODE_UNCONNECTED,
+        /*PTD18*/ PAL_MODE_UNCONNECTED,     /*PTD19*/ PAL_MODE_UNCONNECTED,     /*PTD20*/ PAL_MODE_UNCONNECTED,
+        /*PTD21*/ PAL_MODE_UNCONNECTED,     /*PTD22*/ PAL_MODE_UNCONNECTED,     /*PTD23*/ PAL_MODE_UNCONNECTED,
+        /*PTD24*/ PAL_MODE_UNCONNECTED,     /*PTD25*/ PAL_MODE_UNCONNECTED,     /*PTD26*/ PAL_MODE_UNCONNECTED,
+        /*PTD27*/ PAL_MODE_UNCONNECTED,     /*PTD28*/ PAL_MODE_UNCONNECTED,     /*PTD29*/ PAL_MODE_UNCONNECTED,
+        /*PTD30*/ PAL_MODE_UNCONNECTED,     /*PTD31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT5,  // PORTE
+      .pads = {
+        /* PTE0*/ PAL_MODE_INPUT_ANALOG,    /* PTE1*/ PAL_MODE_INPUT_ANALOG,    /* PTE2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTE3*/ PAL_MODE_INPUT_ANALOG,    /* PTE4*/ PAL_MODE_INPUT_ANALOG,    /* PTE5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTE6*/ PAL_MODE_UNCONNECTED,     /* PTE7*/ PAL_MODE_UNCONNECTED,     /* PTE8*/ PAL_MODE_UNCONNECTED,
+        /* PTE9*/ PAL_MODE_UNCONNECTED,     /*PTE10*/ PAL_MODE_UNCONNECTED,     /*PTE11*/ PAL_MODE_UNCONNECTED,
+        /*PTE12*/ PAL_MODE_UNCONNECTED,     /*PTE13*/ PAL_MODE_UNCONNECTED,     /*PTE14*/ PAL_MODE_UNCONNECTED,
+        /*PTE15*/ PAL_MODE_UNCONNECTED,     /*PTE16*/ PAL_MODE_UNCONNECTED,     /*PTE17*/ PAL_MODE_UNCONNECTED,
+        /*PTE18*/ PAL_MODE_UNCONNECTED,     /*PTE19*/ PAL_MODE_UNCONNECTED,     /*PTE20*/ PAL_MODE_INPUT_ANALOG,
+        /*PTE21*/ PAL_MODE_INPUT_ANALOG,    /*PTE22*/ PAL_MODE_INPUT_ANALOG,    /*PTE23*/ PAL_MODE_INPUT_ANALOG,
+        /*PTE24*/ PAL_MODE_ALTERNATIVE_5,   /*PTE25*/ PAL_MODE_ALTERNATIVE_5,   /*PTE26*/ PAL_MODE_UNCONNECTED,
+        /*PTE27*/ PAL_MODE_UNCONNECTED,     /*PTE28*/ PAL_MODE_UNCONNECTED,     /*PTE29*/ PAL_MODE_INPUT_ANALOG,
+        /*PTE30*/ PAL_MODE_INPUT_ANALOG,    /*PTE31*/ PAL_MODE_INPUT_ANALOG,
+      },
+    },
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  kl2x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h
new file mode 100644
index 000000000..e6d8723a3
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.h
@@ -0,0 +1,79 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Freescale Freedom KL25Z board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_KL25Z
+#define BOARD_NAME                  "Freescale Freedom KL25Z"
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY      8000000UL
+/*
+ * MCU type
+ */
+#define KL25
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED    IOPORT2
+#define PIN_LED_RED     18
+#define GPIO_LED_GREEN  IOPORT2
+#define PIN_LED_GREEN   19
+#define GPIO_LED_BLUE   IOPORT4
+#define PIN_LED_BLUE    1
+/* Inertial sensor: MMA8451Q */
+/* Default I2C address 0x1D */
+/* Note: the pins PTE24/25 are assigned to I2C0 by default;
+ *       if I2C0 is wanted on other pins, these need to be
+ *       assigned another function explicitly!
+ */
+#define I2C_GYRO I2C0
+#define LINE_LED_RED    PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
+#define LINE_LED_GREEN  PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
+#define LINE_LED_BLUE   PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
+#define LINE_GYRO_SCL   PAL_LINE(GPIOE, 24U)
+#define LINE_GYRO_SDA   PAL_LINE(GPIOE, 25U)
+#define LINE_GYRO_INT1  PAL_LINE(GPIOA, 14U)
+#define LINE_GYRO_INT2  PAL_LINE(GPIOA, 15U)
+/*
+ * Not configured:
+ *  - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
+ */
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
new file mode 100644
index 000000000..164e5ed88
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL25Z
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c
new file mode 100644
index 000000000..ede9061ce
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c
@@ -0,0 +1,127 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 flabbergast <[email protected]>
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .ports = {
+    {
+      .port = IOPORT1,  // PORTA
+      .pads = {
+        /* PTA0*/ PAL_MODE_ALTERNATIVE_7,   /* PTA1*/ PAL_MODE_ALTERNATIVE_2,   /* PTA2*/ PAL_MODE_ALTERNATIVE_2,
+        /* PTA3*/ PAL_MODE_ALTERNATIVE_7,   /* PTA4*/ PAL_MODE_INPUT_ANALOG,    /* PTA5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTA6*/ PAL_MODE_UNCONNECTED,     /* PTA7*/ PAL_MODE_UNCONNECTED,     /* PTA8*/ PAL_MODE_UNCONNECTED,
+        /* PTA9*/ PAL_MODE_UNCONNECTED,     /*PTA10*/ PAL_MODE_UNCONNECTED,     /*PTA11*/ PAL_MODE_UNCONNECTED,
+        /*PTA12*/ PAL_MODE_INPUT_ANALOG,    /*PTA13*/ PAL_MODE_INPUT_ANALOG,    /*PTA14*/ PAL_MODE_UNCONNECTED,
+        /*PTA15*/ PAL_MODE_UNCONNECTED,     /*PTA16*/ PAL_MODE_UNCONNECTED,     /*PTA17*/ PAL_MODE_UNCONNECTED,
+        /*PTA18*/ PAL_MODE_INPUT_ANALOG,    /*PTA19*/ PAL_MODE_INPUT_ANALOG,    /*PTA20*/ PAL_MODE_ALTERNATIVE_7,
+        /*PTA21*/ PAL_MODE_UNCONNECTED,     /*PTA22*/ PAL_MODE_UNCONNECTED,     /*PTA23*/ PAL_MODE_UNCONNECTED,
+        /*PTA24*/ PAL_MODE_UNCONNECTED,     /*PTA25*/ PAL_MODE_UNCONNECTED,     /*PTA26*/ PAL_MODE_UNCONNECTED,
+        /*PTA27*/ PAL_MODE_UNCONNECTED,     /*PTA28*/ PAL_MODE_UNCONNECTED,     /*PTA29*/ PAL_MODE_UNCONNECTED,
+        /*PTA30*/ PAL_MODE_UNCONNECTED,     /*PTA31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT2,  // PORTB
+      .pads = {
+        /* PTB0*/ PAL_MODE_INPUT_ANALOG,    /* PTB1*/ PAL_MODE_INPUT_ANALOG,    /* PTB2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTB3*/ PAL_MODE_INPUT_ANALOG,    /* PTB4*/ PAL_MODE_UNCONNECTED,     /* PTB5*/ PAL_MODE_UNCONNECTED,
+        /* PTB6*/ PAL_MODE_UNCONNECTED,     /* PTB7*/ PAL_MODE_UNCONNECTED,     /* PTB8*/ PAL_MODE_INPUT_ANALOG,
+        /* PTB9*/ PAL_MODE_UNCONNECTED,     /*PTB10*/ PAL_MODE_UNCONNECTED,     /*PTB11*/ PAL_MODE_UNCONNECTED,
+        /*PTB12*/ PAL_MODE_UNCONNECTED,     /*PTB13*/ PAL_MODE_UNCONNECTED,     /*PTB14*/ PAL_MODE_UNCONNECTED,
+        /*PTB15*/ PAL_MODE_UNCONNECTED,     /*PTB16*/ PAL_MODE_INPUT_ANALOG,    /*PTB17*/ PAL_MODE_INPUT_ANALOG,
+        /*PTB18*/ PAL_MODE_INPUT_ANALOG,    /*PTB19*/ PAL_MODE_INPUT_ANALOG,    /*PTB20*/ PAL_MODE_UNCONNECTED,
+        /*PTB21*/ PAL_MODE_UNCONNECTED,     /*PTB22*/ PAL_MODE_UNCONNECTED,     /*PTB23*/ PAL_MODE_UNCONNECTED,
+        /*PTB24*/ PAL_MODE_UNCONNECTED,     /*PTB25*/ PAL_MODE_UNCONNECTED,     /*PTB26*/ PAL_MODE_UNCONNECTED,
+        /*PTB27*/ PAL_MODE_UNCONNECTED,     /*PTB28*/ PAL_MODE_UNCONNECTED,     /*PTB29*/ PAL_MODE_UNCONNECTED,
+        /*PTB30*/ PAL_MODE_UNCONNECTED,     /*PTB31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT3,  // PORTC
+      .pads = {
+        /* PTC0*/ PAL_MODE_INPUT_ANALOG,    /* PTC1*/ PAL_MODE_INPUT_ANALOG,    /* PTC2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC3*/ PAL_MODE_INPUT,           /* PTC4*/ PAL_MODE_INPUT_ANALOG,    /* PTC5*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC6*/ PAL_MODE_INPUT_ANALOG,    /* PTC7*/ PAL_MODE_INPUT_ANALOG,    /* PTC8*/ PAL_MODE_INPUT_ANALOG,
+        /* PTC9*/ PAL_MODE_INPUT_ANALOG,    /*PTC10*/ PAL_MODE_INPUT_ANALOG,    /*PTC11*/ PAL_MODE_INPUT_ANALOG,
+        /*PTC12*/ PAL_MODE_UNCONNECTED,     /*PTC13*/ PAL_MODE_UNCONNECTED,     /*PTC14*/ PAL_MODE_UNCONNECTED,
+        /*PTC15*/ PAL_MODE_UNCONNECTED,     /*PTC16*/ PAL_MODE_UNCONNECTED,     /*PTC17*/ PAL_MODE_UNCONNECTED,
+        /*PTC18*/ PAL_MODE_UNCONNECTED,     /*PTC19*/ PAL_MODE_UNCONNECTED,     /*PTC20*/ PAL_MODE_UNCONNECTED,
+        /*PTC21*/ PAL_MODE_UNCONNECTED,     /*PTC22*/ PAL_MODE_UNCONNECTED,     /*PTC23*/ PAL_MODE_UNCONNECTED,
+        /*PTC24*/ PAL_MODE_UNCONNECTED,     /*PTC25*/ PAL_MODE_UNCONNECTED,     /*PTC26*/ PAL_MODE_UNCONNECTED,
+        /*PTC27*/ PAL_MODE_UNCONNECTED,     /*PTC28*/ PAL_MODE_UNCONNECTED,     /*PTC29*/ PAL_MODE_UNCONNECTED,
+        /*PTC30*/ PAL_MODE_UNCONNECTED,     /*PTC31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT4,  // PORTD
+      .pads = {
+        /* PTD0*/ PAL_MODE_INPUT_PULLUP,    /* PTD1*/ PAL_MODE_INPUT_ANALOG,    /* PTD2*/ PAL_MODE_INPUT_ANALOG,
+        /* PTD3*/ PAL_MODE_INPUT_ANALOG,    /* PTD4*/ PAL_MODE_INPUT_ANALOG,    /* PTD5*/ PAL_MODE_OUTPUT_PUSHPULL,
+        /* PTD6*/ PAL_MODE_INPUT_ANALOG,    /* PTD7*/ PAL_MODE_INPUT_ANALOG,    /* PTD8*/ PAL_MODE_UNCONNECTED,
+        /* PTD9*/ PAL_MODE_UNCONNECTED,     /*PTD10*/ PAL_MODE_UNCONNECTED,     /*PTD11*/ PAL_MODE_UNCONNECTED,
+        /*PTD12*/ PAL_MODE_UNCONNECTED,     /*PTD13*/ PAL_MODE_UNCONNECTED,     /*PTD14*/ PAL_MODE_UNCONNECTED,
+        /*PTD15*/ PAL_MODE_UNCONNECTED,     /*PTD16*/ PAL_MODE_UNCONNECTED,     /*PTD17*/ PAL_MODE_UNCONNECTED,
+        /*PTD18*/ PAL_MODE_UNCONNECTED,     /*PTD19*/ PAL_MODE_UNCONNECTED,     /*PTD20*/ PAL_MODE_UNCONNECTED,
+        /*PTD21*/ PAL_MODE_UNCONNECTED,     /*PTD22*/ PAL_MODE_UNCONNECTED,     /*PTD23*/ PAL_MODE_UNCONNECTED,
+        /*PTD24*/ PAL_MODE_UNCONNECTED,     /*PTD25*/ PAL_MODE_UNCONNECTED,     /*PTD26*/ PAL_MODE_UNCONNECTED,
+        /*PTD27*/ PAL_MODE_UNCONNECTED,     /*PTD28*/ PAL_MODE_UNCONNECTED,     /*PTD29*/ PAL_MODE_UNCONNECTED,
+        /*PTD30*/ PAL_MODE_UNCONNECTED,     /*PTD31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT5,  // PORTE
+      .pads = {
+        /* PTE0*/ PAL_MODE_INPUT_ANALOG,    /* PTE1*/ PAL_MODE_INPUT_ANALOG,    /* PTE2*/ PAL_MODE_UNCONNECTED,
+        /* PTE3*/ PAL_MODE_UNCONNECTED,     /* PTE4*/ PAL_MODE_UNCONNECTED,     /* PTE5*/ PAL_MODE_UNCONNECTED,
+        /* PTE6*/ PAL_MODE_UNCONNECTED,     /* PTE7*/ PAL_MODE_UNCONNECTED,     /* PTE8*/ PAL_MODE_UNCONNECTED,
+        /* PTE9*/ PAL_MODE_UNCONNECTED,     /*PTE10*/ PAL_MODE_UNCONNECTED,     /*PTE11*/ PAL_MODE_UNCONNECTED,
+        /*PTE12*/ PAL_MODE_UNCONNECTED,     /*PTE13*/ PAL_MODE_UNCONNECTED,     /*PTE14*/ PAL_MODE_UNCONNECTED,
+        /*PTE15*/ PAL_MODE_UNCONNECTED,     /*PTE16*/ PAL_MODE_UNCONNECTED,     /*PTE17*/ PAL_MODE_UNCONNECTED,
+        /*PTE18*/ PAL_MODE_UNCONNECTED,     /*PTE19*/ PAL_MODE_UNCONNECTED,     /*PTE20*/ PAL_MODE_INPUT_ANALOG,
+        /*PTE21*/ PAL_MODE_INPUT_ANALOG,    /*PTE22*/ PAL_MODE_INPUT,           /*PTE23*/ PAL_MODE_INPUT_ANALOG,
+        /*PTE24*/ PAL_MODE_ALTERNATIVE_5,   /*PTE25*/ PAL_MODE_ALTERNATIVE_5,   /*PTE26*/ PAL_MODE_UNCONNECTED,
+        /*PTE27*/ PAL_MODE_UNCONNECTED,     /*PTE28*/ PAL_MODE_UNCONNECTED,     /*PTE29*/ PAL_MODE_OUTPUT_PUSHPULL,
+        /*PTE30*/ PAL_MODE_INPUT_ANALOG,    /*PTE31*/ PAL_MODE_OUTPUT_PUSHPULL,
+      },
+    },
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  kl2x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h
new file mode 100644
index 000000000..838094a0a
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.h
@@ -0,0 +1,89 @@
+/*
+    ChibiOS - Copyright (C) 2016 flabbergast <[email protected]>
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Freescale Freedom KL26Z board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_FREESCALE_FREEDOM_KL26Z
+#define BOARD_NAME                  "Freescale Freedom KL26Z"
+/* External 8 MHz crystal. */
+#define KINETIS_XTAL_FREQUENCY      8000000UL
+/*
+ * MCU type
+ */
+#define KL26
+/*
+ * Onboard features.
+ */
+#define GPIO_LED_RED        IOPORT5
+#define PIN_LED_RED         29
+#define GPIO_LED_GREEN      IOPORT5
+#define PIN_LED_GREEN       31
+#define GPIO_LED_BLUE       IOPORT4
+#define PIN_LED_BLUE        5
+#define GPIO_BUTTON         IOPORT4
+#define PIN_BUTTON          0
+#define GPIO_LIGHT_SENSOR   IOPORT5
+#define PIN_LIGHT_SENSOR    22
+/* Inertial sensor: FXOS8700CQ */
+/* Default I2C address 0x1D */
+/* Note: the pins PTE24/25 are assigned to I2C0 by default;
+ *       if I2C0 is wanted on other pins, these need to be
+ *       assigned another function explicitly!
+ */
+#define I2C_GYRO I2C0
+#define LINE_LED_RED      PAL_LINE(GPIO_LED_RED, PIN_LED_RED)
+#define LINE_LED_GREEN    PAL_LINE(GPIO_LED_GREEN, PIN_LED_GREEN)
+#define LINE_LED_BLUE     PAL_LINE(GPIO_LED_BLUE, PIN_LED_BLUE)
+#define LINE_BUTTON       PAL_LINE(GPIO_BUTTON, PIN_BUTTON)
+#define LINE_LIGHT_SENSOR PAL_LINE(GPIO_LIGHT_SENSOR, PIN_LIGHT_SENSOR)
+#define LINE_GYRO_SCL     PAL_LINE(GPIOE, 24U)
+#define LINE_GYRO_SDA     PAL_LINE(GPIOE, 25U)
+#define LINE_GYRO_INT1    PAL_LINE(GPIOD, 0U)
+#define LINE_GYRO_INT2    PAL_LINE(GPIOD, 1U)
+/*
+ * Not configured:
+ *  - TSI Slider on PTB16/TSI0_CH9 and PTB17/TSI_CH10
+ *  - I2C inertial sensor on I2C0, routed to PTE25 and PTE25
+ *    Note: these pins are assigned to I2C0 by default;
+ *          if I2C0 is wanted on other pins, these need to be
+ *          assigned another function explicitly!
+ */
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk
new file mode 100644
index 000000000..9df27479e
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/FREESCALE_FREEDOM_KL26Z
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.c b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.c
new file mode 100644
index 000000000..109e36125
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.c
@@ -0,0 +1,127 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .ports = {
+    {
+      .port = IOPORT1,  // PORTA
+      .pads = {
+        /* PTA0*/ PAL_MODE_ALTERNATIVE_7,   /* PTA1*/ PAL_MODE_UNCONNECTED,     /* PTA2*/ PAL_MODE_UNCONNECTED,
+        /* PTA3*/ PAL_MODE_ALTERNATIVE_7,   /* PTA4*/ PAL_MODE_UNCONNECTED,     /* PTA5*/ PAL_MODE_UNCONNECTED,
+        /* PTA6*/ PAL_MODE_UNCONNECTED,     /* PTA7*/ PAL_MODE_UNCONNECTED,     /* PTA8*/ PAL_MODE_UNCONNECTED,
+        /* PTA9*/ PAL_MODE_UNCONNECTED,     /*PTA10*/ PAL_MODE_UNCONNECTED,     /*PTA11*/ PAL_MODE_UNCONNECTED,
+        /*PTA12*/ PAL_MODE_UNCONNECTED,     /*PTA13*/ PAL_MODE_UNCONNECTED,     /*PTA14*/ PAL_MODE_UNCONNECTED,
+        /*PTA15*/ PAL_MODE_UNCONNECTED,     /*PTA16*/ PAL_MODE_UNCONNECTED,     /*PTA17*/ PAL_MODE_UNCONNECTED,
+        /*PTA18*/ PAL_MODE_UNCONNECTED,     /*PTA19*/ PAL_MODE_UNCONNECTED,     /*PTA20*/ PAL_MODE_UNCONNECTED,
+        /*PTA21*/ PAL_MODE_UNCONNECTED,     /*PTA22*/ PAL_MODE_UNCONNECTED,     /*PTA23*/ PAL_MODE_UNCONNECTED,
+        /*PTA24*/ PAL_MODE_UNCONNECTED,     /*PTA25*/ PAL_MODE_UNCONNECTED,     /*PTA26*/ PAL_MODE_UNCONNECTED,
+        /*PTA27*/ PAL_MODE_UNCONNECTED,     /*PTA28*/ PAL_MODE_UNCONNECTED,     /*PTA29*/ PAL_MODE_UNCONNECTED,
+        /*PTA30*/ PAL_MODE_UNCONNECTED,     /*PTA31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT2,  // PORTB
+      .pads = {
+        /* PTB0*/ PAL_MODE_UNCONNECTED,     /* PTB1*/ PAL_MODE_UNCONNECTED,     /* PTB2*/ PAL_MODE_UNCONNECTED,
+        /* PTB3*/ PAL_MODE_UNCONNECTED,     /* PTB4*/ PAL_MODE_UNCONNECTED,     /* PTB5*/ PAL_MODE_UNCONNECTED,
+        /* PTB6*/ PAL_MODE_UNCONNECTED,     /* PTB7*/ PAL_MODE_UNCONNECTED,     /* PTB8*/ PAL_MODE_UNCONNECTED,
+        /* PTB9*/ PAL_MODE_UNCONNECTED,     /*PTB10*/ PAL_MODE_UNCONNECTED,     /*PTB11*/ PAL_MODE_UNCONNECTED,
+        /*PTB12*/ PAL_MODE_UNCONNECTED,     /*PTB13*/ PAL_MODE_UNCONNECTED,     /*PTB14*/ PAL_MODE_UNCONNECTED,
+        /*PTB15*/ PAL_MODE_UNCONNECTED,     /*PTB16*/ PAL_MODE_OUTPUT_PUSHPULL, /*PTB17*/ PAL_MODE_UNCONNECTED,
+        /*PTB18*/ PAL_MODE_UNCONNECTED,     /*PTB19*/ PAL_MODE_UNCONNECTED,     /*PTB20*/ PAL_MODE_UNCONNECTED,
+        /*PTB21*/ PAL_MODE_UNCONNECTED,     /*PTB22*/ PAL_MODE_UNCONNECTED,     /*PTB23*/ PAL_MODE_UNCONNECTED,
+        /*PTB24*/ PAL_MODE_UNCONNECTED,     /*PTB25*/ PAL_MODE_UNCONNECTED,     /*PTB26*/ PAL_MODE_UNCONNECTED,
+        /*PTB27*/ PAL_MODE_UNCONNECTED,     /*PTB28*/ PAL_MODE_UNCONNECTED,     /*PTB29*/ PAL_MODE_UNCONNECTED,
+        /*PTB30*/ PAL_MODE_UNCONNECTED,     /*PTB31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT3,  // PORTC
+      .pads = {
+        /* PTC0*/ PAL_MODE_UNCONNECTED,     /* PTC1*/ PAL_MODE_UNCONNECTED,     /* PTC2*/ PAL_MODE_UNCONNECTED,
+        /* PTC3*/ PAL_MODE_UNCONNECTED,     /* PTC4*/ PAL_MODE_UNCONNECTED,     /* PTC5*/ PAL_MODE_UNCONNECTED,
+        /* PTC6*/ PAL_MODE_UNCONNECTED,     /* PTC7*/ PAL_MODE_UNCONNECTED,     /* PTC8*/ PAL_MODE_UNCONNECTED,
+        /* PTC9*/ PAL_MODE_UNCONNECTED,     /*PTC10*/ PAL_MODE_UNCONNECTED,     /*PTC11*/ PAL_MODE_UNCONNECTED,
+        /*PTC12*/ PAL_MODE_UNCONNECTED,     /*PTC13*/ PAL_MODE_UNCONNECTED,     /*PTC14*/ PAL_MODE_UNCONNECTED,
+        /*PTC15*/ PAL_MODE_UNCONNECTED,     /*PTC16*/ PAL_MODE_UNCONNECTED,     /*PTC17*/ PAL_MODE_UNCONNECTED,
+        /*PTC18*/ PAL_MODE_UNCONNECTED,     /*PTC19*/ PAL_MODE_UNCONNECTED,     /*PTC20*/ PAL_MODE_UNCONNECTED,
+        /*PTC21*/ PAL_MODE_UNCONNECTED,     /*PTC22*/ PAL_MODE_UNCONNECTED,     /*PTC23*/ PAL_MODE_UNCONNECTED,
+        /*PTC24*/ PAL_MODE_UNCONNECTED,     /*PTC25*/ PAL_MODE_UNCONNECTED,     /*PTC26*/ PAL_MODE_UNCONNECTED,
+        /*PTC27*/ PAL_MODE_UNCONNECTED,     /*PTC28*/ PAL_MODE_UNCONNECTED,     /*PTC29*/ PAL_MODE_UNCONNECTED,
+        /*PTC30*/ PAL_MODE_UNCONNECTED,     /*PTC31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT4,  // PORTD
+      .pads = {
+        /* PTD0*/ PAL_MODE_UNCONNECTED,     /* PTD1*/ PAL_MODE_UNCONNECTED,     /* PTD2*/ PAL_MODE_UNCONNECTED,
+        /* PTD3*/ PAL_MODE_UNCONNECTED,     /* PTD4*/ PAL_MODE_UNCONNECTED,     /* PTD5*/ PAL_MODE_UNCONNECTED,
+        /* PTD6*/ PAL_MODE_UNCONNECTED,     /* PTD7*/ PAL_MODE_UNCONNECTED,     /* PTD8*/ PAL_MODE_UNCONNECTED,
+        /* PTD9*/ PAL_MODE_UNCONNECTED,     /*PTD10*/ PAL_MODE_UNCONNECTED,     /*PTD11*/ PAL_MODE_UNCONNECTED,
+        /*PTD12*/ PAL_MODE_UNCONNECTED,     /*PTD13*/ PAL_MODE_UNCONNECTED,     /*PTD14*/ PAL_MODE_UNCONNECTED,
+        /*PTD15*/ PAL_MODE_UNCONNECTED,     /*PTD16*/ PAL_MODE_UNCONNECTED,     /*PTD17*/ PAL_MODE_UNCONNECTED,
+        /*PTD18*/ PAL_MODE_UNCONNECTED,     /*PTD19*/ PAL_MODE_UNCONNECTED,     /*PTD20*/ PAL_MODE_UNCONNECTED,
+        /*PTD21*/ PAL_MODE_UNCONNECTED,     /*PTD22*/ PAL_MODE_UNCONNECTED,     /*PTD23*/ PAL_MODE_UNCONNECTED,
+        /*PTD24*/ PAL_MODE_UNCONNECTED,     /*PTD25*/ PAL_MODE_UNCONNECTED,     /*PTD26*/ PAL_MODE_UNCONNECTED,
+        /*PTD27*/ PAL_MODE_UNCONNECTED,     /*PTD28*/ PAL_MODE_UNCONNECTED,     /*PTD29*/ PAL_MODE_UNCONNECTED,
+        /*PTD30*/ PAL_MODE_UNCONNECTED,     /*PTD31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+    {
+      .port = IOPORT5,  // PORTE
+      .pads = {
+        /* PTE0*/ PAL_MODE_UNCONNECTED,     /* PTE1*/ PAL_MODE_UNCONNECTED,     /* PTE2*/ PAL_MODE_UNCONNECTED,
+        /* PTE3*/ PAL_MODE_UNCONNECTED,     /* PTE4*/ PAL_MODE_UNCONNECTED,     /* PTE5*/ PAL_MODE_UNCONNECTED,
+        /* PTE6*/ PAL_MODE_UNCONNECTED,     /* PTE7*/ PAL_MODE_UNCONNECTED,     /* PTE8*/ PAL_MODE_UNCONNECTED,
+        /* PTE9*/ PAL_MODE_UNCONNECTED,     /*PTE10*/ PAL_MODE_UNCONNECTED,     /*PTE11*/ PAL_MODE_UNCONNECTED,
+        /*PTE12*/ PAL_MODE_UNCONNECTED,     /*PTE13*/ PAL_MODE_UNCONNECTED,     /*PTE14*/ PAL_MODE_UNCONNECTED,
+        /*PTE15*/ PAL_MODE_UNCONNECTED,     /*PTE16*/ PAL_MODE_UNCONNECTED,     /*PTE17*/ PAL_MODE_UNCONNECTED,
+        /*PTE18*/ PAL_MODE_UNCONNECTED,     /*PTE19*/ PAL_MODE_UNCONNECTED,     /*PTE20*/ PAL_MODE_UNCONNECTED,
+        /*PTE21*/ PAL_MODE_UNCONNECTED,     /*PTE22*/ PAL_MODE_UNCONNECTED,     /*PTE23*/ PAL_MODE_UNCONNECTED,
+        /*PTE24*/ PAL_MODE_UNCONNECTED,     /*PTE25*/ PAL_MODE_UNCONNECTED,     /*PTE26*/ PAL_MODE_UNCONNECTED,
+        /*PTE27*/ PAL_MODE_UNCONNECTED,     /*PTE28*/ PAL_MODE_UNCONNECTED,     /*PTE29*/ PAL_MODE_UNCONNECTED,
+        /*PTE30*/ PAL_MODE_UNCONNECTED,     /*PTE31*/ PAL_MODE_UNCONNECTED,
+      },
+    },
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  k20x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.h b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.h
new file mode 100644
index 000000000..701d55dd9
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.h
@@ -0,0 +1,49 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for MCHCL K20 board with MX20DX128 processor.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_MCHCK_K20_MX20DX128
+#define BOARD_NAME                  "MCHCK K20 MX20DX128"
+/*
+ * MCU type
+ */
+#define K20x5
+#define GPIOB_LED   16
+#define LINE_LED    PAL_LINE(GPIOB, GPIOB_LED)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.mk b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.mk
new file mode 100644
index 000000000..cbd24d791
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MCHCK_K20/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MCHCK_K20
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c
new file mode 100644
index 000000000..12f78e29b
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c
@@ -0,0 +1,91 @@
+/*
+    Copyright (C) 2017 Stéphane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* RAM Banks
+ *  (Values are defined in Nordic gcc_startup_nrf51.s)
+ */
+#define NRF_POWER_RAMON_ADDRESS 0x40000524
+#define NRF_POWER_RAMONB_ADDRESS 0x40000554
+#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .pads = {
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.0 : SCL      P19   */
+        PAL_MODE_UNCONNECTED,         /* P0.1 : PAD1     P2    */
+        PAL_MODE_UNCONNECTED,         /* P0.2 : PAD2     P1    */
+        PAL_MODE_UNCONNECTED,         /* P0.3 : PAD3     P0    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.4 : COL1     P3    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5 : COL2     P4    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.6 : COL3     P10   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.7 : COL4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.8 : COL5           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.9 : COL6           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.10: COL7     P9    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.11: COL8     P7    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.12: COL9     P6    */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.13: ROW1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.14: ROW2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.15: ROW3           */
+        PAL_MODE_UNCONNECTED,         /* P0.16           P16   */
+        PAL_MODE_INPUT,               /* P0.17: BTN_A    P5    */
+        PAL_MODE_UNCONNECTED,         /* P0.18           P8    */
+        PAL_MODE_INPUT,               /* P0.19: BTN_RST        */
+        PAL_MODE_UNCONNECTED,         /* P0.20           P12   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.21: SPI_MOSI P15   */
+        PAL_MODE_INPUT_PULLUP,        /* P0.22: SPI_MISO P14   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.23: SPI_SCK  P13   */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.25: UART_RX        */
+        PAL_MODE_INPUT,               /* P0.26: BTN_B    P11   */
+        PAL_MODE_INPUT,               /* P0.27: ACC_INT2       */
+        PAL_MODE_INPUT,               /* P0.28: ACC_INT1       */
+        PAL_MODE_INPUT,               /* P0.29: MAG_INT1       */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.30: SDA      P20   */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+  /* Make sure ALL RAM banks are powered on */
+  *(uint32_t *)NRF_POWER_RAMON_ADDRESS  |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+  *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+}
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h
new file mode 100644
index 000000000..157bd7502
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h
@@ -0,0 +1,147 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * See: https://www.microbit.co.uk/device/pins
+ *      https://lancaster-university.github.io/microbit-docs/ubit/display/
+ */
+/* Board identifier. */
+#define BOARD_MICROBIT
+#define BOARD_NAME              "micro:bit"
+/* Board oscillators-related settings. */
+#define NRF51_XTAL_VALUE        16000000
+#define NRF51_LFCLK_SOURCE      0  /* RC oscillator */
+/*
+ * IO pins assignments.
+ */
+#define IOPORT1_P0              3U
+#define IOPORT1_P1              2U
+#define IOPORT1_P2              1U
+#define IOPORT1_P3              4U
+#define IOPORT1_P4              5U
+#define IOPORT1_P5             17U
+#define IOPORT1_P6             12U
+#define IOPORT1_P7             11U
+#define IOPORT1_P8             18U
+#define IOPORT1_P9             10U
+#define IOPORT1_P10             6U
+#define IOPORT1_P11            26U
+#define IOPORT1_P12            20U
+#define IOPORT1_P13            23U
+#define IOPORT1_P14            22U
+#define IOPORT1_P15            21U
+#define IOPORT1_P16            16U
+#define IOPORT1_P19             0U
+#define IOPORT1_P20            30U
+#define IOPORT1_BTN_A          17U
+#define IOPORT1_BTN_B          26U
+#define IOPORT1_BTN_RST        19U  
+#define IOPORT1_LED_COL_1       4U
+#define IOPORT1_LED_COL_2       5U
+#define IOPORT1_LED_COL_3       6U
+#define IOPORT1_LED_COL_4       7U
+#define IOPORT1_LED_COL_5       8U
+#define IOPORT1_LED_COL_6       9U
+#define IOPORT1_LED_COL_7      10U
+#define IOPORT1_LED_COL_8      11U
+#define IOPORT1_LED_COL_9      12U
+#define IOPORT1_LED_ROW_1      13U
+#define IOPORT1_LED_ROW_2      14U
+#define IOPORT1_LED_ROW_3      15U
+#define IOPORT1_PAD_0             IOPORT1_P0
+#define IOPORT1_PAD_1             IOPORT1_P1
+#define IOPORT1_PAD_2             IOPORT1_P2
+#define IOPORT1_SPI_MOSI       21U
+#define IOPORT1_SPI_MISO       22U
+#define IOPORT1_SPI_SCK        23U
+#define IOPORT1_I2C_SCL         0U
+#define IOPORT1_I2C_SDA        30U
+#define IOPORT1_UART_TX        24U
+#define IOPORT1_UART_RX        25U
+#define IOPORT1_ACC_INT1       28U
+#define IOPORT1_ACC_INT2       27U
+#define IOPORT1_MAG_INT1       29U
+/*
+ * IO lines assignments.
+ */
+#define LINE_P0                PAL_LINE(IOPORT1, IOPORT1_P0)
+#define LINE_P1                PAL_LINE(IOPORT1, IOPORT1_P1)
+#define LINE_P2                PAL_LINE(IOPORT1, IOPORT1_P2)
+#define LINE_P3                PAL_LINE(IOPORT1, IOPORT1_P3)
+#define LINE_P4                PAL_LINE(IOPORT1, IOPORT1_P4)
+#define LINE_P5                PAL_LINE(IOPORT1, IOPORT1_P5)
+#define LINE_P6                PAL_LINE(IOPORT1, IOPORT1_P6)
+#define LINE_P7                PAL_LINE(IOPORT1, IOPORT1_P7)
+#define LINE_P8                PAL_LINE(IOPORT1, IOPORT1_P8)
+#define LINE_P9                PAL_LINE(IOPORT1, IOPORT1_P9)
+#define LINE_P10               PAL_LINE(IOPORT1, IOPORT1_P10)
+#define LINE_P11               PAL_LINE(IOPORT1, IOPORT1_P11)
+#define LINE_P12               PAL_LINE(IOPORT1, IOPORT1_P12)
+#define LINE_P13               PAL_LINE(IOPORT1, IOPORT1_P13)
+#define LINE_P14               PAL_LINE(IOPORT1, IOPORT1_P14)
+#define LINE_P15               PAL_LINE(IOPORT1, IOPORT1_P15)
+#define LINE_P16               PAL_LINE(IOPORT1, IOPORT1_P16)
+#define LINE_P19               PAL_LINE(IOPORT1, IOPORT1_P19)
+#define LINE_P20               PAL_LINE(IOPORT1, IOPORT1_P20)
+#define LINE_BTN_A             PAL_LINE(IOPORT1, IOPORT1_BTN_A)
+#define LINE_BTN_B             PAL_LINE(IOPORT1, IOPORT1_BTN_B)
+#define LINE_BTN_RST           PAL_LINE(IOPORT1, IOPORT1_BTN_RST)
+#define LINE_LED_COL_1         PAL_LINE(IOPORT1, IOPORT1_LED_COL_1)
+#define LINE_LED_COL_2         PAL_LINE(IOPORT1, IOPORT1_LED_COL_2)
+#define LINE_LED_COL_3         PAL_LINE(IOPORT1, IOPORT1_LED_COL_3)
+#define LINE_LED_COL_4         PAL_LINE(IOPORT1, IOPORT1_LED_COL_4)
+#define LINE_LED_COL_5         PAL_LINE(IOPORT1, IOPORT1_LED_COL_5)
+#define LINE_LED_COL_6         PAL_LINE(IOPORT1, IOPORT1_LED_COL_6)
+#define LINE_LED_COL_7         PAL_LINE(IOPORT1, IOPORT1_LED_COL_7)
+#define LINE_LED_COL_8         PAL_LINE(IOPORT1, IOPORT1_LED_COL_8)
+#define LINE_LED_COL_9         PAL_LINE(IOPORT1, IOPORT1_LED_COL_9)
+#define LINE_LED_ROW_1         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1)
+#define LINE_LED_ROW_2         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2)
+#define LINE_LED_ROW_3         PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3)
+#define LINE_PAD_0             PAL_LINE(IOPORT1, IOPORT1_PAD_0)
+#define LINE_PAD_1             PAL_LINE(IOPORT1, IOPORT1_PAD_1)
+#define LINE_PAD_2             PAL_LINE(IOPORT1, IOPORT1_PAD_2)
+#define LINE_SPI_MOSI          PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO          PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SCK           PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_I2C_SCL           PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA           PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+#define LINE_UART_TX           PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_RX           PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_ACC_INT1          PAL_LINE(IOPORT1, IOPORT1_ACC_INT1)
+#define LINE_ACC_INT2          PAL_LINE(IOPORT1, IOPORT1_ACC_INT2)
+#define LINE_MAG_INT1          PAL_LINE(IOPORT1, IOPORT1_MAG_INT1)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk
new file mode 100644
index 000000000..8e26ae6a2
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
new file mode 100644
index 000000000..09b44f777
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
@@ -0,0 +1,261 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#include "stm32_gpio.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_setup_t          PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_setup_t          PKData;
+#endif
+} gpio_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}
+#endif
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+static void stm32_gpio_init(void) {
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB1(STM32_GPIO_EN_MASK);
+  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+  gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+  gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  stm32_gpio_init();
+  stm32_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
new file mode 100644
index 000000000..0788eb7fe
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h
@@ -0,0 +1,1150 @@
+/*
+    ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for STMicroelectronics STM32F4-Discovery board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_NAME                  "NAND and SRAM test board (codename Buod)"
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768
+#endif
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                12000000
+#endif
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F407xx
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0                  0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_SPI1_NSS              4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_USB_PRESENT           9
+#define GPIOA_PIN10                 10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOA_JTMS                  13
+#define GPIOA_JTCK                  14
+#define GPIOA_JTDI                  15
+#define GPIOA_USB_PRESENT           9
+#define GPIOA_PIN10                 10
+#define GPIOA_OTG_FS_DM             11
+#define GPIOA_OTG_FS_DP             12
+#define GPIOB_PIN0                  0
+#define GPIOB_NAND_WP               1
+#define GPIOB_PIN2                  2
+#define GPIOB_JTDO                  3
+#define GPIOB_JTRST                 4
+#define GPIOB_NVRAM_PWR             5
+#define GPIOB_PIN6                  6
+#define GPIOB_PIN7                  7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_PIN8                  8
+#define GPIOC_PIN9                  9
+#define GPIOC_PIN10                 10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_PIN14                 14
+#define GPIOC_PIN15                 15
+#define GPIOD_MEM_D2                0
+#define GPIOD_MEM_D3                1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_MEM_OE                4
+#define GPIOD_MEM_WE                5
+#define GPIOD_NAND_RB_NWAIT         6
+#define GPIOD_NAND_CE1              7
+#define GPIOD_MEM_D13               8
+#define GPIOD_MEM_D14               9
+#define GPIOD_MEM_D15               10
+#define GPIOD_MEM_A16               11
+#define GPIOD_MEM_A17               12
+#define GPIOD_PIN13                 13
+#define GPIOD_MEM_D0                14
+#define GPIOD_MEM_D1                15
+#define GPIOE_SRAM_LB               0
+#define GPIOE_SRAM_UB               1
+#define GPIOE_PIN2                  2
+#define GPIOE_PIN3                  3
+#define GPIOE_PIN4                  4
+#define GPIOE_PIN5                  5
+#define GPIOE_PIN6                  6
+#define GPIOE_MEM_D4                7
+#define GPIOE_MEM_D5                8
+#define GPIOE_MEM_D6                9
+#define GPIOE_MEM_D7                10
+#define GPIOE_MEM_D8                11
+#define GPIOE_MEM_D9                12
+#define GPIOE_MEM_D10               13
+#define GPIOE_MEM_D11               14
+#define GPIOE_MEM_D12               15
+#define GPIOF_MEM_A0                0
+#define GPIOF_MEM_A1                1
+#define GPIOF_MEM_A2                2
+#define GPIOF_MEM_A3                3
+#define GPIOF_MEM_A4                4
+#define GPIOF_MEM_A5                5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_MEM_A6                12
+#define GPIOF_MEM_A7                13
+#define GPIOF_MEM_A8                14
+#define GPIOF_MEM_A9                15
+#define GPIOG_MEM_A10               0
+#define GPIOG_MEM_A11               1
+#define GPIOG_MEM_A12               2
+#define GPIOG_MEM_A13               3
+#define GPIOG_MEM_A14               4
+#define GPIOG_MEM_A15               5
+#define GPIOG_NAND_RB1              6
+#define GPIOG_NAND_RB2              7
+#define GPIOG_PIN8                  8
+#define GPIOG_NAND_CE2              9
+#define GPIOG_PIN10                 10
+#define GPIOG_PIN11                 11
+#define GPIOG_SRAM_CS1              12
+#define GPIOG_PIN13                 13
+#define GPIOG_PIN14                 14
+#define GPIOG_PIN15                 15
+#define GPIOH_OSC_IN                0
+#define GPIOH_OSC_OUT               1
+#define GPIOH_PIN2                  2
+#define GPIOH_PIN3                  3
+#define GPIOH_PIN4                  4
+#define GPIOH_PIN5                  5
+#define GPIOH_PIN6                  6
+#define GPIOH_I2C3_SCL              7
+#define GPIOH_I2C3_SDA              8
+#define GPIOH_PIN9                  9
+#define GPIOH_PIN10                 10
+#define GPIOH_PIN11                 11
+#define GPIOH_PIN12                 12
+#define GPIOH_PIN13                 13
+#define GPIOH_PIN14                 14
+#define GPIOH_PIN15                 15
+#define GPIOI_PIN0                  0
+#define GPIOI_PIN1                  1
+#define GPIOI_PIN2                  2
+#define GPIOI_PIN3                  3
+#define GPIOI_PIN4                  4
+#define GPIOI_PIN5                  5
+#define GPIOI_PIN6                  6
+#define GPIOI_PIN7                  7
+#define GPIOI_PIN8                  8
+#define GPIOI_PIN9                  9
+#define GPIOI_LED_R                 10
+#define GPIOI_LED_G                 11
+#define GPIOI_PIN12                 12
+#define GPIOI_PIN13                 13
+#define GPIOI_PIN14                 14
+#define GPIOI_PIN15                 15
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n)           (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n)          (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+/*
+ * GPIOA setup:
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_SPI1_NSS) |   \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_USB_PRESENT) |    \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTMS) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTCK) |       \
+                                     PIN_MODE_ALTERNATE(GPIOA_JTDI))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SPI1_NSS) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_USB_PRESENT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTMS) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTCK) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_JTDI))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_100M(GPIOA_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOA_SPI1_NSS) |      \
+                                     PIN_OSPEED_100M(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOA_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOA_USB_PRESENT) |   \
+                                     PIN_OSPEED_100M(GPIOA_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_100M(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_100M(GPIOA_JTMS) |          \
+                                     PIN_OSPEED_100M(GPIOA_JTCK) |          \
+                                     PIN_OSPEED_100M(GPIOA_JTDI))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_SPI1_NSS) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_USB_PRESENT) |\
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTMS) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTCK) |       \
+                                     PIN_PUPDR_FLOATING(GPIOA_JTDI))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_SPI1_NSS) |         \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_USB_PRESENT) |      \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_JTMS) |             \
+                                     PIN_ODR_HIGH(GPIOA_JTCK) |             \
+                                     PIN_ODR_HIGH(GPIOA_JTDI))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_SPI1_NSS, 5) |       \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_USB_PRESENT, 0) |    \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) |     \
+                                     PIN_AFIO_AF(GPIOA_JTMS, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_JTCK, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_JTDI, 0))
+/*
+ * GPIOB setup:
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_OUTPUT(GPIOB_NAND_WP) |       \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTDO) |       \
+                                     PIN_MODE_ALTERNATE(GPIOB_JTRST) |      \
+                                     PIN_MODE_OUTPUT(GPIOB_NVRAM_PWR) |     \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_NAND_WP) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTDO) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_JTRST) |      \
+                                     PIN_OTYPE_OPENDRAIN(GPIOB_NVRAM_PWR) | \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_100M(GPIOB_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOB_NAND_WP) |       \
+                                     PIN_OSPEED_100M(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOB_JTDO) |          \
+                                     PIN_OSPEED_100M(GPIOB_JTRST) |         \
+                                     PIN_OSPEED_2M(GPIOB_NVRAM_PWR) |       \
+                                     PIN_OSPEED_100M(GPIOB_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOB_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_PIN0) |       \
+                                     PIN_PUPDR_PULLDOWN(GPIOB_NAND_WP) |    \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTDO) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_JTRST) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_NVRAM_PWR) |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_LOW(GPIOB_NAND_WP) |           \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_JTDO) |             \
+                                     PIN_ODR_HIGH(GPIOB_JTRST) |            \
+                                     PIN_ODR_LOW(GPIOB_NVRAM_PWR) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_NAND_WP, 0) |        \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_JTDO, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_JTRST, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_NVRAM_PWR, 0) |      \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+/*
+ * GPIOC setup:
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_100M(GPIOC_PIN0) |\
+                                     PIN_OSPEED_100M(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOC_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0))
+/*
+ * GPIOD setup:
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_ALTERNATE(GPIOD_MEM_D2) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D3) |     \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_OE) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_WE) |     \
+                                     PIN_MODE_INPUT(GPIOD_NAND_RB_NWAIT) |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_NAND_CE1) |   \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D13) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D14) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D15) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_A16) |    \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_A17) |    \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D0) |     \
+                                     PIN_MODE_ALTERNATE(GPIOD_MEM_D1))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_MEM_D2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_OE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_WE) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_NAND_RB_NWAIT) |\
+                                     PIN_OTYPE_PUSHPULL(GPIOD_NAND_CE1) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D13) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D14) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D15) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_A16) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_A17) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MEM_D1))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_100M(GPIOD_MEM_D2) |        \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D3) |        \
+                                     PIN_OSPEED_100M(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOD_MEM_OE) |        \
+                                     PIN_OSPEED_100M(GPIOD_MEM_WE) |        \
+                                     PIN_OSPEED_100M(GPIOD_NAND_RB_NWAIT) | \
+                                     PIN_OSPEED_100M(GPIOD_NAND_CE1) |      \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D13) |       \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D14) |       \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D15) |       \
+                                     PIN_OSPEED_100M(GPIOD_MEM_A16) |       \
+                                     PIN_OSPEED_100M(GPIOD_MEM_A17) |       \
+                                     PIN_OSPEED_100M(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D0) |        \
+                                     PIN_OSPEED_100M(GPIOD_MEM_D1))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_OE) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_WE) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\
+                                     PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D13) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D14) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D15) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_A16) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_A17) |    \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D0) |     \
+                                     PIN_PUPDR_FLOATING(GPIOD_MEM_D1))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_MEM_D2) |           \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D3) |           \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_MEM_OE) |           \
+                                     PIN_ODR_HIGH(GPIOD_MEM_WE) |           \
+                                     PIN_ODR_HIGH(GPIOD_NAND_RB_NWAIT) |    \
+                                     PIN_ODR_HIGH(GPIOD_NAND_CE1) |         \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D13) |          \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D14) |          \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D15) |          \
+                                     PIN_ODR_HIGH(GPIOD_MEM_A16) |          \
+                                     PIN_ODR_HIGH(GPIOD_MEM_A17) |          \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D0) |           \
+                                     PIN_ODR_HIGH(GPIOD_MEM_D1))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_MEM_D2, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_MEM_D3, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_MEM_OE, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_MEM_WE, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_NAND_RB_NWAIT, 0) |  \
+                                     PIN_AFIO_AF(GPIOD_NAND_CE1, 12))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_MEM_D13, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_MEM_D14, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_MEM_D15, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_MEM_A16, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_MEM_A17, 12) |       \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_MEM_D0, 12) |        \
+                                     PIN_AFIO_AF(GPIOD_MEM_D1, 12))
+/*
+ * GPIOE setup:
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_ALTERNATE(GPIOE_SRAM_LB) |    \
+                                     PIN_MODE_ALTERNATE(GPIOE_SRAM_UB) |    \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D5) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D6) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D8) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D9) |     \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D10) |    \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D11) |    \
+                                     PIN_MODE_ALTERNATE(GPIOE_MEM_D12))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_SRAM_LB) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_SRAM_UB) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D8) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D9) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D10) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D11) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MEM_D12))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_100M(GPIOE_SRAM_LB) |       \
+                                     PIN_OSPEED_100M(GPIOE_SRAM_UB) |       \
+                                     PIN_OSPEED_100M(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D4) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D5) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D6) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D7) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D8) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D9) |        \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D10) |       \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D11) |       \
+                                     PIN_OSPEED_100M(GPIOE_MEM_D12))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_SRAM_LB) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_SRAM_UB) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D5) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D6) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D8) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D9) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D10) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D11) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MEM_D12))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_SRAM_LB) |          \
+                                     PIN_ODR_HIGH(GPIOE_SRAM_UB) |          \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D4) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D5) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D6) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D7) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D8) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D9) |           \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D10) |          \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D11) |          \
+                                     PIN_ODR_HIGH(GPIOE_MEM_D12))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_SRAM_LB, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_SRAM_UB, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOE_MEM_D4, 12))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_MEM_D5, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_MEM_D6, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_MEM_D7, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_MEM_D8, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_MEM_D9, 12) |        \
+                                     PIN_AFIO_AF(GPIOE_MEM_D10, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_MEM_D11, 12) |       \
+                                     PIN_AFIO_AF(GPIOE_MEM_D12, 12))
+/*
+ * GPIOF setup:
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_ALTERNATE(GPIOF_MEM_A0) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A1) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A2) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A3) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A4) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A5) |     \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A6) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A7) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A8) |     \
+                                     PIN_MODE_ALTERNATE(GPIOF_MEM_A9))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_MEM_A0) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A1) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A2) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A3) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A4) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A5) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A6) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A7) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A8) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_MEM_A9))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_100M(GPIOF_MEM_A0) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A1) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A2) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A3) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A4) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A5) |        \
+                                     PIN_OSPEED_100M(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOF_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A6) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A7) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A8) |        \
+                                     PIN_OSPEED_100M(GPIOF_MEM_A9))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_MEM_A0) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A1) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A2) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A3) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A4) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A5) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A6) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A7) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A8) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_MEM_A9))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_MEM_A0) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A1) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A2) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A3) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A4) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A5) |           \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A6) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A7) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A8) |           \
+                                     PIN_ODR_HIGH(GPIOF_MEM_A9))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_MEM_A0, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A1, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A2, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A3, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A4, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A5, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_MEM_A6, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A7, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A8, 12) |        \
+                                     PIN_AFIO_AF(GPIOF_MEM_A9, 12))
+/*
+ * GPIOG setup:
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_ALTERNATE(GPIOG_MEM_A10) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_MEM_A11) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_MEM_A12) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_MEM_A13) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_MEM_A14) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_MEM_A15) |    \
+                                     PIN_MODE_ALTERNATE(GPIOG_NAND_RB1) |   \
+                                     PIN_MODE_ALTERNATE(GPIOG_NAND_RB2) |   \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_ALTERNATE(GPIOG_NAND_CE2) |   \
+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOG_SRAM_CS1) |   \
+                                     PIN_MODE_INPUT(GPIOG_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_MEM_A10) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_MEM_A11) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_MEM_A12) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_MEM_A13) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_MEM_A14) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_MEM_A15) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB1) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_NAND_RB2) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_NAND_CE2) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_SRAM_CS1) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_100M(GPIOG_MEM_A10) |       \
+                                     PIN_OSPEED_100M(GPIOG_MEM_A11) |       \
+                                     PIN_OSPEED_100M(GPIOG_MEM_A12) |       \
+                                     PIN_OSPEED_100M(GPIOG_MEM_A13) |       \
+                                     PIN_OSPEED_100M(GPIOG_MEM_A14) |       \
+                                     PIN_OSPEED_100M(GPIOG_MEM_A15) |       \
+                                     PIN_OSPEED_100M(GPIOG_NAND_RB1) |      \
+                                     PIN_OSPEED_100M(GPIOG_NAND_RB2) |      \
+                                     PIN_OSPEED_100M(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOG_NAND_CE2) |      \
+                                     PIN_OSPEED_100M(GPIOG_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOG_SRAM_CS1) |      \
+                                     PIN_OSPEED_100M(GPIOG_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_MEM_A11) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_MEM_A12) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_MEM_A13) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_MEM_A14) |    \
+                                     PIN_PUPDR_FLOATING(GPIOG_MEM_A15) |    \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) |   \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN8) |       \
+                                     PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) |     \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) |   \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_MEM_A10) |          \
+                                     PIN_ODR_HIGH(GPIOG_MEM_A11) |          \
+                                     PIN_ODR_HIGH(GPIOG_MEM_A12) |          \
+                                     PIN_ODR_HIGH(GPIOG_MEM_A13) |          \
+                                     PIN_ODR_HIGH(GPIOG_MEM_A14) |          \
+                                     PIN_ODR_HIGH(GPIOG_MEM_A15) |          \
+                                     PIN_ODR_HIGH(GPIOG_NAND_RB1) |         \
+                                     PIN_ODR_HIGH(GPIOG_NAND_RB2) |         \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_NAND_CE2) |         \
+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOG_SRAM_CS1) |         \
+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_MEM_A10, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_MEM_A11, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_MEM_A12, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_MEM_A13, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_MEM_A14, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_MEM_A15, 12) |       \
+                                     PIN_AFIO_AF(GPIOG_NAND_RB1, 12) |      \
+                                     PIN_AFIO_AF(GPIOG_NAND_RB2, 12))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOG_NAND_CE2, 12) |      \
+                                     PIN_AFIO_AF(GPIOG_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_SRAM_CS1, 12) |      \
+                                     PIN_AFIO_AF(GPIOG_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0))
+/*
+ * GPIOH setup:
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOH_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_ALTERNATE(GPIOH_I2C3_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOH_I2C3_SDA) |   \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SCL) |  \
+                                     PIN_OTYPE_OPENDRAIN(GPIOH_I2C3_SDA) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_100M(GPIOH_OSC_IN) |        \
+                                     PIN_OSPEED_100M(GPIOH_OSC_OUT) |       \
+                                     PIN_OSPEED_100M(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_2M(GPIOH_I2C3_SCL) |        \
+                                     PIN_OSPEED_2M(GPIOH_I2C3_SDA) |        \
+                                     PIN_OSPEED_100M(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_I2C3_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOH_I2C3_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN10) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN11) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOH_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_I2C3_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOH_I2C3_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOH_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_I2C3_SCL, 4))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_I2C3_SDA, 4) |       \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0))
+/*
+ * GPIOI setup:
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_OUTPUT(GPIOI_LED_R) |         \
+                                     PIN_MODE_OUTPUT(GPIOI_LED_G) |         \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_LED_R) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_LED_G) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_100M(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_100M(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_100M(GPIOI_LED_R) |         \
+                                     PIN_OSPEED_100M(GPIOI_LED_G) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_100M(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_FLOATING(GPIOI_PIN0) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN2) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN3) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN5) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN6) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN7) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN8) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN9) |       \
+                                     PIN_PUPDR_FLOATING(GPIOI_LED_R) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_LED_G) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN12) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN13) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN14) |      \
+                                     PIN_PUPDR_FLOATING(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_LOW(GPIOI_LED_R) |             \
+                                     PIN_ODR_LOW(GPIOI_LED_G) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOI_LED_R, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_LED_G, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0))
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk
new file mode 100644
index 000000000..0303442f2
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.c b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.c
new file mode 100644
index 000000000..c5237d7f7
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.c
@@ -0,0 +1,92 @@
+/*
+    Copyright (C) 2015 Fabio Utzig
+                  2016 Stéphane D'Alu / Bruno Remond
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/* RAM Banks
+ *  (Values are defined in Nordic gcc_startup_nrf51.s)
+ */
+#define NRF_POWER_RAMON_ADDRESS 0x40000524
+#define NRF_POWER_RAMONB_ADDRESS 0x40000554
+#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .pads = {
+        PAL_MODE_UNCONNECTED,         /* P0.0                  */
+        PAL_MODE_UNCONNECTED,         /* P0.1                  */
+        PAL_MODE_UNCONNECTED,         /* P0.2                  */
+        PAL_MODE_UNCONNECTED,         /* P0.3                  */
+        PAL_MODE_UNCONNECTED,         /* P0.4                  */
+        PAL_MODE_UNCONNECTED,         /* P0.5                  */
+        PAL_MODE_UNCONNECTED,         /* P0.6                  */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.7 : SCL            */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.8 : UART_RTS       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.9 : UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.10: UART_CTS       */
+        PAL_MODE_INPUT_PULLUP,        /* P0.11: UART_RX        */
+        PAL_MODE_UNCONNECTED,         /* P0.12                 */
+        PAL_MODE_UNCONNECTED,         /* P0.13                 */
+        PAL_MODE_UNCONNECTED,         /* P0.14                 */
+        PAL_MODE_UNCONNECTED,         /* P0.15                 */
+        PAL_MODE_UNCONNECTED,         /* P0.16                 */
+        PAL_MODE_INPUT_PULLUP,        /* P0.17: BTN1           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.18: BTN2           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.19: BTN3           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.20: BTN4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.21: LED1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.22: LED2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.23: LED3           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: LED4 | SPI_SEL */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.25: SPI_MOSI       */
+        PAL_MODE_UNCONNECTED,         /* P0.26: XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.27: XTAL (32MHz)   */
+        PAL_MODE_INPUT_PULLUP,        /* P0.28: SPI_MISO       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.29: SPI_SCK        */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.30: SDA            */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+  /* Make sure ALL RAM banks are powered on */
+  *(uint32_t *)NRF_POWER_RAMON_ADDRESS  |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+  *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk;
+}
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.h b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.h
new file mode 100644
index 000000000..67e1724f6
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.h
@@ -0,0 +1,145 @@
+/*
+    Copyright (C) 2015 Fabio Utzig
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/* Board identifier. */
+#define BOARD_NRF51_DK
+#define BOARD_NAME              "nRF51 DK"
+/* Board oscillators-related settings. */
+#define NRF51_XTAL_VALUE        16000000
+#define NRF51_LFCLK_SOURCE      1
+/* GPIO pins. */
+#define BTN1           17
+#define BTN2           18
+#define BTN3           19
+#define BTN4           20
+#define LED1           21
+#define LED2           22
+#define LED3           23
+#define LED4           24
+#define UART_RTS        8
+#define UART_TX         9
+#define UART_CTS       10
+#define UART_RX        11
+#define SPI_SCK        29
+#define SPI_MOSI       25
+#define SPI_MISO       28
+#define SPI_SS         24
+#define I2C_SCL         7
+#define I2C_SDA        30
+#define AIN0           26
+#define AIN1           27
+#define AIN2            1
+#define AIN3            2
+#define AIN4            3
+#define AIN5            4
+#define AIN6            5
+#define AIN7            6
+#define AREF0           0
+#define AREF1           6
+/*
+ * IO pins assignments.
+ */
+#define IOPORT1_BTN1           17U
+#define IOPORT1_BTN2           18U
+#define IOPORT1_BTN3           19U
+#define IOPORT1_BTN4           20U
+#define IOPORT1_LED1           21U
+#define IOPORT1_LED2           22U
+#define IOPORT1_LED3           23U
+#define IOPORT1_LED4           24U
+#define IOPORT1_UART_RTS        8U
+#define IOPORT1_UART_TX         9U
+#define IOPORT1_UART_CTS       10U
+#define IOPORT1_UART_RX        11U
+#define IOPORT1_SPI_SCK        29U
+#define IOPORT1_SPI_MOSI       25U
+#define IOPORT1_SPI_MISO       28U
+#define IOPORT1_SPI_SS         24U
+#define IOPORT1_I2C_SCL         7U
+#define IOPORT1_I2C_SDA        30U
+#define IOPORT1_A0              1U
+#define IOPORT1_A1              2U
+#define IOPORT1_A2              3U
+#define IOPORT1_A3              4U
+#define IOPORT1_A4              5U
+#define IOPORT1_A5              6U
+#define IOPORT1_AIN0           26U
+#define IOPORT1_AIN1           27U
+#define IOPORT1_AIN2            1U
+#define IOPORT1_AIN3            2U
+#define IOPORT1_AIN4            3U
+#define IOPORT1_AIN5            4U
+#define IOPORT1_AIN6            5U
+#define IOPORT1_AIN7            6U
+#define IOPORT1_AREF0           0U
+#define IOPORT1_AREF1           6U
+/*
+ * IO lines assignments.
+ */
+#define LINE_BTN1      PAL_LINE(IOPORT1, IOPORT1_BTN1)
+#define LINE_BTN2      PAL_LINE(IOPORT1, IOPORT1_BTN2)
+#define LINE_BTN3      PAL_LINE(IOPORT1, IOPORT1_BTN3)
+#define LINE_BTN4      PAL_LINE(IOPORT1, IOPORT1_BTN4)
+#define LINE_LED1      PAL_LINE(IOPORT1, IOPORT1_LED1)
+#define LINE_LED2      PAL_LINE(IOPORT1, IOPORT1_LED2)
+#define LINE_LED3      PAL_LINE(IOPORT1, IOPORT1_LED3)
+#define LINE_LED4      PAL_LINE(IOPORT1, IOPORT1_LED4)
+#define LINE_UART_RTS  PAL_LINE(IOPORT1, IOPORT1_UART_RTS)
+#define LINE_UART_TX   PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_CTS  PAL_LINE(IOPORT1, IOPORT1_UART_CTS)
+#define LINE_UART_RX   PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_SPI_SCK   PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_SPI_MOSI  PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO  PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SS    PAL_LINE(IOPORT1, IOPORT1_SPI_SS)
+#define LINE_I2C_SCL   PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA   PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+#define LINE_A0        PAL_LINE(IOPORT1, IOPORT1_A0)
+#define LINE_A1        PAL_LINE(IOPORT1, IOPORT1_A1)
+#define LINE_A2        PAL_LINE(IOPORT1, IOPORT1_A2)
+#define LINE_A3        PAL_LINE(IOPORT1, IOPORT1_A3)
+#define LINE_A4        PAL_LINE(IOPORT1, IOPORT1_A4)
+#define LINE_A5        PAL_LINE(IOPORT1, IOPORT1_A5)
+#define LINE_AIN0      PAL_LINE(IOPORT1, IOPORT1_AIN0)
+#define LINE_AIN1      PAL_LINE(IOPORT1, IOPORT1_AIN1)
+#define LINE_AIN2      PAL_LINE(IOPORT1, IOPORT1_AIN2)
+#define LINE_AIN3      PAL_LINE(IOPORT1, IOPORT1_AIN3)
+#define LINE_AIN4      PAL_LINE(IOPORT1, IOPORT1_AIN4)
+#define LINE_AIN5      PAL_LINE(IOPORT1, IOPORT1_AIN5)
+#define LINE_AIN6      PAL_LINE(IOPORT1, IOPORT1_AIN6)
+#define LINE_AIN7      PAL_LINE(IOPORT1, IOPORT1_AIN7)
+#define LINE_AREF0     PAL_LINE(IOPORT1, IOPORT1_AREF0)
+#define LINE_AREF1     PAL_LINE(IOPORT1, IOPORT1_AREF1)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.mk b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.mk
new file mode 100644
index 000000000..3e3e465f7
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF51-DK/board.mk
@@ -0,0 +1,15 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK
+# Flash
+JLINK_DEVICE    = nrf51422
+JLINK_PRE_FLASH = w4 4001e504 1
+JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
+JLINK_PIN_RESET = w4 40000544 1
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.c b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.c
new file mode 100644
index 000000000..cfbf24d14
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.c
@@ -0,0 +1,81 @@
+/*
+    Copyright (C) 2016 Stéphane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .pads = {
+        PAL_MODE_UNCONNECTED,         /* P0.0 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.1 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.2                  */
+        PAL_MODE_UNCONNECTED,         /* P0.3                  */
+        PAL_MODE_UNCONNECTED,         /* P0.4                  */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5 : UART_RTS       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.6 : UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.7 : UART_CTS       */
+        PAL_MODE_INPUT_PULLUP,        /* P0.8 : UART_RX        */
+        PAL_MODE_UNCONNECTED,         /* P0.9                  */
+        PAL_MODE_UNCONNECTED,         /* P0.10                 */
+        PAL_MODE_UNCONNECTED,         /* P0.11                 */
+        PAL_MODE_UNCONNECTED,         /* P0.12                 */
+        PAL_MODE_INPUT_PULLUP,        /* P0.13: BTN1           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.14: BTN2           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.15: BTN3           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.16: BTN4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.17: LED1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.18: LED2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.19: LED3           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.20: LED4           */
+        PAL_MODE_UNCONNECTED,         /* P0.21                 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.22: SPI_SS         */
+        PAL_MODE_INPUT_PULLUP,        /* P0.23: SPI_MISO       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: SPI_MOSI       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.25: SPI_SCK        */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.26: SDA            */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.27: SCL            */
+        PAL_MODE_UNCONNECTED,         /* P0.28                 */
+        PAL_MODE_UNCONNECTED,         /* P0.29                 */
+        PAL_MODE_UNCONNECTED,         /* P0.30                 */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+}
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.h b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.h
new file mode 100644
index 000000000..5c7566a93
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.h
@@ -0,0 +1,201 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/* Board identifier. */
+#define BOARD_NRF52_DK
+#define BOARD_NAME              "nRF52 DK"
+/* Board oscillators-related settings. */
+#define NRF5_XTAL_VALUE        32000000
+#define NRF5_LFCLK_SOURCE      1
+/*
+ * GPIO pins. 
+ */
+/* Defined by board */
+#define BTN1           13U
+#define BTN2           14U
+#define BTN3           15U
+#define BTN4           16U
+#define LED1           17U
+#define LED2           18U
+#define LED3           19U
+#define LED4           20U
+#define UART_RTS        5U
+#define UART_TX         6U
+#define UART_CTS        7U
+#define UART_RX         8U
+#define NFC1            9U
+#define NFC2           10U
+#define I2C_SCL        27U
+#define I2C_SDA        26U
+/* Our definitions */
+#define SPI_SCK        25U
+#define SPI_MOSI       24U
+#define SPI_MISO       23U
+#define SPI_SS         22U
+/* Analog input */
+#define AIN0            2U
+#define AIN1            3U
+#define AIN2            4U
+#define AIN3            5U
+#define AIN4           28U
+#define AIN5           29U
+#define AIN6           30U
+#define AIN7           31U
+#define AREF0         AIN0
+#define AREF1         AIN1
+/*
+ * IO pins assignments.
+ */
+/* Defined by board */
+#define IOPORT1_BTN1           13U
+#define IOPORT1_BTN2           14U
+#define IOPORT1_BTN3           15U
+#define IOPORT1_BTN4           16U
+#define IOPORT1_LED1           17U
+#define IOPORT1_LED2           18U
+#define IOPORT1_LED3           19U
+#define IOPORT1_LED4           20U
+#define IOPORT1_UART_RTS        5U
+#define IOPORT1_UART_TX         6U
+#define IOPORT1_UART_CTS        7U
+#define IOPORT1_UART_RX         8U
+#define IOPORT1_NFC1            9U
+#define IOPORT1_NFC2           10U
+#define IOPORT1_I2C_SCL        27U
+#define IOPORT1_I2C_SDA        26U
+#define IOPORT1_RESET          21U
+/* Our definitions */
+#define IOPORT1_SPI_SCK        25U
+#define IOPORT1_SPI_MOSI       24U
+#define IOPORT1_SPI_MISO       23U
+#define IOPORT1_SPI_SS         22U
+/* Analog inpupt */
+#define IOPORT1_AIN0            2U
+#define IOPORT1_AIN1            3U
+#define IOPORT1_AIN2            4U
+#define IOPORT1_AIN3            5U
+#define IOPORT1_AIN4           28U
+#define IOPORT1_AIN5           29U
+#define IOPORT1_AIN6           30U
+#define IOPORT1_AIN7           31U
+#define IOPORT1_AREF0           IOPORT1_AIN0
+#define IOPORT1_AREF1           IOPORT1_AIN1
+/* Arduino naming */
+#define IOPORT1_A0              3U
+#define IOPORT1_A1              4U
+#define IOPORT1_A2             28U
+#define IOPORT1_A3             39U
+#define IOPORT1_A4             30U
+#define IOPORT1_A5             31U
+#define IOPORT1_D0             11U
+#define IOPORT1_D1             12U
+#define IOPORT1_D2             13U
+#define IOPORT1_D3             14U
+#define IOPORT1_D4             15U
+#define IOPORT1_D5             16U
+#define IOPORT1_D6             17U
+#define IOPORT1_D7             18U
+#define IOPORT1_D8             19U
+#define IOPORT1_D9             20U
+#define IOPORT1_D10            22U
+#define IOPORT1_D11            23U
+#define IOPORT1_D12            24U
+#define IOPORT1_D13            25U
+/*
+ * IO lines assignments.
+ */
+/* Board defined */
+#define LINE_BTN1      PAL_LINE(IOPORT1, IOPORT1_BTN1)
+#define LINE_BTN2      PAL_LINE(IOPORT1, IOPORT1_BTN2)
+#define LINE_BTN3      PAL_LINE(IOPORT1, IOPORT1_BTN3)
+#define LINE_BTN4      PAL_LINE(IOPORT1, IOPORT1_BTN4)
+#define LINE_LED1      PAL_LINE(IOPORT1, IOPORT1_LED1)
+#define LINE_LED2      PAL_LINE(IOPORT1, IOPORT1_LED2)
+#define LINE_LED3      PAL_LINE(IOPORT1, IOPORT1_LED3)
+#define LINE_LED4      PAL_LINE(IOPORT1, IOPORT1_LED4)
+#define LINE_UART_RTS  PAL_LINE(IOPORT1, IOPORT1_UART_RTS)
+#define LINE_UART_TX   PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_CTS  PAL_LINE(IOPORT1, IOPORT1_UART_CTS)
+#define LINE_UART_RX   PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_NFC1      PAL_LINE(IOPORT1, IOPORT1_NFC1)
+#define LINE_NFC2      PAL_LINE(IOPORT1, IOPORT1_NFC2)
+#define LINE_I2C_SCL   PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA   PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+/* Our definitions */
+#define LINE_SPI_SCK   PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_SPI_MOSI  PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO  PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SS    PAL_LINE(IOPORT1, IOPORT1_SPI_SS)
+/* Analog line */
+#define LINE_AIN0      PAL_LINE(IOPORT1, IOPORT1_AIN0)
+#define LINE_AIN1      PAL_LINE(IOPORT1, IOPORT1_AIN1)
+#define LINE_AIN2      PAL_LINE(IOPORT1, IOPORT1_AIN2)
+#define LINE_AIN3      PAL_LINE(IOPORT1, IOPORT1_AIN3)
+#define LINE_AIN4      PAL_LINE(IOPORT1, IOPORT1_AIN4)
+#define LINE_AIN5      PAL_LINE(IOPORT1, IOPORT1_AIN5)
+#define LINE_AIN6      PAL_LINE(IOPORT1, IOPORT1_AIN6)
+#define LINE_AIN7      PAL_LINE(IOPORT1, IOPORT1_AIN7)
+#define LINE_AREF0     PAL_LINE(IOPORT1, IOPORT1_AREF0)
+#define LINE_AREF1     PAL_LINE(IOPORT1, IOPORT1_AREF1)
+/* Arduino naming */
+#define LINE_A0        PAL_LINE(IOPORT1, IOPORT1_A0)
+#define LINE_A1        PAL_LINE(IOPORT1, IOPORT1_A1)
+#define LINE_A2        PAL_LINE(IOPORT1, IOPORT1_A2)
+#define LINE_A3        PAL_LINE(IOPORT1, IOPORT1_A3)
+#define LINE_A4        PAL_LINE(IOPORT1, IOPORT1_A4)
+#define LINE_A5        PAL_LINE(IOPORT1, IOPORT1_A5)
+#define LINE_D0        PAL_LINE(IOPORT1, IOPORT1_D0)
+#define LINE_D1        PAL_LINE(IOPORT1, IOPORT1_D1)
+#define LINE_D2        PAL_LINE(IOPORT1, IOPORT1_D2)
+#define LINE_D3        PAL_LINE(IOPORT1, IOPORT1_D3)
+#define LINE_D4        PAL_LINE(IOPORT1, IOPORT1_D4)
+#define LINE_D5        PAL_LINE(IOPORT1, IOPORT1_D5)
+#define LINE_D6        PAL_LINE(IOPORT1, IOPORT1_D6)
+#define LINE_D7        PAL_LINE(IOPORT1, IOPORT1_D7)
+#define LINE_D8        PAL_LINE(IOPORT1, IOPORT1_D8)
+#define LINE_D9        PAL_LINE(IOPORT1, IOPORT1_D9)
+#define LINE_D10       PAL_LINE(IOPORT1, IOPORT1_D10)
+#define LINE_D11       PAL_LINE(IOPORT1, IOPORT1_D11)
+#define LINE_D12       PAL_LINE(IOPORT1, IOPORT1_D12)
+#define LINE_D13       PAL_LINE(IOPORT1, IOPORT1_D13)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.mk b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.mk
new file mode 100644
index 000000000..b296d27ba
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-DK/board.mk
@@ -0,0 +1,15 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK
+# Flash
+JLINK_DEVICE    = nrf52
+JLINK_PRE_FLASH = w4 4001e504 1
+#JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100
+JLINK_PIN_RESET = w4 40000544 1
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.c b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.c
new file mode 100644
index 000000000..adf002d8f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.c
@@ -0,0 +1,81 @@
+/*
+    Copyright (C) 2016 Stéphane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .pads = {
+        PAL_MODE_UNCONNECTED,         /* P0.0 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.1 : XTAL (32MHz)   */
+        PAL_MODE_UNCONNECTED,         /* P0.2                  */
+        PAL_MODE_UNCONNECTED,         /* P0.3                  */
+        PAL_MODE_UNCONNECTED,         /* P0.4                  */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5 : UART_RTS       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.6 : UART_TX        */
+        PAL_MODE_INPUT_PULLUP,        /* P0.7 : UART_CTS       */
+        PAL_MODE_INPUT_PULLUP,        /* P0.8 : UART_RX        */
+        PAL_MODE_UNCONNECTED,         /* P0.9                  */
+        PAL_MODE_UNCONNECTED,         /* P0.10                 */
+        PAL_MODE_UNCONNECTED,         /* P0.11                 */
+        PAL_MODE_UNCONNECTED,         /* P0.12                 */
+        PAL_MODE_INPUT,               /* P0.13: BTN1           */
+        PAL_MODE_INPUT,               /* P0.14: BTN2           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.15: BTN3           */
+        PAL_MODE_INPUT_PULLUP,        /* P0.16: BTN4           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.17: LED1           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.18: LED2           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.19: LED3           */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.20: LED4           */
+        PAL_MODE_UNCONNECTED,         /* P0.21                 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.22: SPI_SS         */
+        PAL_MODE_INPUT_PULLUP,        /* P0.23: SPI_MISO       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: SPI_MOSI       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.25: SPI_SCK        */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.26: SDA            */
+        PAL_MODE_OUTPUT_OPENDRAIN,    /* P0.27: SCL            */
+        PAL_MODE_UNCONNECTED,         /* P0.28                 */
+        PAL_MODE_UNCONNECTED,         /* P0.29                 */
+        PAL_MODE_UNCONNECTED,         /* P0.30                 */
+        PAL_MODE_UNCONNECTED,         /* P0.31                 */
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+}
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.h b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.h
new file mode 100644
index 000000000..c78909f27
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.h
@@ -0,0 +1,164 @@
+/*
+    Copyright (C) 2016 Stephane D'Alu
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/* Board identifier. */
+#define BOARD_NRF52_EBYTE_E73
+#define BOARD_NAME             "nRF52 EBYTE E73-2G4M04S"
+/* Board oscillators-related settings. */
+#define NRF5_XTAL_VALUE        32000000
+#define NRF5_HFCLK_SOURCE      NRF5_HFCLK_HFXO
+#define NRF5_LFCLK_SOURCE      NRF5_LFCLK_XTAL
+#define NRF5_HFCLK_HFINT       0
+#define NRF5_HFCLK_HFXO        1
+#define NRF5_LFCLK_RC          0
+#define NRF5_LFCLK_XTAL        1
+#define NRF5_LFCLK_SYNTH       2
+/*
+ * GPIO pins. 
+ */
+/* Defined by board */
+#define BTN1           13U
+#define BTN2           14U
+#define BTN3           15U
+#define BTN4           16U
+#define LED1           17U
+#define LED2           18U
+#define LED3           19U
+#define LED4           20U
+#define UART_RTS        5U
+#define UART_TX         6U
+#define UART_CTS        7U
+#define UART_RX         8U
+#define NFC1            9U
+#define NFC2           10U
+#define I2C_SCL        27U
+#define I2C_SDA        26U
+/* Our definitions */
+#define SPI_SCK        25U
+#define SPI_MOSI       24U
+#define SPI_MISO       23U
+#define SPI_SS         22U
+/* Analog input */
+#define AIN0            2U
+#define AIN1            3U
+#define AIN2            4U
+#define AIN3            5U
+#define AIN4           28U
+#define AIN5           29U
+#define AIN6           30U
+#define AIN7           31U
+#define AREF0         AIN0
+#define AREF1         AIN1
+/*
+ * IO pins assignments.
+ */
+/* Defined by board */
+#define IOPORT1_BTN1           13U
+#define IOPORT1_BTN2           14U
+#define IOPORT1_BTN3           15U
+#define IOPORT1_BTN4           16U
+#define IOPORT1_LED1           17U
+#define IOPORT1_LED2           18U
+#define IOPORT1_LED3           19U
+#define IOPORT1_LED4           20U
+#define IOPORT1_UART_RTS        5U
+#define IOPORT1_UART_TX         6U
+#define IOPORT1_UART_CTS        7U
+#define IOPORT1_UART_RX         8U
+#define IOPORT1_NFC1            9U
+#define IOPORT1_NFC2           10U
+#define IOPORT1_I2C_SCL        27U
+#define IOPORT1_I2C_SDA        26U
+#define IOPORT1_RESET          21U
+/* Our definitions */
+#define IOPORT1_SPI_SCK        25U
+#define IOPORT1_SPI_MOSI       24U
+#define IOPORT1_SPI_MISO       23U
+#define IOPORT1_SPI_SS         22U
+/* Analog inpupt */
+#define IOPORT1_AIN0            2U
+#define IOPORT1_AIN1            3U
+#define IOPORT1_AIN2            4U
+#define IOPORT1_AIN3            5U
+#define IOPORT1_AIN4           28U
+#define IOPORT1_AIN5           29U
+#define IOPORT1_AIN6           30U
+#define IOPORT1_AIN7           31U
+#define IOPORT1_AREF0           IOPORT1_AIN0
+#define IOPORT1_AREF1           IOPORT1_AIN1
+/*
+ * IO lines assignments.
+ */
+/* Board defined */
+#define LINE_BTN1      PAL_LINE(IOPORT1, IOPORT1_BTN1)
+#define LINE_BTN2      PAL_LINE(IOPORT1, IOPORT1_BTN2)
+#define LINE_BTN3      PAL_LINE(IOPORT1, IOPORT1_BTN3)
+#define LINE_BTN4      PAL_LINE(IOPORT1, IOPORT1_BTN4)
+#define LINE_LED1      PAL_LINE(IOPORT1, IOPORT1_LED1)
+#define LINE_LED2      PAL_LINE(IOPORT1, IOPORT1_LED2)
+#define LINE_LED3      PAL_LINE(IOPORT1, IOPORT1_LED3)
+#define LINE_LED4      PAL_LINE(IOPORT1, IOPORT1_LED4)
+#define LINE_UART_RTS  PAL_LINE(IOPORT1, IOPORT1_UART_RTS)
+#define LINE_UART_TX   PAL_LINE(IOPORT1, IOPORT1_UART_TX)
+#define LINE_UART_CTS  PAL_LINE(IOPORT1, IOPORT1_UART_CTS)
+#define LINE_UART_RX   PAL_LINE(IOPORT1, IOPORT1_UART_RX)
+#define LINE_NFC1      PAL_LINE(IOPORT1, IOPORT1_NFC1)
+#define LINE_NFC2      PAL_LINE(IOPORT1, IOPORT1_NFC2)
+#define LINE_I2C_SCL   PAL_LINE(IOPORT1, IOPORT1_I2C_SCL)
+#define LINE_I2C_SDA   PAL_LINE(IOPORT1, IOPORT1_I2C_SDA)
+/* Our definitions */
+#define LINE_SPI_SCK   PAL_LINE(IOPORT1, IOPORT1_SPI_SCK)
+#define LINE_SPI_MOSI  PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI)
+#define LINE_SPI_MISO  PAL_LINE(IOPORT1, IOPORT1_SPI_MISO)
+#define LINE_SPI_SS    PAL_LINE(IOPORT1, IOPORT1_SPI_SS)
+/* Analog line */
+#define LINE_AIN0      PAL_LINE(IOPORT1, IOPORT1_AIN0)
+#define LINE_AIN1      PAL_LINE(IOPORT1, IOPORT1_AIN1)
+#define LINE_AIN2      PAL_LINE(IOPORT1, IOPORT1_AIN2)
+#define LINE_AIN3      PAL_LINE(IOPORT1, IOPORT1_AIN3)
+#define LINE_AIN4      PAL_LINE(IOPORT1, IOPORT1_AIN4)
+#define LINE_AIN5      PAL_LINE(IOPORT1, IOPORT1_AIN5)
+#define LINE_AIN6      PAL_LINE(IOPORT1, IOPORT1_AIN6)
+#define LINE_AIN7      PAL_LINE(IOPORT1, IOPORT1_AIN7)
+#define LINE_AREF0     PAL_LINE(IOPORT1, IOPORT1_AREF0)
+#define LINE_AREF1     PAL_LINE(IOPORT1, IOPORT1_AREF1)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.mk b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.mk
new file mode 100644
index 000000000..8876668ec
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NRF52-E73-2G4M04S/board.mk
@@ -0,0 +1,8 @@
+# List of all the board related files.
+BOARDSRC =  ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-E73-2G4M04S/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-E73-2G4M04S
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.c b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.c
new file mode 100644
index 000000000..f5aec9885
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.c
@@ -0,0 +1,40 @@
+/*
+    ChibiOS - Copyright (C) 2020 Alex Lewontin
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL
+const PALConfig pal_default_config;
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ */
+void boardInit(void)
+{
+#if HAL_USE_PAL
+  OnboardLED_Init();
+#endif
+}
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.h b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.h
new file mode 100644
index 000000000..9dd49383c
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.h
@@ -0,0 +1,61 @@
+/*
+    ChibiOS - Copyright (C) 2020 Alex Lewontin
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef BOARD_H
+#define BOARD_H
+/*
+ * Setup for a generic board.
+ */
+/*
+ * Board identifier.
+ */
+#define NUC123SD4AN0
+#define BOARD_NAME "NUTINY SDK NUC123 V2.0"
+/*
+ * Board specific settings.
+ */
+/*
+ * External XTAL speed.
+ */
+#define NUC123_HSECLK 12000000UL
+/*
+ * LED macros.
+ */
+#define ONBOARD_LED_LINE PAL_LINE(GPIOB, 4)
+#define OnboardLED_Init()                                                   \
+  palSetGroupMode(GPIOB, 1, 4, PAL_MODE_OUTPUT_PUSHPULL)
+#define OnboardLED_On()     palClearLine(ONBOARD_LED_LINE)
+#define OnboardLED_Off()    palSetLine(ONBOARD_LED_LINE)
+#define OnboardLED_Toggle() palToggleLine(ONBOARD_LED_LINE)
+#define ONBOARD_SERIAL_DRIVER SD0
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk
new file mode 100644
index 000000000..d6c9b105c
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.mk
@@ -0,0 +1,8 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS_CONTRIB)/os/hal/boards/NUTINY-SDK-NUC123-V2.0
+ALLCSRC += $(BOARDSRC)
+ALLINC += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.c b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.c
new file mode 100644
index 000000000..85e4486b3
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.c
@@ -0,0 +1,80 @@
+/*
+    Copyright (C) 2016 flabbergast
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+  .pads = {
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.0:  PIN11 (AREF0) */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.1:  PIN9  (AIN2)  */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.2:  PIN10 (AIN3)  */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.3:  LED_BLUE      */
+        PAL_MODE_UNCONNECTED,         /* P0.4 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.5:  LED_GREEN     */
+        PAL_MODE_UNCONNECTED,         /* P0.6 */
+        PAL_MODE_UNCONNECTED,         /* P0.7 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.8:  LED_RED       */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.9:  PIN7          */
+        PAL_MODE_UNCONNECTED,         /* P0.10 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.11: PIN6          */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.12: PIN5          */
+        PAL_MODE_UNCONNECTED,         /* P0.13 */
+        PAL_MODE_UNCONNECTED,         /* P0.14 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.15: PIN4          */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.16: PIN3          */
+        PAL_MODE_UNCONNECTED,         /* P0.17 */
+        PAL_MODE_INPUT_PULLUP,        /* P0.18: PIN2 (RX)     */
+        PAL_MODE_UNCONNECTED,         /* P0.19 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.20: PIN1 (TX)     */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.21: PIN15         */
+        PAL_MODE_UNCONNECTED,         /* P0.22 */
+        PAL_MODE_UNCONNECTED,         /* P0.23 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.24: PIN14         */
+        PAL_MODE_UNCONNECTED,         /* P0.25 */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.26: PIN13 (LFXTL) (AIN0) */
+        PAL_MODE_OUTPUT_PUSHPULL,     /* P0.27: PIN12 (LFXTL) (AIN1) */
+        PAL_MODE_UNCONNECTED,         /* P0.28 */
+        PAL_MODE_UNCONNECTED,         /* P0.29 */
+        PAL_MODE_UNCONNECTED,         /* P0.30 */
+        PAL_MODE_UNCONNECTED,         /* P0.31 */
+  },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization is performed just after reset before BSS and
+ *          DATA segments initialization.
+ */
+void __early_init(void)
+{
+}
+/**
+ * @brief   Late initialization code.
+ * @note    This initialization is performed after BSS and DATA segments
+ *          initialization and before invoking the main() function.
+ */
+void boardInit(void)
+{
+}
diff --git a/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.h b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.h
new file mode 100644
index 000000000..e3bbb0baa
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.h
@@ -0,0 +1,64 @@
+/*
+    Copyright (C) 2016 flabbergast
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/* Board identifier. */
+#define BOARD_OSHCHIP_V10
+#define BOARD_NAME              "OSHChip_V1.0"
+/* Board oscillators-related settings. */
+#define NRF51_XTAL_VALUE        16000000
+/* Non-header GPIO pins. */
+#define LED_RED        8
+#define LED_GREEN      5
+#define LED_BLUE       3
+/* Common peripheral GPIO pins. */
+#define UART_TX        20
+#define UART_RX        18
+/* GPIO on DIP pins. */
+#define OSHCHIP_PIN1   20
+#define OSHCHIP_PIN2   18
+#define OSHCHIP_PIN3   16
+#define OSHCHIP_PIN4   15
+#define OSHCHIP_PIN5   12
+#define OSHCHIP_PIN6   11
+#define OSHCHIP_PIN7   9
+/* Pin 8 is GND */
+#define OSHCHIP_PIN9   1
+#define OSHCHIP_PIN10  2
+#define OSHCHIP_PIN11  0
+#define OSHCHIP_PIN12  27
+#define OSHCHIP_PIN13  26
+#define OSHCHIP_PIN14  24
+#define OSHCHIP_PIN15  21
+/* Pin 16 is VCC */
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.mk b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.mk
new file mode 100644
index 000000000..de1c59d4d
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/OSHCHIP_V1.0/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/OSHCHIP_V1.0
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.c
new file mode 100644
index 000000000..4b47d15ec
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.c
@@ -0,0 +1,183 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA4  - PIN33
+             * PTA5  - PIN24
+             * PTA12 - PIN3
+             * PTA13 - PIN4
+             *
+             * PTA18/19 crystal
+             * PTA0/3 SWD
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,      PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0  - PIN16
+             * PTB1  - PIN17
+             * PTB2  - PIN19
+             * PTB3  - PIN18
+             * PTB16 - PIN0 - UART0_TX
+             * PTB17 - PIN1 - UART0_RX
+             * PTB18 - PIN32
+             * PTB19 - PIN25
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             *
+             * PTC0  - PIN15
+             * PTC1  - PIN22
+             * PTC2  - PIN23
+             * PTC3  - PIN9
+             * PTC4  - PIN10
+             * PTC5  - PIN13
+             * PTC6  - PIN11
+             * PTC7  - PIN12
+             * PTC8  - PIN28
+             * PTC9  - PIN27
+             * PTC10 - PIN29
+             * PTC11 - PIN30
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0  - PIN2
+             * PTD1  - PIN14
+             * PTD2  - PIN7
+             * PTD3  - PIN8
+             * PTD4  - PIN6
+             * PTD5  - PIN20
+             * PTD6  - PIN21
+             * PTD7  - PIN5
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE0  - PIN31
+             * PTE1  - PIN26
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  k20x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.h
new file mode 100644
index 000000000..16e066620
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.h
@@ -0,0 +1,296 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy 3.0 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3
+#define BOARD_NAME                  "PJRC Teensy 3.0"
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+/*
+ * MCU type
+ */
+#define K20x5
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define PORTA_PIN1                  1
+#define PORTA_PIN2                  2
+#define PORTA_PIN3                  3
+#define TEENSY_PIN33                4
+#define TEENSY_PIN24                5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define TEENSY_PIN3                 12
+#define TEENSY_PIN4                 13
+#define PORTA_PIN14                 14
+#define PORTA_PIN15                 15
+#define PORTA_PIN16                 16
+#define PORTA_PIN17                 17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define PORTA_PIN26                 26
+#define PORTA_PIN27                 27
+#define PORTA_PIN28                 28
+#define PORTA_PIN29                 29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+#define TEENSY_PIN3_IOPORT  IOPORT1
+#define TEENSY_PIN4_IOPORT  IOPORT1
+#define TEENSY_PIN24_IOPORT IOPORT1
+#define TEENSY_PIN33_IOPORT IOPORT1
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define PORTB_PIN4                  4
+#define PORTB_PIN5                  5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define PORTB_PIN10                 10
+#define PORTB_PIN11                 11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define TEENSY_PIN32                18
+#define TEENSY_PIN25                19
+#define PORTB_PIN20                 20
+#define PORTB_PIN21                 21
+#define PORTB_PIN22                 22
+#define PORTB_PIN23                 23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+#define TEENSY_PIN0_IOPORT  IOPORT2
+#define TEENSY_PIN1_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN25_IOPORT IOPORT2
+#define TEENSY_PIN32_IOPORT IOPORT2
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define TEENSY_PIN28                8
+#define TEENSY_PIN27                9
+#define TEENSY_PIN29                10
+#define TEENSY_PIN30                11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+#define TEENSY_PIN9_IOPORT  IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN27_IOPORT IOPORT3
+#define TEENSY_PIN28_IOPORT IOPORT3
+#define TEENSY_PIN29_IOPORT IOPORT3
+#define TEENSY_PIN30_IOPORT IOPORT3
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define PORTD_PIN8                  8
+#define PORTD_PIN9                  9
+#define PORTD_PIN10                 10
+#define PORTD_PIN11                 11
+#define PORTD_PIN12                 12
+#define PORTD_PIN13                 13
+#define PORTD_PIN14                 14
+#define PORTD_PIN15                 15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+#define TEENSY_PIN2_IOPORT  IOPORT4
+#define TEENSY_PIN5_IOPORT  IOPORT4
+#define TEENSY_PIN6_IOPORT  IOPORT4
+#define TEENSY_PIN7_IOPORT  IOPORT4
+#define TEENSY_PIN8_IOPORT  IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+#define TEENSY_PIN31                0
+#define TEENSY_PIN26                1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define PORTE_PIN10                 10
+#define PORTE_PIN11                 11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define PORTE_PIN20                 20
+#define PORTE_PIN21                 21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define PORTE_PIN24                 24
+#define PORTE_PIN25                 25
+#define PORTE_PIN26                 26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define PORTE_PIN30                 30
+#define PORTE_PIN31                 31
+#define TEENSY_PIN26_IOPORT IOPORT5
+#define TEENSY_PIN31_IOPORT IOPORT5
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.mk
new file mode 100644
index 000000000..bd284bf0e
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.c
new file mode 100644
index 000000000..6f5eb2a65
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.c
@@ -0,0 +1,183 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA4  - PIN33
+             * PTA5  - PIN24
+             * PTA12 - PIN3
+             * PTA13 - PIN4
+             *
+             * PTA18/19 crystal
+             * PTA0/3 SWD
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,      PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0  - PIN16
+             * PTB1  - PIN17
+             * PTB2  - PIN19
+             * PTB3  - PIN18
+             * PTB16 - PIN0 - UART0_TX
+             * PTB17 - PIN1 - UART0_RX
+             * PTB18 - PIN32
+             * PTB19 - PIN25
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             *
+             * PTC0  - PIN15
+             * PTC1  - PIN22
+             * PTC2  - PIN23
+             * PTC3  - PIN9
+             * PTC4  - PIN10
+             * PTC5  - PIN13
+             * PTC6  - PIN11
+             * PTC7  - PIN12
+             * PTC8  - PIN28
+             * PTC9  - PIN27
+             * PTC10 - PIN29
+             * PTC11 - PIN30
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0  - PIN2
+             * PTD1  - PIN14
+             * PTD2  - PIN7
+             * PTD3  - PIN8
+             * PTD4  - PIN6
+             * PTD5  - PIN20
+             * PTD6  - PIN21
+             * PTD7  - PIN5
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE0  - PIN31
+             * PTE1  - PIN26
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  k20x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.h
new file mode 100644
index 000000000..b40e8ae4b
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.h
@@ -0,0 +1,296 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy 3.1 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3_1
+#define BOARD_NAME                  "PJRC Teensy 3.1"
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+/*
+ * MCU type
+ */
+#define K20x7
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define PORTA_PIN1                  1
+#define PORTA_PIN2                  2
+#define PORTA_PIN3                  3
+#define TEENSY_PIN33                4
+#define TEENSY_PIN24                5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define TEENSY_PIN3                 12
+#define TEENSY_PIN4                 13
+#define PORTA_PIN14                 14
+#define PORTA_PIN15                 15
+#define PORTA_PIN16                 16
+#define PORTA_PIN17                 17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define PORTA_PIN26                 26
+#define PORTA_PIN27                 27
+#define PORTA_PIN28                 28
+#define PORTA_PIN29                 29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+#define TEENSY_PIN3_IOPORT  IOPORT1
+#define TEENSY_PIN4_IOPORT  IOPORT1
+#define TEENSY_PIN24_IOPORT IOPORT1
+#define TEENSY_PIN33_IOPORT IOPORT1
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define PORTB_PIN4                  4
+#define PORTB_PIN5                  5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define PORTB_PIN10                 10
+#define PORTB_PIN11                 11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define TEENSY_PIN32                18
+#define TEENSY_PIN25                19
+#define PORTB_PIN20                 20
+#define PORTB_PIN21                 21
+#define PORTB_PIN22                 22
+#define PORTB_PIN23                 23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+#define TEENSY_PIN0_IOPORT  IOPORT2
+#define TEENSY_PIN1_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN25_IOPORT IOPORT2
+#define TEENSY_PIN32_IOPORT IOPORT2
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define TEENSY_PIN28                8
+#define TEENSY_PIN27                9
+#define TEENSY_PIN29                10
+#define TEENSY_PIN30                11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+#define TEENSY_PIN9_IOPORT  IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN27_IOPORT IOPORT3
+#define TEENSY_PIN28_IOPORT IOPORT3
+#define TEENSY_PIN29_IOPORT IOPORT3
+#define TEENSY_PIN30_IOPORT IOPORT3
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define PORTD_PIN8                  8
+#define PORTD_PIN9                  9
+#define PORTD_PIN10                 10
+#define PORTD_PIN11                 11
+#define PORTD_PIN12                 12
+#define PORTD_PIN13                 13
+#define PORTD_PIN14                 14
+#define PORTD_PIN15                 15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+#define TEENSY_PIN2_IOPORT  IOPORT4
+#define TEENSY_PIN5_IOPORT  IOPORT4
+#define TEENSY_PIN6_IOPORT  IOPORT4
+#define TEENSY_PIN7_IOPORT  IOPORT4
+#define TEENSY_PIN8_IOPORT  IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+#define TEENSY_PIN31                0
+#define TEENSY_PIN26                1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define PORTE_PIN10                 10
+#define PORTE_PIN11                 11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define PORTE_PIN20                 20
+#define PORTE_PIN21                 21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define PORTE_PIN24                 24
+#define PORTE_PIN25                 25
+#define PORTE_PIN26                 26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define PORTE_PIN30                 30
+#define PORTE_PIN31                 31
+#define TEENSY_PIN26_IOPORT IOPORT5
+#define TEENSY_PIN31_IOPORT IOPORT5
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.mk
new file mode 100644
index 000000000..985ccbbbc
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_1/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_1
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.c
new file mode 100644
index 000000000..b081f1404
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.c
@@ -0,0 +1,218 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+              Copyright (C) 2017 Wim Lewis
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#define SOME_GPIO PAL_MODE_INPUT_PULLUP
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA0 -PTA3  -- bootloading coprocessor
+             * PTA5        -- PIN25
+             * PTA12-PTA13 -- PIN3-PIN4
+             * PTA14-PTA16 -- PIN26-PIN28
+             * PTA17       -- PIN39 / A20
+             * PTA26       -- PIN42
+             * PTA28       -- PIN40
+             * PTA29       -- PIN41
+             *
+             * PTA18/19 crystal
+             */
+            .port = IOPORT1,
+            .pads = {
+                /* PTA0-PTA3 -- bootloading coprocessor */
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_7,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN25 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN3 */
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN4 */
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN26 */
+                PAL_MODE_UNCONNECTED,           /* PIN27 */
+                PAL_MODE_UNCONNECTED,           /* PIN28 */
+                PAL_MODE_UNCONNECTED,           /* PIN39 */
+                PAL_MODE_INPUT_ANALOG,          /* XTAL0 */
+                PAL_MODE_INPUT_ANALOG,          /* XTAL0 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN42 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN40 */
+                PAL_MODE_UNCONNECTED,           /* PIN41 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0  - PIN16
+             * PTB1  - PIN17
+             * PTB2  - PIN19
+             * PTB3  - PIN18
+             * PTB10 - PIN31
+             * PTB11 - PIN32
+             * PTB16 - PIN0 - UART0_TX
+             * PTB17 - PIN1 - UART0_RX
+             * PTB18 - PIN32
+             * PTB19 - PIN25
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,
+                SOME_GPIO,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             *
+             * PTC0  - PIN15
+             * PTC1  - PIN22
+             * PTC2  - PIN23
+             * PTC3  - PIN9
+             * PTC4  - PIN10
+             * PTC5  - PIN13
+             * PTC6  - PIN11
+             * PTC7  - PIN12
+             * PTC8  - PIN35
+             * PTC9  - PIN36
+             * PTC10 - PIN37
+             * PTC11 - PIN38
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0  - PIN2
+             * PTD1  - PIN14
+             * PTD2  - PIN7
+             * PTD3  - PIN8
+             * PTD4  - PIN6
+             * PTD5  - PIN20
+             * PTD6  - PIN21
+             * PTD7  - PIN5
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       SOME_GPIO,       SOME_GPIO,
+                SOME_GPIO,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE0  - PTE5   -- SDHC slot
+             * PTE6           -- USB OTG power switch (Teensy3.6 only)
+             * PTE10 - PIN56
+             * PTE11 - PIN57
+             * PTE24 - PIN33
+             * PTE25 - PIN34
+             * PTE26 - PIN24
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  k60x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.h
new file mode 100644
index 000000000..7c10831bb
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.h
@@ -0,0 +1,243 @@
+/*
+    ChibiOS - Copyright (C) 2017 Wim Lewis
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy 3.5 board.
+ */
+/*
+ * Board identifier
+ */
+#define BOARD_PJRC_TEENSY_3_5
+#define BOARD_NAME                  "PJRC Teensy 3.5"
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+/*
+ * MCU type
+ */
+#define K64FX512
+/*
+ * IO pin assignments
+ */
+#define TEENSY_PIN25            5
+#define TEENSY_PIN3             12
+#define TEENSY_PIN4             13
+#define TEENSY_PIN26            14
+#define TEENSY_PIN27            15
+#define TEENSY_PIN28            16
+#define TEENSY_PIN39            17
+#define TEENSY_PIN42            26
+#define TEENSY_PIN40            28
+#define TEENSY_PIN41            29
+#define TEENSY_PIN25_IOPORT     IOPORT1
+#define TEENSY_PIN3_IOPORT      IOPORT1
+#define TEENSY_PIN4_IOPORT      IOPORT1
+#define TEENSY_PIN26_IOPORT     IOPORT1
+#define TEENSY_PIN27_IOPORT     IOPORT1
+#define TEENSY_PIN28_IOPORT     IOPORT1
+#define TEENSY_PIN39_IOPORT     IOPORT1
+#define TEENSY_PIN42_IOPORT     IOPORT1
+#define TEENSY_PIN40_IOPORT     IOPORT1
+#define TEENSY_PIN41_IOPORT     IOPORT1
+#define TEENSY_PIN16            0
+#define TEENSY_PIN17            1
+#define TEENSY_PIN19            2
+#define TEENSY_PIN18            3
+#define TEENSY_PIN49            4
+#define TEENSY_PIN50            5
+#define TEENSY_PIN31            10
+#define TEENSY_PIN32            11
+#define TEENSY_PIN0             16
+#define TEENSY_PIN1             17
+#define TEENSY_PIN29            18
+#define TEENSY_PIN30            19
+#define TEENSY_PIN43            20
+#define TEENSY_PIN46            21
+#define TEENSY_PIN44            22
+#define TEENSY_PIN45            23
+#define TEENSY_PIN16_IOPORT     IOPORT2
+#define TEENSY_PIN17_IOPORT     IOPORT2
+#define TEENSY_PIN19_IOPORT     IOPORT2
+#define TEENSY_PIN18_IOPORT     IOPORT2
+#define TEENSY_PIN49_IOPORT     IOPORT2
+#define TEENSY_PIN50_IOPORT     IOPORT2
+#define TEENSY_PIN31_IOPORT     IOPORT2
+#define TEENSY_PIN32_IOPORT     IOPORT2
+#define TEENSY_PIN0_IOPORT      IOPORT2
+#define TEENSY_PIN1_IOPORT      IOPORT2
+#define TEENSY_PIN29_IOPORT     IOPORT2
+#define TEENSY_PIN30_IOPORT     IOPORT2
+#define TEENSY_PIN43_IOPORT     IOPORT2
+#define TEENSY_PIN46_IOPORT     IOPORT2
+#define TEENSY_PIN44_IOPORT     IOPORT2
+#define TEENSY_PIN45_IOPORT     IOPORT2
+#define TEENSY_PIN15            0
+#define TEENSY_PIN22            1
+#define TEENSY_PIN23            2
+#define TEENSY_PIN9             3
+#define TEENSY_PIN10            4
+#define TEENSY_PIN13            5
+#define TEENSY_PIN11            6
+#define TEENSY_PIN12            7
+#define TEENSY_PIN35            8
+#define TEENSY_PIN36            9
+#define TEENSY_PIN37            10
+#define TEENSY_PIN38            11
+#define TEENSY_PIN15_IOPORT     IOPORT3
+#define TEENSY_PIN22_IOPORT     IOPORT3
+#define TEENSY_PIN23_IOPORT     IOPORT3
+#define TEENSY_PIN9_IOPORT      IOPORT3
+#define TEENSY_PIN10_IOPORT     IOPORT3
+#define TEENSY_PIN13_IOPORT     IOPORT3
+#define TEENSY_PIN11_IOPORT     IOPORT3
+#define TEENSY_PIN12_IOPORT     IOPORT3
+#define TEENSY_PIN35_IOPORT     IOPORT3
+#define TEENSY_PIN36_IOPORT     IOPORT3
+#define TEENSY_PIN37_IOPORT     IOPORT3
+#define TEENSY_PIN38_IOPORT     IOPORT3
+#define TEENSY_PIN2             0
+#define TEENSY_PIN14            1
+#define TEENSY_PIN7             2
+#define TEENSY_PIN8             3
+#define TEENSY_PIN6             4
+#define TEENSY_PIN20            5
+#define TEENSY_PIN21            6
+#define TEENSY_PIN5             7
+#define TEENSY_PIN47            8
+#define TEENSY_PIN48            9
+#define TEENSY_PIN55            11
+#define TEENSY_PIN53            12
+#define TEENSY_PIN52            13
+#define TEENSY_PIN51            14
+#define TEENSY_PIN54            15
+#define TEENSY_PIN2_IOPORT      IOPORT4
+#define TEENSY_PIN14_IOPORT     IOPORT4
+#define TEENSY_PIN7_IOPORT      IOPORT4
+#define TEENSY_PIN8_IOPORT      IOPORT4
+#define TEENSY_PIN6_IOPORT      IOPORT4
+#define TEENSY_PIN20_IOPORT     IOPORT4
+#define TEENSY_PIN21_IOPORT     IOPORT4
+#define TEENSY_PIN5_IOPORT      IOPORT4
+#define TEENSY_PIN47_IOPORT     IOPORT4
+#define TEENSY_PIN48_IOPORT     IOPORT4
+#define TEENSY_PIN55_IOPORT     IOPORT4
+#define TEENSY_PIN53_IOPORT     IOPORT4
+#define TEENSY_PIN52_IOPORT     IOPORT4
+#define TEENSY_PIN51_IOPORT     IOPORT4
+#define TEENSY_PIN54_IOPORT     IOPORT4
+#define TEENSY_PIN56            10
+#define TEENSY_PIN57            11
+#define TEENSY_PIN33            24
+#define TEENSY_PIN34            25
+#define TEENSY_PIN24            26
+#define TEENSY_PIN56_IOPORT     IOPORT5
+#define TEENSY_PIN57_IOPORT     IOPORT5
+#define TEENSY_PIN33_IOPORT     IOPORT5
+#define TEENSY_PIN34_IOPORT     IOPORT5
+#define TEENSY_PIN24_IOPORT     IOPORT5
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN51)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.mk
new file mode 100644
index 000000000..e7869a104
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_5/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.c
new file mode 100644
index 000000000..e59f4ae2c
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.c
@@ -0,0 +1,216 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA0 - SWD
+             * PTA3 - SWD
+             * PTA5 - PIN25
+             * PTA12 - PIN3
+             * PTA13 - PIN4
+             * PTA14 - PIN26
+             * PTA15 - PIN27
+             * PTA16 - PIN28
+             * PTA17 - PIN39
+             * PTA18 - Crystal
+             * PTA19 - Crystal
+             * PTA26 - PIN42
+             * PTA28 - PIN40
+             * PTA29 - PIN41
+             *
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0 - PIN16
+             * PTB1 - PIN17
+             * PTB2 - PIN19
+             * PTB3 - PIN18
+             * PTB4 - PIN49
+             * PTB5 - PIN50
+             * PTB10 - PIN31
+             * PTB11 - PIN32
+             * PTB16 - PIN0 - UART0_RX 
+             * PTB17 - PIN1 - UART0_TX
+             * PTB18 - PIN29
+             * PTB19 - PIN30
+             * PTB20 - PIN43
+             * PTB21 - PIN46
+             * PTB22 - PIN44
+             * PTB23 - PIN45
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             * PTC0 - PIN15
+             * PTC1 - PIN22
+             * PTC2 - PIN23
+             * PTC3 - PIN9
+             * PTC4 - PIN10
+             * PTC5 - PIN13
+             * PTC6 - PIN11
+             * PTC7 - PIN12
+             * PTC8 - PIN35
+             * PTC9 - PIN36
+             * PTC10 - PIN37
+             * PTC11 - PIN38
+             *
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0 - PIN2
+             * PTD1 - PIN14
+             * PTD2 - PIN7
+             * PTD3 - PIN8
+             * PTD4 - PIN6
+             * PTD5 - PIN20
+             * PTD6 - PIN21
+             * PTD7 - PIN5
+             * PTD8 - PIN47
+             * PTD9 - PIN48
+             * PTD11 - PIN55
+             * PTD12 - PIN53
+             * PTD13 - PIN52
+             * PTD14 - PIN51
+             * PTD15 - PIN54
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE0 - SDHC
+             * PTE1 - SDHC
+             * PTE2 - SDHC
+             * PTE3 - SDHC
+             * PTE4 - SDHC
+             * PTE5 - SDHC
+             * PTE6 - USB OTG power switch
+             * PTE10 - PIN56
+             * PTE11 - PIN57
+             * PTE24 - PIN33
+             * PTE25 - PIN34
+             * PTE26 - PIN24
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  MK66F18_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.h
new file mode 100644
index 000000000..0607d56f0
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.h
@@ -0,0 +1,345 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy 3.6 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3_6
+#define BOARD_NAME                  "PJRC Teensy 3.6"
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC0_CR_SC8P_SET(1) | OSC0_CR_SC2P_SET(1) | OSC0_CR_ERCLKEN_SET(1)
+/*
+ * MCU type
+ */
+#define MK66F18
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define PORTA_PIN1                  1
+#define PORTA_PIN2                  2
+#define PORTA_PIN3                  3
+#define PORTA_PIN4                  4
+#define TEENSY_PIN25                5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define TEENSY_PIN3                 12
+#define TEENSY_PIN4                 13
+#define TEENSY_PIN26                14
+#define TEENSY_PIN27                15
+#define TEENSY_PIN28                16
+#define TEENSY_PIN39                17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define TEENSY_PIN42                26
+#define PORTA_PIN27                 27
+#define TEENSY_PIN40                28
+#define TEENSY_PIN41                29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+#define TEENSY_PIN40_IOPORT  IOPORT1
+#define TEENSY_PIN41_IOPORT  IOPORT1
+#define TEENSY_PIN42_IOPORT  IOPORT1
+#define TEENSY_PIN3_IOPORT   IOPORT1
+#define TEENSY_PIN4_IOPORT   IOPORT1
+#define TEENSY_PIN25_IOPORT  IOPORT1
+#define TEENSY_PIN26_IOPORT  IOPORT1
+#define TEENSY_PIN27_IOPORT  IOPORT1
+#define TEENSY_PIN28_IOPORT  IOPORT1
+#define TEENSY_PIN39_IOPORT  IOPORT1
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define TEENSY_PIN49                4
+#define TEENSY_PIN50                5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define TEENSY_PIN31                10
+#define TEENSY_PIN32                11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define TEENSY_PIN29                18
+#define TEENSY_PIN30                19
+#define TEENSY_PIN43                20
+#define TEENSY_PIN46                21
+#define TEENSY_PIN44                22
+#define TEENSY_PIN45                23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+#define TEENSY_PIN49_IOPORT  IOPORT2
+#define TEENSY_PIN50_IOPORT  IOPORT2
+#define TEENSY_PIN43_IOPORT  IOPORT2
+#define TEENSY_PIN44_IOPORT  IOPORT2
+#define TEENSY_PIN45_IOPORT  IOPORT2
+#define TEENSY_PIN46_IOPORT  IOPORT2
+#define TEENSY_PIN0_IOPORT   IOPORT2
+#define TEENSY_PIN1_IOPORT   IOPORT2
+#define TEENSY_PIN29_IOPORT  IOPORT2
+#define TEENSY_PIN30_IOPORT  IOPORT2
+#define TEENSY_PIN31_IOPORT  IOPORT2
+#define TEENSY_PIN32_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT  IOPORT2
+#define TEENSY_PIN17_IOPORT  IOPORT2
+#define TEENSY_PIN19_IOPORT  IOPORT2
+#define TEENSY_PIN18_IOPORT  IOPORT2
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define TEENSY_PIN35                8
+#define TEENSY_PIN36                9
+#define TEENSY_PIN37                10
+#define TEENSY_PIN38                11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+#define TEENSY_PIN9_IOPORT   IOPORT3
+#define TEENSY_PIN10_IOPORT  IOPORT3
+#define TEENSY_PIN11_IOPORT  IOPORT3
+#define TEENSY_PIN12_IOPORT  IOPORT3
+#define TEENSY_PIN35_IOPORT  IOPORT3
+#define TEENSY_PIN36_IOPORT  IOPORT3
+#define TEENSY_PIN37_IOPORT  IOPORT3
+#define TEENSY_PIN38_IOPORT  IOPORT3
+#define TEENSY_PIN13_IOPORT  IOPORT3
+#define TEENSY_PIN15_IOPORT  IOPORT3
+#define TEENSY_PIN22_IOPORT  IOPORT3
+#define TEENSY_PIN23_IOPORT  IOPORT3
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define TEENSY_PIN47                8
+#define TEENSY_PIN48                9
+#define PORTD_PIN10                 10
+#define TEENSY_PIN55                11
+#define TEENSY_PIN53                12
+#define TEENSY_PIN52                13
+#define TEENSY_PIN51                14
+#define TEENSY_PIN54                15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+#define TEENSY_PIN51_IOPORT  IOPORT4
+#define TEENSY_PIN52_IOPORT  IOPORT4
+#define TEENSY_PIN53_IOPORT  IOPORT4
+#define TEENSY_PIN54_IOPORT  IOPORT4
+#define TEENSY_PIN55_IOPORT  IOPORT4
+#define TEENSY_PIN47_IOPORT  IOPORT4
+#define TEENSY_PIN48_IOPORT  IOPORT4
+#define TEENSY_PIN2_IOPORT   IOPORT4
+#define TEENSY_PIN5_IOPORT   IOPORT4
+#define TEENSY_PIN6_IOPORT   IOPORT4
+#define TEENSY_PIN7_IOPORT   IOPORT4
+#define TEENSY_PIN8_IOPORT   IOPORT4
+#define TEENSY_PIN14_IOPORT  IOPORT4
+#define TEENSY_PIN20_IOPORT  IOPORT4
+#define TEENSY_PIN21_IOPORT  IOPORT4
+#define PORTE_PIN0                  0
+#define PORTE_PIN1                  1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define TEENSY_PIN56                10
+#define TEENSY_PIN57                11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define PORTE_PIN20                 20
+#define PORTE_PIN21                 21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define TEENSY_PIN33                24
+#define TEENSY_PIN34                25
+#define TEENSY_PIN24                26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define PORTE_PIN30                 30
+#define PORTE_PIN31                 31
+#define TEENSY_PIN56_IOPORT  IOPORT5
+#define TEENSY_PIN57_IOPORT  IOPORT5
+#define TEENSY_PIN24_IOPORT  IOPORT5
+#define TEENSY_PIN33_IOPORT  IOPORT5
+#define TEENSY_PIN34_IOPORT  IOPORT5
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.mk
new file mode 100644
index 000000000..ba25c8560
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_3_6/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.c
new file mode 100644
index 000000000..3efd66337
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.c
@@ -0,0 +1,47 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+}
+void __late_init(void) {
+  MIMXRT1062_clock_init();
+  MIMXRT1062_MPU_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.h
new file mode 100644
index 000000000..798fd8737
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.h
@@ -0,0 +1,404 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy 4.1 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_4_1
+#define BOARD_NAME                  "PJRC Teensy 4.1"
+// TODO: correct clock values
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL 
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC0_CR_SC8P_SET(1) | OSC0_CR_SC2P_SET(1) | OSC0_CR_ERCLKEN_SET(1)
+/*
+ * MCU type
+ */
+#define MIMXRT1062
+/*
+ * IO pins assignments.
+ *
+ * These come from (with light string replacement from CORE_ to TEENSY_ for
+ * consistency with the Teensy 3.6 port):
+ * https://github.com/PaulStoffregen/cores/blob/master/teensy4/core_pins.h
+ *
+ */
+// We expose teensy pin numbers
+#define TEENSY_PIN0 0
+#define TEENSY_PIN1 1
+#define TEENSY_PIN2 2
+#define TEENSY_PIN3 3
+#define TEENSY_PIN4 4
+#define TEENSY_PIN5 5
+#define TEENSY_PIN6 6
+#define TEENSY_PIN7 7
+#define TEENSY_PIN8 8
+#define TEENSY_PIN9 9
+#define TEENSY_PIN10 10
+#define TEENSY_PIN11 11
+#define TEENSY_PIN12 12
+#define TEENSY_PIN13 13
+#define TEENSY_PIN14 14
+#define TEENSY_PIN15 15
+#define TEENSY_PIN16 16
+#define TEENSY_PIN17 17
+#define TEENSY_PIN18 18
+#define TEENSY_PIN19 19
+#define TEENSY_PIN20 20
+#define TEENSY_PIN21 21
+#define TEENSY_PIN22 22
+#define TEENSY_PIN23 23
+#define TEENSY_PIN24 24
+#define TEENSY_PIN25 25
+#define TEENSY_PIN26 26
+#define TEENSY_PIN27 27
+#define TEENSY_PIN28 28
+#define TEENSY_PIN29 29
+#define TEENSY_PIN30 30
+#define TEENSY_PIN31 31
+#define TEENSY_PIN32 32
+#define TEENSY_PIN33 33
+#define TEENSY_PIN34 34
+#define TEENSY_PIN35 35
+#define TEENSY_PIN36 36
+#define TEENSY_PIN37 37
+#define TEENSY_PIN38 38
+#define TEENSY_PIN39 39
+#define TEENSY_PIN40 40
+#define TEENSY_PIN41 41
+#define TEENSY_PIN42 42
+#define TEENSY_PIN43 43
+#define TEENSY_PIN44 44
+#define TEENSY_PIN45 45
+#define TEENSY_PIN46 46
+#define TEENSY_PIN47 47
+#define TEENSY_PIN48 48
+#define TEENSY_PIN49 49
+#define TEENSY_PIN50 50
+#define TEENSY_PIN51 51
+#define TEENSY_PIN52 52
+#define TEENSY_PIN53 53
+#define TEENSY_PIN54 54
+#define TEENSY_PIN0_BIT           3
+#define TEENSY_PIN1_BIT           2
+#define TEENSY_PIN2_BIT           4
+#define TEENSY_PIN3_BIT           5
+#define TEENSY_PIN4_BIT           6
+#define TEENSY_PIN5_BIT           8
+#define TEENSY_PIN6_BIT           10
+#define TEENSY_PIN7_BIT           17
+#define TEENSY_PIN8_BIT           16
+#define TEENSY_PIN9_BIT           11
+#define TEENSY_PIN10_BIT          0
+#define TEENSY_PIN11_BIT          2
+#define TEENSY_PIN12_BIT          1
+#define TEENSY_PIN13_BIT          3
+#define TEENSY_PIN14_BIT          18
+#define TEENSY_PIN15_BIT          19
+#define TEENSY_PIN16_BIT          23
+#define TEENSY_PIN17_BIT          22
+#define TEENSY_PIN18_BIT          17
+#define TEENSY_PIN19_BIT          16
+#define TEENSY_PIN20_BIT          26
+#define TEENSY_PIN21_BIT          27
+#define TEENSY_PIN22_BIT          24
+#define TEENSY_PIN23_BIT          25
+#define TEENSY_PIN24_BIT          12
+#define TEENSY_PIN25_BIT          13
+#define TEENSY_PIN26_BIT          30
+#define TEENSY_PIN27_BIT          31
+#define TEENSY_PIN28_BIT          18
+#define TEENSY_PIN29_BIT          31
+#define TEENSY_PIN30_BIT          23
+#define TEENSY_PIN31_BIT          22
+#define TEENSY_PIN32_BIT          12
+#define TEENSY_PIN33_BIT          7
+#define TEENSY_PIN34_BIT          29
+#define TEENSY_PIN35_BIT          28
+#define TEENSY_PIN36_BIT          18
+#define TEENSY_PIN37_BIT          19
+#define TEENSY_PIN38_BIT          28
+#define TEENSY_PIN39_BIT          29
+#define TEENSY_PIN40_BIT          20
+#define TEENSY_PIN41_BIT          21
+#define TEENSY_PIN42_BIT          15
+#define TEENSY_PIN43_BIT          14
+#define TEENSY_PIN44_BIT          13
+#define TEENSY_PIN45_BIT          12
+#define TEENSY_PIN46_BIT          17
+#define TEENSY_PIN47_BIT          16
+#define TEENSY_PIN48_BIT          24
+#define TEENSY_PIN49_BIT          27
+#define TEENSY_PIN50_BIT          28
+#define TEENSY_PIN51_BIT          22
+#define TEENSY_PIN52_BIT          26
+#define TEENSY_PIN53_BIT          25
+#define TEENSY_PIN54_BIT          29
+#define TEENSY_PIN0_IOPORT        GPIO6
+#define TEENSY_PIN1_IOPORT        GPIO6
+#define TEENSY_PIN2_IOPORT        GPIO9
+#define TEENSY_PIN3_IOPORT        GPIO9
+#define TEENSY_PIN4_IOPORT        GPIO9
+#define TEENSY_PIN5_IOPORT        GPIO9
+#define TEENSY_PIN6_IOPORT        GPIO7
+#define TEENSY_PIN7_IOPORT        GPIO7
+#define TEENSY_PIN8_IOPORT        GPIO7
+#define TEENSY_PIN9_IOPORT        GPIO7
+#define TEENSY_PIN10_IOPORT       GPIO7
+#define TEENSY_PIN11_IOPORT       GPIO7
+#define TEENSY_PIN12_IOPORT       GPIO7
+#define TEENSY_PIN13_IOPORT       GPIO7
+#define TEENSY_PIN14_IOPORT       GPIO6
+#define TEENSY_PIN15_IOPORT       GPIO6
+#define TEENSY_PIN16_IOPORT       GPIO6
+#define TEENSY_PIN17_IOPORT       GPIO6
+#define TEENSY_PIN18_IOPORT       GPIO6
+#define TEENSY_PIN19_IOPORT       GPIO6
+#define TEENSY_PIN20_IOPORT       GPIO6
+#define TEENSY_PIN21_IOPORT       GPIO6
+#define TEENSY_PIN22_IOPORT       GPIO6
+#define TEENSY_PIN23_IOPORT       GPIO6
+#define TEENSY_PIN24_IOPORT       GPIO6
+#define TEENSY_PIN25_IOPORT       GPIO6
+#define TEENSY_PIN26_IOPORT       GPIO6
+#define TEENSY_PIN27_IOPORT       GPIO6
+#define TEENSY_PIN28_IOPORT       GPIO8
+#define TEENSY_PIN29_IOPORT       GPIO9
+#define TEENSY_PIN30_IOPORT       GPIO8
+#define TEENSY_PIN31_IOPORT       GPIO8
+#define TEENSY_PIN32_IOPORT       GPIO7
+#define TEENSY_PIN33_IOPORT       GPIO9
+#define TEENSY_PIN34_IOPORT       GPIO7
+#define TEENSY_PIN35_IOPORT       GPIO7
+#define TEENSY_PIN36_IOPORT       GPIO7
+#define TEENSY_PIN37_IOPORT       GPIO7
+#define TEENSY_PIN38_IOPORT       GPIO6
+#define TEENSY_PIN39_IOPORT       GPIO6
+#define TEENSY_PIN40_IOPORT       GPIO6
+#define TEENSY_PIN41_IOPORT       GPIO6
+#define TEENSY_PIN42_IOPORT       GPIO8
+#define TEENSY_PIN43_IOPORT       GPIO8
+#define TEENSY_PIN44_IOPORT       GPIO8
+#define TEENSY_PIN45_IOPORT       GPIO8
+#define TEENSY_PIN46_IOPORT       GPIO8
+#define TEENSY_PIN47_IOPORT       GPIO8
+#define TEENSY_PIN48_IOPORT       GPIO9
+#define TEENSY_PIN49_IOPORT       GPIO9
+#define TEENSY_PIN50_IOPORT       GPIO9
+#define TEENSY_PIN51_IOPORT       GPIO9
+#define TEENSY_PIN52_IOPORT       GPIO9
+#define TEENSY_PIN53_IOPORT       GPIO9
+#define TEENSY_PIN54_IOPORT       GPIO9
+// mux config registers control which peripheral uses the pin
+#define TEENSY_PIN0_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03
+#define TEENSY_PIN1_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02
+#define TEENSY_PIN2_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04
+#define TEENSY_PIN3_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05
+#define TEENSY_PIN4_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06
+#define TEENSY_PIN5_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08
+#define TEENSY_PIN6_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10
+#define TEENSY_PIN7_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01
+#define TEENSY_PIN8_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00
+#define TEENSY_PIN9_MUX        kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11
+#define TEENSY_PIN10_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00
+#define TEENSY_PIN11_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02
+#define TEENSY_PIN12_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01
+#define TEENSY_PIN13_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03
+#define TEENSY_PIN14_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02
+#define TEENSY_PIN15_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03
+#define TEENSY_PIN16_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07
+#define TEENSY_PIN17_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06
+#define TEENSY_PIN18_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01
+#define TEENSY_PIN19_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00
+#define TEENSY_PIN20_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10
+#define TEENSY_PIN21_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11
+#define TEENSY_PIN22_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08
+#define TEENSY_PIN23_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09
+#define TEENSY_PIN24_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12
+#define TEENSY_PIN25_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13
+#define TEENSY_PIN26_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14
+#define TEENSY_PIN27_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15
+#define TEENSY_PIN28_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32
+#define TEENSY_PIN29_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31
+#define TEENSY_PIN30_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37
+#define TEENSY_PIN31_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36
+#define TEENSY_PIN32_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12
+#define TEENSY_PIN33_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07
+#define TEENSY_PIN34_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13
+#define TEENSY_PIN35_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12
+#define TEENSY_PIN36_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02
+#define TEENSY_PIN37_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03
+#define TEENSY_PIN38_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12
+#define TEENSY_PIN39_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13
+#define TEENSY_PIN40_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04
+#define TEENSY_PIN41_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05
+#define TEENSY_PIN42_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03
+#define TEENSY_PIN43_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02
+#define TEENSY_PIN44_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01
+#define TEENSY_PIN45_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00
+#define TEENSY_PIN46_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05
+#define TEENSY_PIN47_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04
+#define TEENSY_PIN48_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24
+#define TEENSY_PIN49_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27
+#define TEENSY_PIN50_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28
+#define TEENSY_PIN51_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22
+#define TEENSY_PIN52_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26
+#define TEENSY_PIN53_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25
+#define TEENSY_PIN54_MUX       kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29
+// pad config registers control pullup/pulldown/keeper, drive strength, etc
+#define TEENSY_PIN0_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03
+#define TEENSY_PIN1_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02
+#define TEENSY_PIN2_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04
+#define TEENSY_PIN3_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05
+#define TEENSY_PIN4_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06
+#define TEENSY_PIN5_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08
+#define TEENSY_PIN6_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10
+#define TEENSY_PIN7_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01
+#define TEENSY_PIN8_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00
+#define TEENSY_PIN9_PAD     kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11
+#define TEENSY_PIN10_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00
+#define TEENSY_PIN11_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02
+#define TEENSY_PIN12_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01
+#define TEENSY_PIN13_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03
+#define TEENSY_PIN14_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02
+#define TEENSY_PIN15_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03
+#define TEENSY_PIN16_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07
+#define TEENSY_PIN17_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06
+#define TEENSY_PIN18_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01
+#define TEENSY_PIN19_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00
+#define TEENSY_PIN20_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10
+#define TEENSY_PIN21_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11
+#define TEENSY_PIN22_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08
+#define TEENSY_PIN23_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09
+#define TEENSY_PIN24_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12
+#define TEENSY_PIN25_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13
+#define TEENSY_PIN26_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14
+#define TEENSY_PIN27_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15
+#define TEENSY_PIN28_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32
+#define TEENSY_PIN29_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31
+#define TEENSY_PIN30_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37
+#define TEENSY_PIN31_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36
+#define TEENSY_PIN32_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12
+#define TEENSY_PIN33_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07
+#define TEENSY_PIN34_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13
+#define TEENSY_PIN35_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12
+#define TEENSY_PIN36_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02
+#define TEENSY_PIN37_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03
+#define TEENSY_PIN38_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12
+#define TEENSY_PIN39_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13
+#define TEENSY_PIN40_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04
+#define TEENSY_PIN41_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05
+#define TEENSY_PIN42_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03
+#define TEENSY_PIN43_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02
+#define TEENSY_PIN44_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01
+#define TEENSY_PIN45_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00
+#define TEENSY_PIN46_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05
+#define TEENSY_PIN47_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04
+#define TEENSY_PIN48_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24
+#define TEENSY_PIN49_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27
+#define TEENSY_PIN50_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28
+#define TEENSY_PIN51_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22
+#define TEENSY_PIN52_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26
+#define TEENSY_PIN53_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25
+#define TEENSY_PIN54_PAD    kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.mk
new file mode 100644
index 000000000..adfc7a34b
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_4_1/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_4_1/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_4_1
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.c b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.c
new file mode 100644
index 000000000..93444daa3
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.c
@@ -0,0 +1,177 @@
+/*
+    ChibiOS - Copyright (C) 2016 flabbergast <[email protected]>
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA1 - PIN3
+             * PTA2 - PIN4
+             *
+             * PTA18/19 crystal
+             * PTA0/3 SWD
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,      PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0  - PIN16
+             * PTB1  - PIN17
+             * PTB2  - PIN19
+             * PTB3  - PIN18
+             * PTB16 - PIN0 - UART0_TX
+             * PTB17 - PIN1 - UART0_RX
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             *
+             * PTC0  - PIN15
+             * PTC1  - PIN22
+             * PTC2  - PIN23
+             * PTC3  - PIN9
+             * PTC4  - PIN10
+             * PTC5  - PIN13
+             * PTC6  - PIN11
+             * PTC7  - PIN12
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0  - PIN2
+             * PTD1  - PIN14
+             * PTD2  - PIN7
+             * PTD3  - PIN8
+             * PTD4  - PIN6
+             * PTD5  - PIN20
+             * PTD6  - PIN21
+             * PTD7  - PIN5
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE20 - PIN24
+             * PTE21 - PIN25
+             * PTE30 - PIN26
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+  kl2x_clock_init();
+}
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.h b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.h
new file mode 100644
index 000000000..6bfe094ce
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.h
@@ -0,0 +1,280 @@
+/*
+    ChibiOS - Copyright (C) 2016 flabbergast <[email protected]>
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the PJRC Teensy LC board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_LC
+#define BOARD_NAME                  "PJRC Teensy LC"
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P|OSC_CR_ERCLKEN
+/*
+ * MCU type
+ */
+#define KL26
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define TEENSY_PIN3                 1
+#define TEENSY_PIN4                 2
+#define PORTA_PIN3                  3
+#define PORTA_PIN4                  4
+#define PORTA_PIN5                  5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define PORTA_PIN12                 12
+#define PORTA_PIN13                 13
+#define PORTA_PIN14                 14
+#define PORTA_PIN15                 15
+#define PORTA_PIN16                 16
+#define PORTA_PIN17                 17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define PORTA_PIN26                 26
+#define PORTA_PIN27                 27
+#define PORTA_PIN28                 28
+#define PORTA_PIN29                 29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+#define TEENSY_PIN3_IOPORT  IOPORT1
+#define TEENSY_PIN4_IOPORT  IOPORT1
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define PORTB_PIN4                  4
+#define PORTB_PIN5                  5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define PORTB_PIN10                 10
+#define PORTB_PIN11                 11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define PORTB_PIN18                 18
+#define PORTB_PIN19                 19
+#define PORTB_PIN20                 20
+#define PORTB_PIN21                 21
+#define PORTB_PIN22                 22
+#define PORTB_PIN23                 23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+#define TEENSY_PIN0_IOPORT  IOPORT2
+#define TEENSY_PIN1_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT IOPORT2
+#define TEENSY_PIN17_IOPORT IOPORT2
+#define TEENSY_PIN18_IOPORT IOPORT2
+#define TEENSY_PIN19_IOPORT IOPORT2
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define PORTC_PIN8                  8
+#define PORTC_PIN9                  9
+#define PORTC_PIN10                 10
+#define PORTC_PIN11                 11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+#define TEENSY_PIN9_IOPORT  IOPORT3
+#define TEENSY_PIN10_IOPORT IOPORT3
+#define TEENSY_PIN11_IOPORT IOPORT3
+#define TEENSY_PIN12_IOPORT IOPORT3
+#define TEENSY_PIN13_IOPORT IOPORT3
+#define TEENSY_PIN15_IOPORT IOPORT3
+#define TEENSY_PIN22_IOPORT IOPORT3
+#define TEENSY_PIN23_IOPORT IOPORT3
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define PORTD_PIN8                  8
+#define PORTD_PIN9                  9
+#define PORTD_PIN10                 10
+#define PORTD_PIN11                 11
+#define PORTD_PIN12                 12
+#define PORTD_PIN13                 13
+#define PORTD_PIN14                 14
+#define PORTD_PIN15                 15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+#define TEENSY_PIN2_IOPORT  IOPORT4
+#define TEENSY_PIN5_IOPORT  IOPORT4
+#define TEENSY_PIN6_IOPORT  IOPORT4
+#define TEENSY_PIN7_IOPORT  IOPORT4
+#define TEENSY_PIN8_IOPORT  IOPORT4
+#define TEENSY_PIN14_IOPORT IOPORT4
+#define TEENSY_PIN20_IOPORT IOPORT4
+#define TEENSY_PIN21_IOPORT IOPORT4
+#define PORTE_PIN0                  0
+#define PORTE_PIN1                  1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define PORTE_PIN10                 10
+#define PORTE_PIN11                 11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define TEENSY_PIN24                20
+#define TEENSY_PIN25                21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define PORTE_PIN24                 24
+#define PORTE_PIN25                 25
+#define PORTE_PIN26                 26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define TEENSY_PIN26                30
+#define PORTE_PIN31                 31
+#define TEENSY_PIN24_IOPORT IOPORT5
+#define TEENSY_PIN25_IOPORT IOPORT5
+#define TEENSY_PIN26_IOPORT IOPORT5
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_LED            LINE_PIN13
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.mk b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.mk
new file mode 100644
index 000000000..4d7d5a553
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/PJRC_TEENSY_LC/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_LC
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.c b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.c
new file mode 100644
index 000000000..36a27cb58
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  gd32_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+    /* Free B4 pin by disabling JTAG NJTRST. */
+    AFIO->PCF0 |= AFIO_PCF0_SWJ_CFG_NOJNTRST;
+}
diff --git a/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.h b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.h
new file mode 100644
index 000000000..5ce1b8716
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.h
@@ -0,0 +1,140 @@
+/*
+    ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for a Generic GD32VF103 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_GD32VF103
+#define BOARD_NAME              "Sipeed Longan Nano GD32VF103CBT6"
+#define BOARD_USBFS_NOVBUSSENS
+/*
+ * Board frequencies.
+ */
+#define GD32_LXTALCLK              32768
+#define GD32_HXTALCLK            8000000
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define GD32VF103CB
+/*
+ * IO pins assignments
+ */
+#define PIN_GREEN_LED         1
+#define PIN_BLUE_LED          2
+#define PIN_RED_LED           13
+#define PIN_DISPLAY_MISO      6
+#define PIN_DISPLAY_MOSI      7
+#define PIN_DISPLAY_SCK       5
+#define PIN_DISPLAY_CS        2
+#define PIN_DISPLAY_DC        0
+#define PIN_DISPLAY_RST       1
+#define LINE_GREEN_LED         PAL_LINE(GPIOA, PIN_GREEN_LED)
+#define LINE_BLUE_LED          PAL_LINE(GPIOA, PIN_BLUE_LED)
+#define LINE_RED_LED           PAL_LINE(GPIOC, PIN_RED_LED)
+#define LINE_DISPLAY_MISO      PAL_LINE(GPIOA, PIN_DISPLAY_MISO)
+#define LINE_DISPLAY_MOSI      PAL_LINE(GPIOA, PIN_DISPLAY_MOSI)
+#define LINE_DISPLAY_SCK       PAL_LINE(GPIOA, PIN_DISPLAY_SCK)
+#define LINE_DISPLAY_CS        PAL_LINE(GPIOB, PIN_DISPLAY_CS)
+#define LINE_DISPLAY_DC        PAL_LINE(GPIOB, PIN_DISPLAY_DC)
+#define LINE_DISPLAY_RST       PAL_LINE(GPIOB, PIN_DISPLAY_RST)
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * A1 - Green LED - Push Pull output 50MHz
+ * A2 - Blue LED - Push Pull output 50MHz
+ * A5 - Display SCK - Alternate Push Pull output 50MHz.
+ * A7 - Display MOSI - Alternate Push Pull output 50MHz.
+ */
+#define VAL_GPIOACRL            0xB8B88338      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x88888888      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * B0 - Display DC - Push Pull output 50Mhz.
+ * B1 - Display RST - Push Pull output 50Mhz.
+ * B2 - Display CS - Push Pull output 50Mhz.
+ */
+#define VAL_GPIOBCRL            0x88888333      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888888      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ * C13 - RED LED - Push Pull output 50MHz
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88388888      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIODCRL            0x88888888      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.mk b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.mk
new file mode 100644
index 000000000..960fc2678
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/SIPEED_LONGAN_NANO/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/SIPEED_LONGAN_NANO
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
new file mode 100644
index 000000000..266465a22
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
@@ -0,0 +1,246 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#include "hal.h"
+#include "stm32_gpio.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+} gpio_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
+#endif
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+static void stm32_gpio_init(void) {
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB(STM32_GPIO_EN_MASK);
+  rccEnableAHB(STM32_GPIO_EN_MASK, true);
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  stm32_gpio_init();
+  stm32_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h
new file mode 100644
index 000000000..34eba1739
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.h
@@ -0,0 +1,757 @@
+/*
+    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for ST STM32F0-Discovery board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F0308_DISCOVERY
+#define BOARD_NAME                  "ST STM32F0308-Discovery"
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0
+#endif
+#define STM32_LSEDRV                (3 << 3)
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                0
+#endif
+#define STM32_HSE_BYPASS
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F030x8
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON                0
+#define GPIOA_PIN1                  1
+#define GPIOA_PIN2                  2
+#define GPIOA_PIN3                  3
+#define GPIOA_PIN4                  4
+#define GPIOA_PIN5                  5
+#define GPIOA_PIN6                  6
+#define GPIOA_PIN7                  7
+#define GPIOA_PIN8                  8
+#define GPIOA_PIN9                  9
+#define GPIOA_PIN10                 10
+#define GPIOA_PIN11                 11
+#define GPIOA_PIN12                 12
+#define GPIOA_SWDAT                 13
+#define GPIOA_SWCLK                 14
+#define GPIOA_PIN15                 15
+#define GPIOB_PIN0                  0
+#define GPIOB_PIN1                  1
+#define GPIOB_PIN2                  2
+#define GPIOB_PIN3                  3
+#define GPIOB_PIN4                  4
+#define GPIOB_PIN5                  5
+#define GPIOB_PIN6                  6
+#define GPIOB_PIN7                  7
+#define GPIOB_PIN8                  8
+#define GPIOB_PIN9                  9
+#define GPIOB_PIN10                 10
+#define GPIOB_PIN11                 11
+#define GPIOB_PIN12                 12
+#define GPIOB_PIN13                 13
+#define GPIOB_PIN14                 14
+#define GPIOB_PIN15                 15
+#define GPIOC_PIN0                  0
+#define GPIOC_PIN1                  1
+#define GPIOC_PIN2                  2
+#define GPIOC_PIN3                  3
+#define GPIOC_PIN4                  4
+#define GPIOC_PIN5                  5
+#define GPIOC_PIN6                  6
+#define GPIOC_PIN7                  7
+#define GPIOC_LED4                  8
+#define GPIOC_LED3                  9
+#define GPIOC_PIN10                 10
+#define GPIOC_PIN11                 11
+#define GPIOC_PIN12                 12
+#define GPIOC_PIN13                 13
+#define GPIOC_OSC32_IN              14
+#define GPIOC_OSC32_OUT             15
+#define GPIOD_PIN0                  0
+#define GPIOD_PIN1                  1
+#define GPIOD_PIN2                  2
+#define GPIOD_PIN3                  3
+#define GPIOD_PIN4                  4
+#define GPIOD_PIN5                  5
+#define GPIOD_PIN6                  6
+#define GPIOD_PIN7                  7
+#define GPIOD_PIN8                  8
+#define GPIOD_PIN9                  9
+#define GPIOD_PIN10                 10
+#define GPIOD_PIN11                 11
+#define GPIOD_PIN12                 12
+#define GPIOD_PIN13                 13
+#define GPIOD_PIN14                 14
+#define GPIOD_PIN15                 15
+#define GPIOF_OSC_IN                0
+#define GPIOF_OSC_OUT               1
+#define GPIOF_PIN2                  2
+#define GPIOF_PIN3                  3
+#define GPIOF_PIN4                  4
+#define GPIOF_PIN5                  5
+#define GPIOF_PIN6                  6
+#define GPIOF_PIN7                  7
+#define GPIOF_PIN8                  8
+#define GPIOF_PIN9                  9
+#define GPIOF_PIN10                 10
+#define GPIOF_PIN11                 11
+#define GPIOF_PIN12                 12
+#define GPIOF_PIN13                 13
+#define GPIOF_PIN14                 14
+#define GPIOF_PIN15                 15
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_2M(n)            (0U << ((n) * 2))
+#define PIN_OSPEED_10M(n)           (1U << ((n) * 2))
+#define PIN_OSPEED_40M(n)           (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v)           ((v##U) << ((n % 8) * 4))
+/*
+ * GPIOA setup:
+ *
+ * PA0  - BUTTON                    (input floating).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - PIN2                      (input pullup).
+ * PA3  - PIN3                      (input pullup).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - PIN7                      (input pullup).
+ * PA8  - PIN8                      (input pullup).
+ * PA9  - PIN9                      (input pullup).
+ * PA10 - PIN10                     (input pullup).
+ * PA11 - PIN11                     (input pullup).
+ * PA12 - PIN12                     (input pullup).
+ * PA13 - SWDAT                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_BUTTON) |         \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOA_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDAT) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDAT) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_2M(GPIOA_BUTTON) |          \
+                                     PIN_OSPEED_2M(GPIOA_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOA_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOA_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOA_PIN12) |           \
+                                     PIN_OSPEED_40M(GPIOA_SWDAT) |          \
+                                     PIN_OSPEED_40M(GPIOA_SWCLK) |          \
+                                     PIN_OSPEED_40M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_BUTTON) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOA_SWDAT) |        \
+                                     PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_BUTTON) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWDAT) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_BUTTON, 0) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWDAT, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0))
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - PIN3                      (input pullup).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6                      (input pullup).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - PIN10                     (input pullup).
+ * PB11 - PIN11                     (input pullup).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - PIN13                     (input pullup).
+ * PB14 - PIN14                     (input pullup).
+ * PB15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_2M(GPIOB_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN1) |            \
+                                     PIN_OSPEED_40M(GPIOB_PIN2) |           \
+                                     PIN_OSPEED_40M(GPIOB_PIN3) |           \
+                                     PIN_OSPEED_40M(GPIOB_PIN4) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOB_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0))
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - LED4                      (output pushpull maximum).
+ * PC9  - LED3                      (output pushpull maximum).
+ * PC10 - PIN10                     (input pullup).
+ * PC11 - PIN11                     (input pullup).
+ * PC12 - PIN12                     (input pullup).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - OSC32_IN                  (input floating).
+ * PC15 - OSC32_OUT                 (input floating).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_OUTPUT(GPIOC_LED4) |          \
+                                     PIN_MODE_OUTPUT(GPIOC_LED3) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_IN) |       \
+                                     PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_LED3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_2M(GPIOC_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOC_PIN7) |            \
+                                     PIN_OSPEED_40M(GPIOC_LED4) |           \
+                                     PIN_OSPEED_40M(GPIOC_LED3) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOC_PIN13) |           \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_IN) |       \
+                                     PIN_OSPEED_40M(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED4) |       \
+                                     PIN_PUPDR_FLOATING(GPIOC_LED3) |       \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_LOW(GPIOC_LED4) |              \
+                                     PIN_ODR_LOW(GPIOC_LED3) |              \
+                                     PIN_ODR_HIGH(GPIOC_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_IN) |         \
+                                     PIN_ODR_HIGH(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_LED4, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_LED3, 0) |           \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOC_OSC32_IN, 0) |       \
+                                     PIN_AFIO_AF(GPIOC_OSC32_OUT, 0))
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - PIN5                      (input pullup).
+ * PD6  - PIN6                      (input pullup).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - PIN8                      (input pullup).
+ * PD9  - PIN9                      (input pullup).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - PIN12                     (input pullup).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_2M(GPIOD_PIN0) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN1) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOD_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0))
+/*
+ * GPIOF setup:
+ *
+ * PF0  - OSC_IN                    (input floating).
+ * PF1  - OSC_OUT                   (input floating).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - PIN11                     (input pullup).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_OSC_IN) |         \
+                                     PIN_MODE_INPUT(GPIOF_OSC_OUT) |        \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_OSC_IN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_OSC_OUT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_2M(GPIOF_OSC_IN) |          \
+                                     PIN_OSPEED_2M(GPIOF_OSC_OUT) |         \
+                                     PIN_OSPEED_2M(GPIOF_PIN2) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN3) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN4) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN5) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN6) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN7) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN8) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN9) |            \
+                                     PIN_OSPEED_2M(GPIOF_PIN10) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN11) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN12) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN13) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN14) |           \
+                                     PIN_OSPEED_2M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_FLOATING(GPIOF_OSC_IN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOF_OSC_OUT) |    \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_OSC_IN) |           \
+                                     PIN_ODR_HIGH(GPIOF_OSC_OUT) |          \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_OSC_IN, 0) |         \
+                                     PIN_AFIO_AF(GPIOF_OSC_OUT, 0) |        \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0) |           \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0))
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk
new file mode 100644
index 000000000..52ac32bbc
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/ST_STM32F0308_DISCOVERY/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/ST_STM32F0308_DISCOVERY
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.c b/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.c
new file mode 100644
index 000000000..cd9e32ee7
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.c
@@ -0,0 +1,288 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#include "hal.h"
+#include "stm32_gpio.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_setup_t          PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_setup_t          PKData;
+#endif
+} gpio_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+  {
+    VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+    VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOB
+  {
+    VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+    VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOC
+  {
+    VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+    VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOD
+  {
+    VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+    VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOE
+  {
+    VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+    VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOF
+  {
+    VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+    VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOG
+  {
+    VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+    VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOH
+  {
+    VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+    VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOI
+  {
+    VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+    VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOJ
+  {
+    VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+    VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH
+  },
+#endif
+#if STM32_HAS_GPIOK
+  {
+    VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+    VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH
+  }
+#endif
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+static void stm32_gpio_init(void) {
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB1(STM32_GPIO_EN_MASK);
+  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+  gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+  gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  stm32_gpio_init();
+  stm32_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.h b/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.h
new file mode 100644
index 000000000..f24a5d479
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/boards/ST_STM32F411_DISCOVERY/board.h
@@ -0,0 +1,1339 @@
+/*
+    ChibiOS                                  - Copyright (C) 2006..2018 Giovanni Di Sirio
+    ChibiOS ST32F411-Disco Board Description - Copyright (C) 2019 Tim Rheinfels
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+/*
+ * Did so... Using the ChibiOS / STM32F4-Disco HAL with the following changes:
+ *
+ * - STM32F4 -> STM32F411
+ * - Removed all pad specializations except for SWD and HSE oscillator
+ */
+#ifndef BOARD_H
+#define BOARD_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/*
+ * Setup for STMicroelectronics STM32F411-Discovery board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_STM32F411_DISCOVERY
+#define BOARD_NAME                  "STMicroelectronics STM32F411-Discovery"
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                0U
+#endif
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                8000000U
+#endif
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300U
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F411xE
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0                  0U
+#define GPIOA_PIN1                  1U
+#define GPIOA_PIN2                  2U
+#define GPIOA_PIN3                  3U
+#define GPIOA_PIN4                  4U
+#define GPIOA_PIN5                  5U
+#define GPIOA_PIN6                  6U
+#define GPIOA_PIN7                  7U
+#define GPIOA_PIN8                  8U
+#define GPIOA_PIN9                  9U
+#define GPIOA_PIN10                 10U
+#define GPIOA_PIN11                 11U
+#define GPIOA_PIN12                 12U
+#define GPIOA_SWDIO                 13U
+#define GPIOA_SWCLK                 14U
+#define GPIOA_PIN15                 15U
+#define GPIOB_PIN0                  0U
+#define GPIOB_PIN1                  1U
+#define GPIOB_PIN2                  2U
+#define GPIOB_PIN3                  3U
+#define GPIOB_PIN4                  4U
+#define GPIOB_PIN5                  5U
+#define GPIOB_PIN6                  6U
+#define GPIOB_PIN7                  7U
+#define GPIOB_PIN8                  8U
+#define GPIOB_PIN9                  9U
+#define GPIOB_PIN10                 10U
+#define GPIOB_PIN11                 11U
+#define GPIOB_PIN12                 12U
+#define GPIOB_PIN13                 13U
+#define GPIOB_PIN14                 14U
+#define GPIOB_PIN15                 15U
+#define GPIOC_PIN0                  0U
+#define GPIOC_PIN1                  1U
+#define GPIOC_PIN2                  2U
+#define GPIOC_PIN3                  3U
+#define GPIOC_PIN4                  4U
+#define GPIOC_PIN5                  5U
+#define GPIOC_PIN6                  6U
+#define GPIOC_PIN7                  7U
+#define GPIOC_PIN8                  8U
+#define GPIOC_PIN9                  9U
+#define GPIOC_PIN10                 10U
+#define GPIOC_PIN11                 11U
+#define GPIOC_PIN12                 12U
+#define GPIOC_PIN13                 13U
+#define GPIOC_PIN14                 14U
+#define GPIOC_PIN15                 15U
+#define GPIOD_PIN0                  0U
+#define GPIOD_PIN1                  1U
+#define GPIOD_PIN2                  2U
+#define GPIOD_PIN3                  3U
+#define GPIOD_PIN4                  4U
+#define GPIOD_PIN5                  5U
+#define GPIOD_PIN6                  6U
+#define GPIOD_PIN7                  7U
+#define GPIOD_PIN8                  8U
+#define GPIOD_PIN9                  9U
+#define GPIOD_PIN10                 10U
+#define GPIOD_PIN11                 11U
+#define GPIOD_PIN12                 12U
+#define GPIOD_PIN13                 13U
+#define GPIOD_PIN14                 14U
+#define GPIOD_PIN15                 15U
+#define GPIOE_PIN0                  0U
+#define GPIOE_PIN1                  1U
+#define GPIOE_PIN2                  2U
+#define GPIOE_PIN3                  3U
+#define GPIOE_PIN4                  4U
+#define GPIOE_PIN5                  5U
+#define GPIOE_PIN6                  6U
+#define GPIOE_PIN7                  7U
+#define GPIOE_PIN8                  8U
+#define GPIOE_PIN9                  9U
+#define GPIOE_PIN10                 10U
+#define GPIOE_PIN11                 11U
+#define GPIOE_PIN12                 12U
+#define GPIOE_PIN13                 13U
+#define GPIOE_PIN14                 14U
+#define GPIOE_PIN15                 15U
+#define GPIOF_PIN0                  0U
+#define GPIOF_PIN1                  1U
+#define GPIOF_PIN2                  2U
+#define GPIOF_PIN3                  3U
+#define GPIOF_PIN4                  4U
+#define GPIOF_PIN5                  5U
+#define GPIOF_PIN6                  6U
+#define GPIOF_PIN7                  7U
+#define GPIOF_PIN8                  8U
+#define GPIOF_PIN9                  9U
+#define GPIOF_PIN10                 10U
+#define GPIOF_PIN11                 11U
+#define GPIOF_PIN12                 12U
+#define GPIOF_PIN13                 13U
+#define GPIOF_PIN14                 14U
+#define GPIOF_PIN15                 15U
+#define GPIOG_PIN0                  0U
+#define GPIOG_PIN1                  1U
+#define GPIOG_PIN2                  2U
+#define GPIOG_PIN3                  3U
+#define GPIOG_PIN4                  4U
+#define GPIOG_PIN5                  5U
+#define GPIOG_PIN6                  6U
+#define GPIOG_PIN7                  7U
+#define GPIOG_PIN8                  8U
+#define GPIOG_PIN9                  9U
+#define GPIOG_PIN10                 10U
+#define GPIOG_PIN11                 11U
+#define GPIOG_PIN12                 12U
+#define GPIOG_PIN13                 13U
+#define GPIOG_PIN14                 14U
+#define GPIOG_PIN15                 15U
+#define GPIOH_OSC_IN                0U
+#define GPIOH_OSC_OUT               1U
+#define GPIOH_PIN2                  2U
+#define GPIOH_PIN3                  3U
+#define GPIOH_PIN4                  4U
+#define GPIOH_PIN5                  5U
+#define GPIOH_PIN6                  6U
+#define GPIOH_PIN7                  7U
+#define GPIOH_PIN8                  8U
+#define GPIOH_PIN9                  9U
+#define GPIOH_PIN10                 10U
+#define GPIOH_PIN11                 11U
+#define GPIOH_PIN12                 12U
+#define GPIOH_PIN13                 13U
+#define GPIOH_PIN14                 14U
+#define GPIOH_PIN15                 15U
+#define GPIOI_PIN0                  0U
+#define GPIOI_PIN1                  1U
+#define GPIOI_PIN2                  2U
+#define GPIOI_PIN3                  3U
+#define GPIOI_PIN4                  4U
+#define GPIOI_PIN5                  5U
+#define GPIOI_PIN6                  6U
+#define GPIOI_PIN7                  7U
+#define GPIOI_PIN8                  8U
+#define GPIOI_PIN9                  9U
+#define GPIOI_PIN10                 10U
+#define GPIOI_PIN11                 11U
+#define GPIOI_PIN12                 12U
+#define GPIOI_PIN13                 13U
+#define GPIOI_PIN14                 14U
+#define GPIOI_PIN15                 15U
+/*
+ * IO lines assignments.
+ */
+#define LINE_SWDIO                  PAL_LINE(GPIOA, GPIOA_SWDIO)
+#define LINE_SWCLK                  PAL_LINE(GPIOA, GPIOA_SWCLK)
+#define LINE_OSC_IN                 PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT                PAL_LINE(GPIOH, 1U)
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))
+/*
+ * GPIOA setup:
+ *
+ * PA0  - PIN0                      (analog).
+ * PA1  - PIN1                      (analog).
+ * PA2  - PIN2                      (analog).
+ * PA3  - PIN3                      (analog).
+ * PA4  - PIN4                      (analog).
+ * PA5  - PIN5                      (analog).
+ * PA6  - PIN6                      (analog).
+ * PA7  - PIN7                      (analog).
+ * PA8  - PIN8                      (analog).
+ * PA9  - PIN9                      (analog).
+ * PA10 - PIN10                     (analog).
+ * PA11 - PIN11                     (analog).
+ * PA12 - PIN12                     (analog).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (analog).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_ANALOG(GPIOA_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK)  |  \
+                                     PIN_MODE_ANALOG(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN2)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN3)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN8)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN9)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN10)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN11)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN12)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_HIGH(GPIOA_PIN0)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN1)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN2)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN3)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN4)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN5)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN6)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN7)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN8)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN9)      |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN10)     |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN11)     |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN12)     |  \
+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO)     |  \
+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK)     |  \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_FLOATING(GPIOA_PIN0)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN1)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN2)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN3)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN4)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN5)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN6)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN7)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN8)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN9)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN10)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN11)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN12)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWDIO)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWCLK)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO)        |  \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK)        |  \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0U))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOA_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOA_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOA_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0U))
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (analog).
+ * PB1  - PIN1                      (analog).
+ * PB2  - PIN2                      (analog).
+ * PB3  - PIN3                      (analog).
+ * PB4  - PIN4                      (analog).
+ * PB5  - PIN5                      (analog).
+ * PB6  - PIN6                      (analog).
+ * PB7  - PIN7                      (analog).
+ * PB8  - PIN8                      (analog).
+ * PB9  - PIN9                      (analog).
+ * PB10 - PIN10                     (analog).
+ * PB11 - PIN11                     (analog).
+ * PB12 - PIN12                     (analog).
+ * PB13 - PIN13                     (analog).
+ * PB14 - PIN14                     (analog).
+ * PB15 - PIN15                     (analog).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_ANALOG(GPIOB_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_PIN13)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_PIN14)  |  \
+                                     PIN_MODE_ANALOG(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN10)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN11)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN13)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN14)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_PIN0)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN1)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN2)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN3)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN4)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN5)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN6)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN7)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN8)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN9)      |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN10)     |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN11)     |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN12)     |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN13)     |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN14)     |  \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_FLOATING(GPIOB_PIN0)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN1)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN2)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN3)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN4)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN5)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN6)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN7)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN8)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN9)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN10)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN11)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN12)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN13)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN14)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_PIN15))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN13)        |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN14)        |  \
+                                     PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOB_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOB_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOB_PIN13, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOB_PIN14, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOB_PIN15, 0U))
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (analog).
+ * PC1  - PIN1                      (analog).
+ * PC2  - PIN2                      (analog).
+ * PC3  - PIN3                      (analog).
+ * PC4  - PIN4                      (analog).
+ * PC5  - PIN5                      (analog).
+ * PC6  - PIN6                      (analog).
+ * PC7  - PIN7                      (analog).
+ * PC8  - PIN8                      (analog).
+ * PC9  - PIN9                      (analog).
+ * PC10 - PIN10                     (analog).
+ * PC11 - PIN11                     (analog).
+ * PC12 - PIN12                     (analog).
+ * PC13 - PIN13                     (analog).
+ * PC14 - PIN14                     (analog).
+ * PC15 - PIN15                     (analog).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_ANALOG(GPIOC_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_PIN13)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_PIN14)  |  \
+                                     PIN_MODE_ANALOG(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN9)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN10)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN11)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN12)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_PIN0)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN1)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN2)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN3)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN4)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN5)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN6)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN7)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN8)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN9)      |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN10)     |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN11)     |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN12)     |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN13)     |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN14)     |  \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_FLOATING(GPIOC_PIN0)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN1)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN2)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN3)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN4)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN5)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN6)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN7)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN8)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN9)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN10)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN11)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN12)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN13)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN14)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN13)        |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN14)        |  \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOC_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOC_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOC_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0U))
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (analog).
+ * PD1  - PIN1                      (analog).
+ * PD2  - PIN2                      (analog).
+ * PD3  - PIN3                      (analog).
+ * PD4  - PIN4                      (analog).
+ * PD5  - PIN5                      (analog).
+ * PD6  - PIN6                      (analog).
+ * PD7  - PIN7                      (analog).
+ * PD8  - PIN8                      (analog).
+ * PD9  - PIN9                      (analog).
+ * PD10 - PIN10                     (analog).
+ * PD11 - PIN11                     (analog).
+ * PD12 - PIN12                     (analog).
+ * PD13 - PIN13                     (analog).
+ * PD14 - PIN14                     (analog).
+ * PD15 - PIN15                     (analog).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_ANALOG(GPIOD_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_PIN13)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_PIN14)  |  \
+                                     PIN_MODE_ANALOG(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN5)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN6)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN8)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN9)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN12)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_HIGH(GPIOD_PIN0)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN1)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN2)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN3)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN4)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN5)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN6)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN7)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN8)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN9)      |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN10)     |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN11)     |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN12)     |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN13)     |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN14)     |  \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_FLOATING(GPIOD_PIN0)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN1)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN2)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN3)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN4)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN5)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN6)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN7)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN8)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN9)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN10)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN11)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN12)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN13)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN14)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN13)        |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN14)        |  \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOD_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0U))
+/*
+ * GPIOE setup:
+ *
+ * PE0  - PIN0                      (analog).
+ * PE1  - PIN1                      (analog).
+ * PE2  - PIN2                      (analog).
+ * PE3  - PIN3                      (analog).
+ * PE4  - PIN4                      (analog).
+ * PE5  - PIN5                      (analog).
+ * PE6  - PIN6                      (analog).
+ * PE7  - PIN7                      (analog).
+ * PE8  - PIN8                      (analog).
+ * PE9  - PIN9                      (analog).
+ * PE10 - PIN10                     (analog).
+ * PE11 - PIN11                     (analog).
+ * PE12 - PIN12                     (analog).
+ * PE13 - PIN13                     (analog).
+ * PE14 - PIN14                     (analog).
+ * PE15 - PIN15                     (analog).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_ANALOG(GPIOE_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOE_PIN13)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOE_PIN14)  |  \
+                                     PIN_MODE_ANALOG(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_PIN0)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN7)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN8)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN9)   |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN10)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN11)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN12)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN13)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN14)  |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_HIGH(GPIOE_PIN0)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN1)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN2)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN3)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN4)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN5)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN6)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN7)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN8)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN9)      |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN10)     |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN11)     |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN12)     |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN13)     |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN14)     |  \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_PIN0)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN1)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN2)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN3)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN4)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN5)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN6)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN7)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN8)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN9)   |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN10)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN11)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN12)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN13)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN14)  |  \
+                                     PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN13)        |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN14)        |  \
+                                     PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN7, 0U))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOE_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOE_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOE_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOE_PIN13, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOE_PIN14, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOE_PIN15, 0U))
+/*
+ * GPIOF setup:
+ *
+! * PF0  - PIN0                      (analog).
+ * PF1  - PIN1                      (analog).
+ * PF2  - PIN2                      (analog).
+ * PF3  - PIN3                      (analog).
+ * PF4  - PIN4                      (analog).
+ * PF5  - PIN5                      (analog).
+ * PF6  - PIN6                      (analog).
+ * PF7  - PIN7                      (analog).
+ * PF8  - PIN8                      (analog).
+ * PF9  - PIN9                      (analog).
+ * PF10 - PIN10                     (analog).
+ * PF11 - PIN11                     (analog).
+ * PF12 - PIN12                     (analog).
+ * PF13 - PIN13                     (analog).
+ * PF14 - PIN14                     (analog).
+ * PF15 - PIN15                     (analog).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_ANALOG(GPIOF_PIN0)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN1)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN2)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN3)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN4)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN5)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN6)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN7)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN8)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN9)      |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN10)     |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN11)     |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN12)     |  \
+                                     PIN_MODE_ALTERNATE(GPIOF_PIN13)  |  \
+                                     PIN_MODE_ALTERNATE(GPIOF_PIN14)  |  \
+                                     PIN_MODE_ANALOG(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPFR            (PIN_OTYPF_PUSHPULL(GPIOF_PIN0)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN1)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN2)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN3)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN4)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN5)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN6)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN7)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN8)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN9)   |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN10)  |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN11)  |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN12)  |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN13)  |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN14)  |  \
+                                     PIN_OTYPF_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPFEDR           (PIN_OSPFED_HIGH(GPIOF_PIN0)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN1)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN2)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN3)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN4)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN5)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN6)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN7)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN8)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN9)      |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN10)     |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN11)     |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN12)     |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN13)     |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN14)     |  \
+                                     PIN_OSPFED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPFR             (PIN_PUPFR_FLOATING(GPIOF_PIN0)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN1)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN2)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN3)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN4)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN5)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN6)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN7)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN8)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN9)   |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN10)  |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN11)  |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN12)  |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN13)  |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN14)  |  \
+                                     PIN_PUPFR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN1)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN2)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN3)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN4)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN5)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN6)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN7)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN8)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN9)         |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN10)        |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN11)        |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN12)        |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN13)        |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN14)        |  \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0U)      |  \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0U)     |  \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0U))