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diff --git a/lib/chibios-contrib/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h b/lib/chibios-contrib/os/hal/ports/NRF5/NRF52832/nrf52_bitfields.h
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1/*
2
3Copyright (c) 2010 - 2018, Nordic Semiconductor ASA
4
5All rights reserved.
6
7Redistribution and use in source and binary forms, with or without modification,
8are permitted provided that the following conditions are met:
9
101. Redistributions of source code must retain the above copyright notice, this
11 list of conditions and the following disclaimer.
12
132. Redistributions in binary form, except as embedded into a Nordic
14 Semiconductor ASA integrated circuit in a product or a software update for
15 such product, must reproduce the above copyright notice, this list of
16 conditions and the following disclaimer in the documentation and/or other
17 materials provided with the distribution.
18
193. Neither the name of Nordic Semiconductor ASA nor the names of its
20 contributors may be used to endorse or promote products derived from this
21 software without specific prior written permission.
22
234. This software, with or without modification, must only be used with a
24 Nordic Semiconductor ASA integrated circuit.
25
265. Any software provided in binary form under this license must not be reverse
27 engineered, decompiled, modified and/or disassembled.
28
29THIS SOFTWARE IS PROVIDED BY NORDIC SEMICONDUCTOR ASA "AS IS" AND ANY EXPRESS
30OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
31OF MERCHANTABILITY, NONINFRINGEMENT, AND FITNESS FOR A PARTICULAR PURPOSE ARE
32DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE
33LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
34CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
35GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
37LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
38OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39
40*/
41
42/** @addtogroup Nordic Semiconductor
43 * @{
44 */
45
46/** @addtogroup nrf52
47 * @{
48 */
49
50#ifndef __NRF52_BITS_H
51#define __NRF52_BITS_H
52
53/*lint ++flb "Enter library region" */
54
55/* Peripheral: AAR */
56/* Description: Accelerated Address Resolver */
57
58/* Register: AAR_INTENSET */
59/* Description: Enable interrupt */
60
61/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
62#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
63#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
64#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
65#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
66#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
67
68/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
69#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
70#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
71#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
72#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
73#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
74
75/* Bit 0 : Write '1' to Enable interrupt for END event */
76#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
77#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
78#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
79#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
80#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
81
82/* Register: AAR_INTENCLR */
83/* Description: Disable interrupt */
84
85/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
86#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
87#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
88#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
89#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
90#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
91
92/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
93#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
94#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
95#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
96#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
97#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
98
99/* Bit 0 : Write '1' to Disable interrupt for END event */
100#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
101#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
102#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
103#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
104#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
105
106/* Register: AAR_STATUS */
107/* Description: Resolution status */
108
109/* Bits 3..0 : The IRK that was used last time an address was resolved */
110#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
111#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
112
113/* Register: AAR_ENABLE */
114/* Description: Enable AAR */
115
116/* Bits 1..0 : Enable or disable AAR */
117#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
118#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
119#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
120#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
121
122/* Register: AAR_NIRK */
123/* Description: Number of IRKs */
124
125/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
126#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
127#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
128
129/* Register: AAR_IRKPTR */
130/* Description: Pointer to IRK data structure */
131
132/* Bits 31..0 : Pointer to the IRK data structure */
133#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
134#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
135
136/* Register: AAR_ADDRPTR */
137/* Description: Pointer to the resolvable address */
138
139/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
140#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
141#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
142
143/* Register: AAR_SCRATCHPTR */
144/* Description: Pointer to data area used for temporary storage */
145
146/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
147#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
148#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
149
150
151/* Peripheral: BPROT */
152/* Description: Block Protect */
153
154/* Register: BPROT_CONFIG0 */
155/* Description: Block protect configuration register 0 */
156
157/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
158#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
159#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
160#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
161#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
162
163/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
164#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
165#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
166#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
167#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
168
169/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
170#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
171#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
172#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
173#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
174
175/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
176#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
177#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
178#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
179#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
180
181/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
182#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
183#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
184#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
185#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
186
187/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
188#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
189#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
190#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
191#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
192
193/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
194#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
195#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
196#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
197#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
198
199/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
200#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
201#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
202#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
203#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
204
205/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
206#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
207#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
208#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
209#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
210
211/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
212#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
213#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
214#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
215#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
216
217/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
218#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
219#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
220#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
221#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
222
223/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
224#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
225#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
226#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
227#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
228
229/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
230#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
231#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
232#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
233#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
234
235/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
236#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
237#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
238#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
239#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
240
241/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
242#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
243#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
244#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
245#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
246
247/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
248#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
249#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
250#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
251#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
252
253/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
254#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
255#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
256#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
257#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
258
259/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
260#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
261#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
262#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
263#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
264
265/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
266#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
267#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
268#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
269#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
270
271/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
272#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
273#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
274#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
275#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
276
277/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
278#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
279#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
280#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
281#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
282
283/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
284#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
285#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
286#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
287#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
288
289/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
290#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
291#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
292#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
293#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
294
295/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
296#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
297#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
298#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
299#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
300
301/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
302#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
303#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
304#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
305#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
306
307/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
308#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
309#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
310#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
311#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
312
313/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
314#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
315#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
316#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
317#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
318
319/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
320#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
321#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
322#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
323#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
324
325/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
326#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
327#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
328#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
329#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
330
331/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
332#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
333#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
334#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
335#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
336
337/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
338#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
339#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
340#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
341#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
342
343/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
344#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
345#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
346#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
347#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
348
349/* Register: BPROT_CONFIG1 */
350/* Description: Block protect configuration register 1 */
351
352/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
353#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
354#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
355#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
356#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
357
358/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
359#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
360#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
361#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
362#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
363
364/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
365#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
366#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
367#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
368#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
369
370/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
371#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
372#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
373#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
374#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
375
376/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
377#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
378#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
379#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
380#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
381
382/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
383#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
384#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
385#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
386#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
387
388/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
389#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
390#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
391#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
392#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
393
394/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
395#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
396#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
397#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
398#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
399
400/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
401#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
402#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
403#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
404#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
405
406/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
407#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
408#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
409#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
410#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
411
412/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
413#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
414#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
415#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
416#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
417
418/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
419#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
420#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
421#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
422#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
423
424/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
425#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
426#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
427#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
428#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
429
430/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
431#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
432#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
433#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
434#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
435
436/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
437#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
438#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
439#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
440#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
441
442/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
443#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
444#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
445#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
446#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
447
448/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
449#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
450#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
451#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
452#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
453
454/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
455#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
456#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
457#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
458#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
459
460/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
461#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
462#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
463#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
464#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
465
466/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
467#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
468#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
469#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
470#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
471
472/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
473#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
474#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
475#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
476#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
477
478/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
479#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
480#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
481#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
482#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
483
484/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
485#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
486#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
487#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
488#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
489
490/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
491#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
492#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
493#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
494#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
495
496/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
497#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
498#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
499#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
500#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
501
502/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
503#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
504#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
505#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
506#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
507
508/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
509#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
510#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
511#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
512#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
513
514/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
515#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
516#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
517#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
518#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
519
520/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
521#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
522#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
523#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
524#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
525
526/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
527#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
528#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
529#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
530#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
531
532/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
533#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
534#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
535#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
536#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
537
538/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
539#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
540#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
541#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
542#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
543
544/* Register: BPROT_DISABLEINDEBUG */
545/* Description: Disable protection mechanism in debug interface mode */
546
547/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
548#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
549#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
550#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
551#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
552
553/* Register: BPROT_CONFIG2 */
554/* Description: Block protect configuration register 2 */
555
556/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
557#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
558#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
559#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
560#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
561
562/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
563#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
564#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
565#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
566#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
567
568/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
569#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
570#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
571#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
572#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
573
574/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
575#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
576#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
577#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
578#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
579
580/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
581#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
582#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
583#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
584#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
585
586/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
587#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
588#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
589#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
590#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
591
592/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
593#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
594#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
595#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
596#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
597
598/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
599#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
600#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
601#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
602#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
603
604/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
605#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
606#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
607#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
608#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
609
610/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
611#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
612#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
613#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
614#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
615
616/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
617#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
618#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
619#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
620#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
621
622/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
623#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
624#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
625#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
626#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
627
628/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
629#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
630#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
631#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
632#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
633
634/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
635#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
636#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
637#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
638#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
639
640/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
641#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
642#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
643#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
644#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
645
646/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
647#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
648#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
649#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
650#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
651
652/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
653#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
654#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
655#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
656#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
657
658/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
659#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
660#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
661#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
662#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
663
664/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
665#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
666#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
667#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
668#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
669
670/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
671#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
672#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
673#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
674#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
675
676/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
677#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
678#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
679#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
680#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
681
682/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
683#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
684#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
685#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
686#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
687
688/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
689#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
690#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
691#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
692#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
693
694/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
695#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
696#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
697#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
698#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
699
700/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
701#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
702#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
703#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
704#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
705
706/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
707#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
708#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
709#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
710#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
711
712/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
713#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
714#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
715#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
716#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
717
718/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
719#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
720#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
721#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
722#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
723
724/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
725#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
726#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
727#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
728#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
729
730/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
731#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
732#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
733#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
734#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
735
736/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
737#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
738#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
739#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
740#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
741
742/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
743#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
744#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
745#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
746#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
747
748/* Register: BPROT_CONFIG3 */
749/* Description: Block protect configuration register 3 */
750
751/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
752#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
753#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
754#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
755#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
756
757/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
758#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
759#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
760#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
761#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
762
763/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
764#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
765#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
766#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
767#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
768
769/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
770#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
771#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
772#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
773#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
774
775/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
776#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
777#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
778#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
779#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
780
781/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
782#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
783#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
784#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
785#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
786
787/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
788#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
789#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
790#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
791#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
792
793/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
794#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
795#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
796#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
797#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
798
799/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
800#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
801#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
802#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
803#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
804
805/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
806#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
807#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
808#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
809#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
810
811/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
812#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
813#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
814#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
815#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
816
817/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
818#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
819#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
820#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
821#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
822
823/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
824#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
825#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
826#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
827#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
828
829/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
830#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
831#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
832#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
833#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
834
835/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
836#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
837#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
838#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
839#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
840
841/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
842#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
843#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
844#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
845#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
846
847/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
848#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
849#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
850#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
851#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
852
853/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
854#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
855#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
856#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
857#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
858
859/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
860#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
861#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
862#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
863#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
864
865/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
866#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
867#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
868#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
869#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
870
871/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
872#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
873#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
874#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
875#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
876
877/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
878#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
879#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
880#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
881#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
882
883/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
884#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
885#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
886#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
887#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
888
889/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
890#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
891#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
892#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
893#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
894
895/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
896#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
897#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
898#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
899#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
900
901/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
902#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
903#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
904#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
905#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
906
907/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
908#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
909#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
910#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
911#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
912
913/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
914#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
915#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
916#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
917#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
918
919/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
920#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
921#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
922#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
923#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
924
925/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
926#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
927#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
928#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
929#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
930
931/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
932#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
933#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
934#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
935#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
936
937/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
938#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
939#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
940#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
941#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
942
943
944/* Peripheral: CCM */
945/* Description: AES CCM Mode Encryption */
946
947/* Register: CCM_SHORTS */
948/* Description: Shortcut register */
949
950/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
951#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
952#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
953#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
954#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
955
956/* Register: CCM_INTENSET */
957/* Description: Enable interrupt */
958
959/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
960#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
961#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
962#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
963#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
964#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
965
966/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
967#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
968#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
969#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
970#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
971#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
972
973/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
974#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
975#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
976#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
977#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
978#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
979
980/* Register: CCM_INTENCLR */
981/* Description: Disable interrupt */
982
983/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
984#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
985#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
986#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
987#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
988#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
989
990/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
991#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
992#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
993#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
994#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
995#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
996
997/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
998#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
999#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
1000#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
1001#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
1002#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
1003
1004/* Register: CCM_MICSTATUS */
1005/* Description: MIC check result */
1006
1007/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
1008#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
1009#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
1010#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
1011#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
1012
1013/* Register: CCM_ENABLE */
1014/* Description: Enable */
1015
1016/* Bits 1..0 : Enable or disable CCM */
1017#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1018#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1019#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1020#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1021
1022/* Register: CCM_MODE */
1023/* Description: Operation mode */
1024
1025/* Bit 24 : Packet length configuration */
1026#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
1027#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
1028#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
1029#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
1030
1031/* Bit 16 : Data rate that the CCM shall run in synch with */
1032#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
1033#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
1034#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
1035#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
1036
1037/* Bit 0 : The mode of operation to be used */
1038#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
1039#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
1040#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
1041#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
1042
1043/* Register: CCM_CNFPTR */
1044/* Description: Pointer to data structure holding AES key and NONCE vector */
1045
1046/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
1047#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
1048#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
1049
1050/* Register: CCM_INPTR */
1051/* Description: Input pointer */
1052
1053/* Bits 31..0 : Input pointer */
1054#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
1055#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
1056
1057/* Register: CCM_OUTPTR */
1058/* Description: Output pointer */
1059
1060/* Bits 31..0 : Output pointer */
1061#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
1062#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
1063
1064/* Register: CCM_SCRATCHPTR */
1065/* Description: Pointer to data area used for temporary storage */
1066
1067/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
1068#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
1069#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
1070
1071
1072/* Peripheral: CLOCK */
1073/* Description: Clock control */
1074
1075/* Register: CLOCK_INTENSET */
1076/* Description: Enable interrupt */
1077
1078/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
1079#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1080#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
1081#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
1082#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
1083#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
1084
1085/* Bit 3 : Write '1' to Enable interrupt for DONE event */
1086#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
1087#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
1088#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
1089#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
1090#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
1091
1092/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
1093#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1094#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1095#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1096#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1097#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
1098
1099/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
1100#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1101#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1102#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1103#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1104#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
1105
1106/* Register: CLOCK_INTENCLR */
1107/* Description: Disable interrupt */
1108
1109/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
1110#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
1111#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
1112#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
1113#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
1114#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
1115
1116/* Bit 3 : Write '1' to Disable interrupt for DONE event */
1117#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
1118#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
1119#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
1120#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
1121#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
1122
1123/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
1124#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
1125#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
1126#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1127#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1128#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
1129
1130/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
1131#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
1132#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
1133#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
1134#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
1135#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
1136
1137/* Register: CLOCK_HFCLKRUN */
1138/* Description: Status indicating that HFCLKSTART task has been triggered */
1139
1140/* Bit 0 : HFCLKSTART task triggered or not */
1141#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1142#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1143#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1144#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1145
1146/* Register: CLOCK_HFCLKSTAT */
1147/* Description: HFCLK status */
1148
1149/* Bit 16 : HFCLK state */
1150#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1151#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1152#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
1153#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
1154
1155/* Bit 0 : Source of HFCLK */
1156#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1157#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1158#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
1159#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
1160
1161/* Register: CLOCK_LFCLKRUN */
1162/* Description: Status indicating that LFCLKSTART task has been triggered */
1163
1164/* Bit 0 : LFCLKSTART task triggered or not */
1165#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
1166#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
1167#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
1168#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
1169
1170/* Register: CLOCK_LFCLKSTAT */
1171/* Description: LFCLK status */
1172
1173/* Bit 16 : LFCLK state */
1174#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
1175#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
1176#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
1177#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
1178
1179/* Bits 1..0 : Source of LFCLK */
1180#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
1181#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
1182#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1183#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1184#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1185
1186/* Register: CLOCK_LFCLKSRCCOPY */
1187/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
1188
1189/* Bits 1..0 : Clock source */
1190#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
1191#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
1192#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1193#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1194#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1195
1196/* Register: CLOCK_LFCLKSRC */
1197/* Description: Clock source for the LFCLK */
1198
1199/* Bit 17 : Enable or disable external source for LFCLK */
1200#define CLOCK_LFCLKSRC_EXTERNAL_Pos (17UL) /*!< Position of EXTERNAL field. */
1201#define CLOCK_LFCLKSRC_EXTERNAL_Msk (0x1UL << CLOCK_LFCLKSRC_EXTERNAL_Pos) /*!< Bit mask of EXTERNAL field. */
1202#define CLOCK_LFCLKSRC_EXTERNAL_Disabled (0UL) /*!< Disable external source (use with Xtal) */
1203#define CLOCK_LFCLKSRC_EXTERNAL_Enabled (1UL) /*!< Enable use of external source instead of Xtal (SRC needs to be set to Xtal) */
1204
1205/* Bit 16 : Enable or disable bypass of LFCLK crystal oscillator with external clock source */
1206#define CLOCK_LFCLKSRC_BYPASS_Pos (16UL) /*!< Position of BYPASS field. */
1207#define CLOCK_LFCLKSRC_BYPASS_Msk (0x1UL << CLOCK_LFCLKSRC_BYPASS_Pos) /*!< Bit mask of BYPASS field. */
1208#define CLOCK_LFCLKSRC_BYPASS_Disabled (0UL) /*!< Disable (use with Xtal or low-swing external source) */
1209#define CLOCK_LFCLKSRC_BYPASS_Enabled (1UL) /*!< Enable (use with rail-to-rail external source) */
1210
1211/* Bits 1..0 : Clock source */
1212#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
1213#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
1214#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
1215#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
1216#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
1217
1218/* Register: CLOCK_CTIV */
1219/* Description: Calibration timer interval */
1220
1221/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
1222#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
1223#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
1224
1225/* Register: CLOCK_TRACECONFIG */
1226/* Description: Clocking options for the Trace Port debug interface */
1227
1228/* Bits 17..16 : Pin multiplexing of trace signals. */
1229#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
1230#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
1231#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
1232#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
1233#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
1234
1235/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
1236#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
1237#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
1238#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
1239#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
1240#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
1241#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
1242
1243
1244/* Peripheral: COMP */
1245/* Description: Comparator */
1246
1247/* Register: COMP_SHORTS */
1248/* Description: Shortcut register */
1249
1250/* Bit 4 : Shortcut between CROSS event and STOP task */
1251#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
1252#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
1253#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
1254#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
1255
1256/* Bit 3 : Shortcut between UP event and STOP task */
1257#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
1258#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
1259#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
1260#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
1261
1262/* Bit 2 : Shortcut between DOWN event and STOP task */
1263#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
1264#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
1265#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
1266#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
1267
1268/* Bit 1 : Shortcut between READY event and STOP task */
1269#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
1270#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
1271#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
1272#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
1273
1274/* Bit 0 : Shortcut between READY event and SAMPLE task */
1275#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
1276#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
1277#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
1278#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
1279
1280/* Register: COMP_INTEN */
1281/* Description: Enable or disable interrupt */
1282
1283/* Bit 3 : Enable or disable interrupt for CROSS event */
1284#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1285#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
1286#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
1287#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
1288
1289/* Bit 2 : Enable or disable interrupt for UP event */
1290#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
1291#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
1292#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
1293#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
1294
1295/* Bit 1 : Enable or disable interrupt for DOWN event */
1296#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1297#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
1298#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
1299#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
1300
1301/* Bit 0 : Enable or disable interrupt for READY event */
1302#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
1303#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
1304#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
1305#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
1306
1307/* Register: COMP_INTENSET */
1308/* Description: Enable interrupt */
1309
1310/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
1311#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1312#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
1313#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
1314#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
1315#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
1316
1317/* Bit 2 : Write '1' to Enable interrupt for UP event */
1318#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
1319#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
1320#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
1321#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
1322#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
1323
1324/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
1325#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1326#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
1327#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
1328#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
1329#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
1330
1331/* Bit 0 : Write '1' to Enable interrupt for READY event */
1332#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
1333#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
1334#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
1335#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
1336#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
1337
1338/* Register: COMP_INTENCLR */
1339/* Description: Disable interrupt */
1340
1341/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
1342#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
1343#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
1344#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
1345#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
1346#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
1347
1348/* Bit 2 : Write '1' to Disable interrupt for UP event */
1349#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
1350#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
1351#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
1352#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
1353#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
1354
1355/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
1356#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
1357#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
1358#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
1359#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
1360#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
1361
1362/* Bit 0 : Write '1' to Disable interrupt for READY event */
1363#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
1364#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
1365#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
1366#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
1367#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
1368
1369/* Register: COMP_RESULT */
1370/* Description: Compare result */
1371
1372/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
1373#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
1374#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
1375#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
1376#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
1377
1378/* Register: COMP_ENABLE */
1379/* Description: COMP enable */
1380
1381/* Bits 1..0 : Enable or disable COMP */
1382#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
1383#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
1384#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
1385#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
1386
1387/* Register: COMP_PSEL */
1388/* Description: Pin select */
1389
1390/* Bits 2..0 : Analog pin select */
1391#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
1392#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
1393#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
1394#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
1395#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
1396#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
1397#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
1398#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
1399#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
1400#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
1401
1402/* Register: COMP_REFSEL */
1403/* Description: Reference source select for single-ended mode */
1404
1405/* Bits 2..0 : Reference select */
1406#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
1407#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
1408#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
1409#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
1410#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
1411#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
1412#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
1413
1414/* Register: COMP_EXTREFSEL */
1415/* Description: External reference select */
1416
1417/* Bits 2..0 : External analog reference select */
1418#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
1419#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x7UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
1420#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
1421#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
1422#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference2 (2UL) /*!< Use AIN2 as external analog reference */
1423#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference3 (3UL) /*!< Use AIN3 as external analog reference */
1424#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference4 (4UL) /*!< Use AIN4 as external analog reference */
1425#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference5 (5UL) /*!< Use AIN5 as external analog reference */
1426#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference6 (6UL) /*!< Use AIN6 as external analog reference */
1427#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference7 (7UL) /*!< Use AIN7 as external analog reference */
1428
1429/* Register: COMP_TH */
1430/* Description: Threshold configuration for hysteresis unit */
1431
1432/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
1433#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
1434#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
1435
1436/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
1437#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
1438#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
1439
1440/* Register: COMP_MODE */
1441/* Description: Mode configuration */
1442
1443/* Bit 8 : Main operation modes */
1444#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
1445#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
1446#define COMP_MODE_MAIN_SE (0UL) /*!< Single-ended mode */
1447#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
1448
1449/* Bits 1..0 : Speed and power modes */
1450#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
1451#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
1452#define COMP_MODE_SP_Low (0UL) /*!< Low-power mode */
1453#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
1454#define COMP_MODE_SP_High (2UL) /*!< High-speed mode */
1455
1456/* Register: COMP_HYST */
1457/* Description: Comparator hysteresis enable */
1458
1459/* Bit 0 : Comparator hysteresis */
1460#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
1461#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
1462#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
1463#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
1464
1465/* Register: COMP_ISOURCE */
1466/* Description: Current source select on analog input */
1467
1468/* Bits 1..0 : Comparator hysteresis */
1469#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
1470#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
1471#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
1472#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
1473#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
1474#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
1475
1476
1477/* Peripheral: ECB */
1478/* Description: AES ECB Mode Encryption */
1479
1480/* Register: ECB_INTENSET */
1481/* Description: Enable interrupt */
1482
1483/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
1484#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1485#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1486#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1487#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1488#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
1489
1490/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
1491#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1492#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1493#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1494#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1495#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
1496
1497/* Register: ECB_INTENCLR */
1498/* Description: Disable interrupt */
1499
1500/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
1501#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
1502#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
1503#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
1504#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
1505#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
1506
1507/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
1508#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
1509#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
1510#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
1511#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
1512#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
1513
1514/* Register: ECB_ECBDATAPTR */
1515/* Description: ECB block encrypt memory pointers */
1516
1517/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
1518#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
1519#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
1520
1521
1522/* Peripheral: EGU */
1523/* Description: Event Generator Unit 0 */
1524
1525/* Register: EGU_INTEN */
1526/* Description: Enable or disable interrupt */
1527
1528/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
1529#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1530#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1531#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
1532#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
1533
1534/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
1535#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1536#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1537#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
1538#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
1539
1540/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
1541#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1542#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1543#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
1544#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
1545
1546/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
1547#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1548#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1549#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
1550#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
1551
1552/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
1553#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1554#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1555#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
1556#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
1557
1558/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
1559#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1560#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1561#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
1562#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
1563
1564/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
1565#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1566#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1567#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
1568#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
1569
1570/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
1571#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1572#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1573#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
1574#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
1575
1576/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
1577#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1578#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1579#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
1580#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
1581
1582/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
1583#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1584#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1585#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
1586#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
1587
1588/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
1589#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1590#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1591#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
1592#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
1593
1594/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
1595#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1596#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1597#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
1598#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
1599
1600/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
1601#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1602#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1603#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
1604#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
1605
1606/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
1607#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1608#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1609#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
1610#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
1611
1612/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
1613#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1614#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1615#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
1616#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
1617
1618/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
1619#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1620#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1621#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
1622#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
1623
1624/* Register: EGU_INTENSET */
1625/* Description: Enable interrupt */
1626
1627/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
1628#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1629#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1630#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1631#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1632#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
1633
1634/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
1635#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1636#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1637#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1638#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1639#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
1640
1641/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
1642#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1643#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1644#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1645#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1646#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
1647
1648/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
1649#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1650#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1651#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1652#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1653#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
1654
1655/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
1656#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1657#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1658#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1659#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1660#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
1661
1662/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
1663#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1664#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1665#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1666#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1667#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
1668
1669/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
1670#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1671#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1672#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1673#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1674#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
1675
1676/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
1677#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1678#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1679#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1680#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1681#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
1682
1683/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
1684#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1685#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1686#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1687#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1688#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
1689
1690/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
1691#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1692#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1693#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1694#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1695#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
1696
1697/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
1698#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1699#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1700#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1701#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1702#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
1703
1704/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
1705#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1706#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1707#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1708#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1709#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
1710
1711/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
1712#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1713#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1714#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1715#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1716#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
1717
1718/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
1719#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1720#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1721#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1722#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1723#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
1724
1725/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
1726#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1727#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1728#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1729#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1730#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
1731
1732/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
1733#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1734#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1735#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1736#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1737#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
1738
1739/* Register: EGU_INTENCLR */
1740/* Description: Disable interrupt */
1741
1742/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
1743#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
1744#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
1745#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
1746#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
1747#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
1748
1749/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
1750#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
1751#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
1752#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
1753#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
1754#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
1755
1756/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
1757#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
1758#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
1759#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
1760#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
1761#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
1762
1763/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
1764#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
1765#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
1766#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
1767#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
1768#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
1769
1770/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
1771#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
1772#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
1773#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
1774#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
1775#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
1776
1777/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
1778#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
1779#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
1780#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
1781#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
1782#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
1783
1784/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
1785#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
1786#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
1787#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
1788#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
1789#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
1790
1791/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
1792#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
1793#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
1794#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
1795#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
1796#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
1797
1798/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
1799#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
1800#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
1801#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
1802#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
1803#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
1804
1805/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
1806#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
1807#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
1808#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
1809#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
1810#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
1811
1812/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
1813#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
1814#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
1815#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
1816#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
1817#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
1818
1819/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
1820#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
1821#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
1822#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
1823#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
1824#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
1825
1826/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
1827#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
1828#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
1829#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
1830#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
1831#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
1832
1833/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
1834#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
1835#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
1836#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
1837#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
1838#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
1839
1840/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
1841#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
1842#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
1843#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
1844#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
1845#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
1846
1847/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
1848#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
1849#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
1850#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
1851#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
1852#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
1853
1854
1855/* Peripheral: FICR */
1856/* Description: Factory Information Configuration Registers */
1857
1858/* Register: FICR_CODEPAGESIZE */
1859/* Description: Code memory page size */
1860
1861/* Bits 31..0 : Code memory page size */
1862#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
1863#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
1864
1865/* Register: FICR_CODESIZE */
1866/* Description: Code memory size */
1867
1868/* Bits 31..0 : Code memory size in number of pages */
1869#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
1870#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
1871
1872/* Register: FICR_DEVICEID */
1873/* Description: Description collection[0]: Device identifier */
1874
1875/* Bits 31..0 : 64 bit unique device identifier */
1876#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
1877#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
1878
1879/* Register: FICR_ER */
1880/* Description: Description collection[0]: Encryption Root, word 0 */
1881
1882/* Bits 31..0 : Encryption Root, word n */
1883#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
1884#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
1885
1886/* Register: FICR_IR */
1887/* Description: Description collection[0]: Identity Root, word 0 */
1888
1889/* Bits 31..0 : Identity Root, word n */
1890#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
1891#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
1892
1893/* Register: FICR_DEVICEADDRTYPE */
1894/* Description: Device address type */
1895
1896/* Bit 0 : Device address type */
1897#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
1898#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
1899#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
1900#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
1901
1902/* Register: FICR_DEVICEADDR */
1903/* Description: Description collection[0]: Device address 0 */
1904
1905/* Bits 31..0 : 48 bit device address */
1906#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
1907#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
1908
1909/* Register: FICR_INFO_PART */
1910/* Description: Part code */
1911
1912/* Bits 31..0 : Part code */
1913#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
1914#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
1915#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
1916#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1917
1918/* Register: FICR_INFO_VARIANT */
1919/* Description: Part Variant, Hardware version and Production configuration */
1920
1921/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
1922#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
1923#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
1924#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
1925#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
1926#define FICR_INFO_VARIANT_VARIANT_AAB0 (0x41414230UL) /*!< AAB0 */
1927#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
1928#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
1929#define FICR_INFO_VARIANT_VARIANT_AAE0 (0x41414530UL) /*!< AAE0 */
1930#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1931
1932/* Register: FICR_INFO_PACKAGE */
1933/* Description: Package option */
1934
1935/* Bits 31..0 : Package option */
1936#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
1937#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
1938#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
1939#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
1940#define FICR_INFO_PACKAGE_PACKAGE_CI (0x2002UL) /*!< CIxx - 7x8 WLCSP 56 balls */
1941#define FICR_INFO_PACKAGE_PACKAGE_CK (0x2005UL) /*!< CKxx - 7x8 WLCSP 56 balls with backside coating for light protection */
1942#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1943
1944/* Register: FICR_INFO_RAM */
1945/* Description: RAM variant */
1946
1947/* Bits 31..0 : RAM variant */
1948#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
1949#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
1950#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
1951#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
1952#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
1953#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1954
1955/* Register: FICR_INFO_FLASH */
1956/* Description: Flash variant */
1957
1958/* Bits 31..0 : Flash variant */
1959#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
1960#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
1961#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
1962#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
1963#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
1964#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
1965
1966/* Register: FICR_TEMP_A0 */
1967/* Description: Slope definition A0. */
1968
1969/* Bits 11..0 : A (slope definition) register. */
1970#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
1971#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
1972
1973/* Register: FICR_TEMP_A1 */
1974/* Description: Slope definition A1. */
1975
1976/* Bits 11..0 : A (slope definition) register. */
1977#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
1978#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
1979
1980/* Register: FICR_TEMP_A2 */
1981/* Description: Slope definition A2. */
1982
1983/* Bits 11..0 : A (slope definition) register. */
1984#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
1985#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
1986
1987/* Register: FICR_TEMP_A3 */
1988/* Description: Slope definition A3. */
1989
1990/* Bits 11..0 : A (slope definition) register. */
1991#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
1992#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
1993
1994/* Register: FICR_TEMP_A4 */
1995/* Description: Slope definition A4. */
1996
1997/* Bits 11..0 : A (slope definition) register. */
1998#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
1999#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
2000
2001/* Register: FICR_TEMP_A5 */
2002/* Description: Slope definition A5. */
2003
2004/* Bits 11..0 : A (slope definition) register. */
2005#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
2006#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
2007
2008/* Register: FICR_TEMP_B0 */
2009/* Description: y-intercept B0. */
2010
2011/* Bits 13..0 : B (y-intercept) */
2012#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
2013#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
2014
2015/* Register: FICR_TEMP_B1 */
2016/* Description: y-intercept B1. */
2017
2018/* Bits 13..0 : B (y-intercept) */
2019#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
2020#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
2021
2022/* Register: FICR_TEMP_B2 */
2023/* Description: y-intercept B2. */
2024
2025/* Bits 13..0 : B (y-intercept) */
2026#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
2027#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
2028
2029/* Register: FICR_TEMP_B3 */
2030/* Description: y-intercept B3. */
2031
2032/* Bits 13..0 : B (y-intercept) */
2033#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
2034#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
2035
2036/* Register: FICR_TEMP_B4 */
2037/* Description: y-intercept B4. */
2038
2039/* Bits 13..0 : B (y-intercept) */
2040#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
2041#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
2042
2043/* Register: FICR_TEMP_B5 */
2044/* Description: y-intercept B5. */
2045
2046/* Bits 13..0 : B (y-intercept) */
2047#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
2048#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
2049
2050/* Register: FICR_TEMP_T0 */
2051/* Description: Segment end T0. */
2052
2053/* Bits 7..0 : T (segment end)register. */
2054#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
2055#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
2056
2057/* Register: FICR_TEMP_T1 */
2058/* Description: Segment end T1. */
2059
2060/* Bits 7..0 : T (segment end)register. */
2061#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
2062#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
2063
2064/* Register: FICR_TEMP_T2 */
2065/* Description: Segment end T2. */
2066
2067/* Bits 7..0 : T (segment end)register. */
2068#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
2069#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
2070
2071/* Register: FICR_TEMP_T3 */
2072/* Description: Segment end T3. */
2073
2074/* Bits 7..0 : T (segment end)register. */
2075#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
2076#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
2077
2078/* Register: FICR_TEMP_T4 */
2079/* Description: Segment end T4. */
2080
2081/* Bits 7..0 : T (segment end)register. */
2082#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
2083#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
2084
2085/* Register: FICR_NFC_TAGHEADER0 */
2086/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2087
2088/* Bits 31..24 : Unique identifier byte 3 */
2089#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
2090#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
2091
2092/* Bits 23..16 : Unique identifier byte 2 */
2093#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
2094#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
2095
2096/* Bits 15..8 : Unique identifier byte 1 */
2097#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
2098#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
2099
2100/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
2101#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
2102#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
2103
2104/* Register: FICR_NFC_TAGHEADER1 */
2105/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2106
2107/* Bits 31..24 : Unique identifier byte 7 */
2108#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
2109#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
2110
2111/* Bits 23..16 : Unique identifier byte 6 */
2112#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
2113#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
2114
2115/* Bits 15..8 : Unique identifier byte 5 */
2116#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
2117#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
2118
2119/* Bits 7..0 : Unique identifier byte 4 */
2120#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
2121#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
2122
2123/* Register: FICR_NFC_TAGHEADER2 */
2124/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2125
2126/* Bits 31..24 : Unique identifier byte 11 */
2127#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
2128#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
2129
2130/* Bits 23..16 : Unique identifier byte 10 */
2131#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
2132#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
2133
2134/* Bits 15..8 : Unique identifier byte 9 */
2135#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
2136#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
2137
2138/* Bits 7..0 : Unique identifier byte 8 */
2139#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
2140#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
2141
2142/* Register: FICR_NFC_TAGHEADER3 */
2143/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
2144
2145/* Bits 31..24 : Unique identifier byte 15 */
2146#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
2147#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
2148
2149/* Bits 23..16 : Unique identifier byte 14 */
2150#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
2151#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
2152
2153/* Bits 15..8 : Unique identifier byte 13 */
2154#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
2155#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
2156
2157/* Bits 7..0 : Unique identifier byte 12 */
2158#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
2159#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
2160
2161
2162/* Peripheral: GPIOTE */
2163/* Description: GPIO Tasks and Events */
2164
2165/* Register: GPIOTE_INTENSET */
2166/* Description: Enable interrupt */
2167
2168/* Bit 31 : Write '1' to Enable interrupt for PORT event */
2169#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
2170#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
2171#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
2172#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
2173#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
2174
2175/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
2176#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
2177#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
2178#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
2179#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
2180#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
2181
2182/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
2183#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
2184#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
2185#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
2186#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
2187#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
2188
2189/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
2190#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
2191#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
2192#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
2193#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
2194#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
2195
2196/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
2197#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
2198#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
2199#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
2200#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
2201#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
2202
2203/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
2204#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
2205#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
2206#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
2207#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
2208#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
2209
2210/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
2211#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
2212#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
2213#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
2214#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
2215#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
2216
2217/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
2218#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
2219#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
2220#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
2221#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
2222#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
2223
2224/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
2225#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
2226#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
2227#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
2228#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
2229#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
2230
2231/* Register: GPIOTE_INTENCLR */
2232/* Description: Disable interrupt */
2233
2234/* Bit 31 : Write '1' to Disable interrupt for PORT event */
2235#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
2236#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
2237#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
2238#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
2239#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
2240
2241/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
2242#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
2243#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
2244#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
2245#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
2246#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
2247
2248/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
2249#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
2250#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
2251#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
2252#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
2253#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
2254
2255/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
2256#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
2257#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
2258#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
2259#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
2260#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
2261
2262/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
2263#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
2264#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
2265#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
2266#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
2267#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
2268
2269/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
2270#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
2271#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
2272#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
2273#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
2274#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
2275
2276/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
2277#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
2278#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
2279#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
2280#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
2281#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
2282
2283/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
2284#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
2285#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
2286#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
2287#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
2288#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
2289
2290/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
2291#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
2292#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
2293#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
2294#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
2295#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
2296
2297/* Register: GPIOTE_CONFIG */
2298/* Description: Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
2299
2300/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
2301#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
2302#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
2303#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
2304#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
2305
2306/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
2307#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
2308#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
2309#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
2310#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
2311#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
2312#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
2313
2314/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
2315#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
2316#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
2317
2318/* Bits 1..0 : Mode */
2319#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
2320#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
2321#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
2322#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
2323#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
2324
2325
2326/* Peripheral: I2S */
2327/* Description: Inter-IC Sound */
2328
2329/* Register: I2S_INTEN */
2330/* Description: Enable or disable interrupt */
2331
2332/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
2333#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2334#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2335#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
2336#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
2337
2338/* Bit 2 : Enable or disable interrupt for STOPPED event */
2339#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2340#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2341#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
2342#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
2343
2344/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
2345#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2346#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2347#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
2348#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
2349
2350/* Register: I2S_INTENSET */
2351/* Description: Enable interrupt */
2352
2353/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
2354#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2355#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2356#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2357#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2358#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
2359
2360/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
2361#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2362#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2363#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2364#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2365#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
2366
2367/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
2368#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2369#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2370#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2371#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2372#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
2373
2374/* Register: I2S_INTENCLR */
2375/* Description: Disable interrupt */
2376
2377/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
2378#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
2379#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
2380#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2381#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2382#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
2383
2384/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
2385#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
2386#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
2387#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
2388#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
2389#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
2390
2391/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
2392#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
2393#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
2394#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
2395#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
2396#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
2397
2398/* Register: I2S_ENABLE */
2399/* Description: Enable I2S module. */
2400
2401/* Bit 0 : Enable I2S module. */
2402#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2403#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2404#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2405#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2406
2407/* Register: I2S_CONFIG_MODE */
2408/* Description: I2S mode. */
2409
2410/* Bit 0 : I2S mode. */
2411#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
2412#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
2413#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
2414#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
2415
2416/* Register: I2S_CONFIG_RXEN */
2417/* Description: Reception (RX) enable. */
2418
2419/* Bit 0 : Reception (RX) enable. */
2420#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
2421#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
2422#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
2423#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
2424
2425/* Register: I2S_CONFIG_TXEN */
2426/* Description: Transmission (TX) enable. */
2427
2428/* Bit 0 : Transmission (TX) enable. */
2429#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
2430#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
2431#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
2432#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
2433
2434/* Register: I2S_CONFIG_MCKEN */
2435/* Description: Master clock generator enable. */
2436
2437/* Bit 0 : Master clock generator enable. */
2438#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
2439#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
2440#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
2441#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
2442
2443/* Register: I2S_CONFIG_MCKFREQ */
2444/* Description: Master clock generator frequency. */
2445
2446/* Bits 31..0 : Master clock generator frequency. */
2447#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
2448#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
2449#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
2450#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
2451#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
2452#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
2453#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
2454#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
2455#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
2456#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
2457#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
2458#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
2459#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
2460#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
2461#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
2462#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
2463#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
2464#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
2465#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
2466#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
2467
2468/* Register: I2S_CONFIG_RATIO */
2469/* Description: MCK / LRCK ratio. */
2470
2471/* Bits 3..0 : MCK / LRCK ratio. */
2472#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
2473#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
2474#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
2475#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
2476#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
2477#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
2478#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
2479#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
2480#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
2481#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
2482#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
2483
2484/* Register: I2S_CONFIG_SWIDTH */
2485/* Description: Sample width. */
2486
2487/* Bits 1..0 : Sample width. */
2488#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
2489#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
2490#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
2491#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
2492#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
2493
2494/* Register: I2S_CONFIG_ALIGN */
2495/* Description: Alignment of sample within a frame. */
2496
2497/* Bit 0 : Alignment of sample within a frame. */
2498#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
2499#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
2500#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
2501#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
2502
2503/* Register: I2S_CONFIG_FORMAT */
2504/* Description: Frame format. */
2505
2506/* Bit 0 : Frame format. */
2507#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
2508#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
2509#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
2510#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
2511
2512/* Register: I2S_CONFIG_CHANNELS */
2513/* Description: Enable channels. */
2514
2515/* Bits 1..0 : Enable channels. */
2516#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
2517#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
2518#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
2519#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
2520#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
2521
2522/* Register: I2S_RXD_PTR */
2523/* Description: Receive buffer RAM start address. */
2524
2525/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
2526#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2527#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2528
2529/* Register: I2S_TXD_PTR */
2530/* Description: Transmit buffer RAM start address. */
2531
2532/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
2533#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
2534#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
2535
2536/* Register: I2S_RXTXD_MAXCNT */
2537/* Description: Size of RXD and TXD buffers. */
2538
2539/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
2540#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
2541#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
2542
2543/* Register: I2S_PSEL_MCK */
2544/* Description: Pin select for MCK signal. */
2545
2546/* Bit 31 : Connection */
2547#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2548#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2549#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
2550#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2551
2552/* Bits 4..0 : Pin number */
2553#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2554#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
2555
2556/* Register: I2S_PSEL_SCK */
2557/* Description: Pin select for SCK signal. */
2558
2559/* Bit 31 : Connection */
2560#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2561#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2562#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
2563#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2564
2565/* Bits 4..0 : Pin number */
2566#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2567#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
2568
2569/* Register: I2S_PSEL_LRCK */
2570/* Description: Pin select for LRCK signal. */
2571
2572/* Bit 31 : Connection */
2573#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2574#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2575#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
2576#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
2577
2578/* Bits 4..0 : Pin number */
2579#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
2580#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
2581
2582/* Register: I2S_PSEL_SDIN */
2583/* Description: Pin select for SDIN signal. */
2584
2585/* Bit 31 : Connection */
2586#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2587#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2588#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
2589#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
2590
2591/* Bits 4..0 : Pin number */
2592#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
2593#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
2594
2595/* Register: I2S_PSEL_SDOUT */
2596/* Description: Pin select for SDOUT signal. */
2597
2598/* Bit 31 : Connection */
2599#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
2600#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
2601#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
2602#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
2603
2604/* Bits 4..0 : Pin number */
2605#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
2606#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
2607
2608
2609/* Peripheral: LPCOMP */
2610/* Description: Low Power Comparator */
2611
2612/* Register: LPCOMP_SHORTS */
2613/* Description: Shortcut register */
2614
2615/* Bit 4 : Shortcut between CROSS event and STOP task */
2616#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
2617#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
2618#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
2619#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
2620
2621/* Bit 3 : Shortcut between UP event and STOP task */
2622#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
2623#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
2624#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
2625#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
2626
2627/* Bit 2 : Shortcut between DOWN event and STOP task */
2628#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
2629#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
2630#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
2631#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
2632
2633/* Bit 1 : Shortcut between READY event and STOP task */
2634#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
2635#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
2636#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
2637#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
2638
2639/* Bit 0 : Shortcut between READY event and SAMPLE task */
2640#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
2641#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
2642#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
2643#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
2644
2645/* Register: LPCOMP_INTENSET */
2646/* Description: Enable interrupt */
2647
2648/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
2649#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2650#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
2651#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
2652#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
2653#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
2654
2655/* Bit 2 : Write '1' to Enable interrupt for UP event */
2656#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
2657#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
2658#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
2659#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
2660#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
2661
2662/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
2663#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2664#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
2665#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
2666#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
2667#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
2668
2669/* Bit 0 : Write '1' to Enable interrupt for READY event */
2670#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
2671#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
2672#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
2673#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
2674#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
2675
2676/* Register: LPCOMP_INTENCLR */
2677/* Description: Disable interrupt */
2678
2679/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
2680#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
2681#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
2682#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
2683#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
2684#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
2685
2686/* Bit 2 : Write '1' to Disable interrupt for UP event */
2687#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
2688#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
2689#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
2690#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
2691#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
2692
2693/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
2694#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
2695#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
2696#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
2697#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
2698#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
2699
2700/* Bit 0 : Write '1' to Disable interrupt for READY event */
2701#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
2702#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
2703#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
2704#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
2705#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
2706
2707/* Register: LPCOMP_RESULT */
2708/* Description: Compare result */
2709
2710/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
2711#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
2712#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
2713#define LPCOMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
2714#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
2715
2716/* Register: LPCOMP_ENABLE */
2717/* Description: Enable LPCOMP */
2718
2719/* Bits 1..0 : Enable or disable LPCOMP */
2720#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
2721#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
2722#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
2723#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
2724
2725/* Register: LPCOMP_PSEL */
2726/* Description: Input pin select */
2727
2728/* Bits 2..0 : Analog pin select */
2729#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
2730#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
2731#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
2732#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
2733#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
2734#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
2735#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
2736#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
2737#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
2738#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
2739
2740/* Register: LPCOMP_REFSEL */
2741/* Description: Reference select */
2742
2743/* Bits 3..0 : Reference select */
2744#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
2745#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
2746#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
2747#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
2748#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
2749#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
2750#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
2751#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
2752#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
2753#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
2754#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
2755#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
2756#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
2757#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
2758#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
2759#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
2760#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
2761#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
2762
2763/* Register: LPCOMP_EXTREFSEL */
2764/* Description: External reference select */
2765
2766/* Bit 0 : External analog reference select */
2767#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
2768#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
2769#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
2770#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
2771
2772/* Register: LPCOMP_ANADETECT */
2773/* Description: Analog detect configuration */
2774
2775/* Bits 1..0 : Analog detect configuration */
2776#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
2777#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
2778#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
2779#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
2780#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
2781
2782/* Register: LPCOMP_HYST */
2783/* Description: Comparator hysteresis enable */
2784
2785/* Bit 0 : Comparator hysteresis enable */
2786#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
2787#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
2788#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
2789#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
2790
2791
2792/* Peripheral: MWU */
2793/* Description: Memory Watch Unit */
2794
2795/* Register: MWU_INTEN */
2796/* Description: Enable or disable interrupt */
2797
2798/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
2799#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2800#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2801#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
2802#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
2803
2804/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
2805#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2806#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2807#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
2808#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
2809
2810/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
2811#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2812#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2813#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
2814#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
2815
2816/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
2817#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2818#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2819#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
2820#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
2821
2822/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
2823#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2824#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2825#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
2826#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
2827
2828/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
2829#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2830#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2831#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
2832#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
2833
2834/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
2835#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2836#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2837#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
2838#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
2839
2840/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
2841#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2842#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2843#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
2844#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
2845
2846/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
2847#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2848#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2849#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
2850#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
2851
2852/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
2853#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2854#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2855#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
2856#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
2857
2858/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
2859#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2860#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2861#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
2862#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
2863
2864/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
2865#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2866#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2867#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
2868#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
2869
2870/* Register: MWU_INTENSET */
2871/* Description: Enable interrupt */
2872
2873/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
2874#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2875#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2876#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2877#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2878#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
2879
2880/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
2881#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2882#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2883#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2884#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2885#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
2886
2887/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
2888#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2889#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2890#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2891#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2892#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
2893
2894/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
2895#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2896#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2897#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2898#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2899#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
2900
2901/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
2902#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2903#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2904#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2905#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2906#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
2907
2908/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
2909#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2910#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2911#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2912#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
2913#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
2914
2915/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
2916#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
2917#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
2918#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
2919#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
2920#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
2921
2922/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
2923#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
2924#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
2925#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
2926#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
2927#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
2928
2929/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
2930#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
2931#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
2932#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
2933#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
2934#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
2935
2936/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
2937#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
2938#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
2939#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
2940#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
2941#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
2942
2943/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
2944#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
2945#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
2946#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
2947#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
2948#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
2949
2950/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
2951#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
2952#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
2953#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
2954#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
2955#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
2956
2957/* Register: MWU_INTENCLR */
2958/* Description: Disable interrupt */
2959
2960/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
2961#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
2962#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
2963#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
2964#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
2965#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
2966
2967/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
2968#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
2969#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
2970#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
2971#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
2972#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
2973
2974/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
2975#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
2976#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
2977#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
2978#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
2979#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
2980
2981/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
2982#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
2983#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
2984#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
2985#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
2986#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
2987
2988/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
2989#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
2990#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
2991#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
2992#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
2993#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
2994
2995/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
2996#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
2997#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
2998#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
2999#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3000#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3001
3002/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
3003#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3004#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3005#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3006#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3007#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3008
3009/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
3010#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3011#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3012#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3013#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3014#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3015
3016/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
3017#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3018#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3019#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3020#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3021#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3022
3023/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
3024#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3025#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3026#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3027#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3028#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3029
3030/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
3031#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3032#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3033#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3034#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3035#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3036
3037/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
3038#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3039#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3040#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3041#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3042#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3043
3044/* Register: MWU_NMIEN */
3045/* Description: Enable or disable non-maskable interrupt */
3046
3047/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
3048#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3049#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3050#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
3051#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
3052
3053/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
3054#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3055#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3056#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
3057#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
3058
3059/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
3060#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3061#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3062#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
3063#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
3064
3065/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
3066#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3067#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3068#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
3069#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
3070
3071/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
3072#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3073#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3074#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
3075#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
3076
3077/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
3078#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3079#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3080#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
3081#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
3082
3083/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
3084#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3085#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3086#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
3087#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
3088
3089/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
3090#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3091#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3092#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
3093#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
3094
3095/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
3096#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3097#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3098#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
3099#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
3100
3101/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
3102#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3103#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3104#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
3105#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
3106
3107/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
3108#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3109#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3110#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
3111#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
3112
3113/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
3114#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3115#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3116#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
3117#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
3118
3119/* Register: MWU_NMIENSET */
3120/* Description: Enable non-maskable interrupt */
3121
3122/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
3123#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3124#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3125#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3126#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3127#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
3128
3129/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
3130#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3131#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3132#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3133#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3134#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
3135
3136/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
3137#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3138#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3139#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3140#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3141#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
3142
3143/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
3144#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3145#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3146#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3147#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3148#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
3149
3150/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
3151#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3152#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3153#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3154#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3155#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
3156
3157/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
3158#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3159#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3160#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3161#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3162#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
3163
3164/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
3165#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3166#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3167#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3168#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3169#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
3170
3171/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
3172#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3173#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3174#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3175#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3176#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
3177
3178/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
3179#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3180#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3181#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3182#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3183#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
3184
3185/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
3186#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3187#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3188#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3189#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3190#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
3191
3192/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
3193#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3194#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3195#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3196#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3197#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
3198
3199/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
3200#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3201#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3202#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3203#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3204#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
3205
3206/* Register: MWU_NMIENCLR */
3207/* Description: Disable non-maskable interrupt */
3208
3209/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
3210#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
3211#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
3212#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
3213#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
3214#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
3215
3216/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
3217#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
3218#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
3219#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
3220#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
3221#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
3222
3223/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
3224#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
3225#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
3226#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
3227#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
3228#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
3229
3230/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
3231#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
3232#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
3233#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
3234#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
3235#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
3236
3237/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
3238#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
3239#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
3240#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
3241#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
3242#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
3243
3244/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
3245#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
3246#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
3247#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
3248#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
3249#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
3250
3251/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
3252#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
3253#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
3254#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
3255#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
3256#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
3257
3258/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
3259#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
3260#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
3261#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
3262#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
3263#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
3264
3265/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
3266#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
3267#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
3268#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
3269#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
3270#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
3271
3272/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
3273#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
3274#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
3275#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
3276#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
3277#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
3278
3279/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
3280#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
3281#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
3282#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
3283#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
3284#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
3285
3286/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
3287#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
3288#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
3289#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
3290#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
3291#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
3292
3293/* Register: MWU_PERREGION_SUBSTATWA */
3294/* Description: Description cluster[0]: Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
3295
3296/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3297#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3298#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
3299#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
3300#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
3301
3302/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3303#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3304#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
3305#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
3306#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
3307
3308/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3309#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3310#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
3311#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
3312#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
3313
3314/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3315#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3316#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
3317#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
3318#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
3319
3320/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3321#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3322#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
3323#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
3324#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
3325
3326/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3327#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3328#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
3329#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
3330#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
3331
3332/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3333#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3334#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
3335#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
3336#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
3337
3338/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3339#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3340#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
3341#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
3342#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
3343
3344/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3345#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3346#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
3347#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
3348#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
3349
3350/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3351#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3352#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
3353#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
3354#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
3355
3356/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3357#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3358#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
3359#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
3360#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
3361
3362/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3363#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3364#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
3365#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
3366#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
3367
3368/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3369#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3370#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
3371#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
3372#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
3373
3374/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3375#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3376#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
3377#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
3378#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
3379
3380/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3381#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3382#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
3383#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
3384#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
3385
3386/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3387#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3388#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
3389#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
3390#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
3391
3392/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3393#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3394#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
3395#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
3396#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
3397
3398/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3399#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3400#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
3401#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
3402#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
3403
3404/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3405#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3406#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
3407#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
3408#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
3409
3410/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3411#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3412#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
3413#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
3414#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
3415
3416/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3417#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3418#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
3419#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
3420#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
3421
3422/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3423#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3424#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
3425#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
3426#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
3427
3428/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3429#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3430#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
3431#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
3432#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
3433
3434/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3435#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3436#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
3437#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
3438#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
3439
3440/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3441#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3442#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
3443#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
3444#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
3445
3446/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3447#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3448#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
3449#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
3450#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
3451
3452/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3453#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3454#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
3455#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
3456#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
3457
3458/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3459#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3460#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
3461#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
3462#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
3463
3464/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3465#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3466#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
3467#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
3468#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
3469
3470/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3471#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3472#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
3473#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
3474#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
3475
3476/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3477#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3478#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
3479#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
3480#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
3481
3482/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3483#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3484#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
3485#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
3486#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
3487
3488/* Register: MWU_PERREGION_SUBSTATRA */
3489/* Description: Description cluster[0]: Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
3490
3491/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
3492#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
3493#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
3494#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
3495#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
3496
3497/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
3498#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
3499#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
3500#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
3501#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
3502
3503/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
3504#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
3505#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
3506#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
3507#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
3508
3509/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
3510#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
3511#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
3512#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
3513#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
3514
3515/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
3516#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
3517#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
3518#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
3519#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
3520
3521/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
3522#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
3523#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
3524#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
3525#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
3526
3527/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
3528#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
3529#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
3530#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
3531#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
3532
3533/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
3534#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
3535#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
3536#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
3537#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
3538
3539/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
3540#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
3541#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
3542#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
3543#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
3544
3545/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
3546#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
3547#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
3548#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
3549#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
3550
3551/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
3552#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
3553#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
3554#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
3555#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
3556
3557/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
3558#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
3559#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
3560#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
3561#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
3562
3563/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
3564#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
3565#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
3566#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
3567#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
3568
3569/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
3570#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
3571#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
3572#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
3573#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
3574
3575/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
3576#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
3577#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
3578#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
3579#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
3580
3581/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
3582#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
3583#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
3584#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
3585#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
3586
3587/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
3588#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
3589#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
3590#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
3591#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
3592
3593/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
3594#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
3595#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
3596#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
3597#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
3598
3599/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
3600#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
3601#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
3602#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
3603#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
3604
3605/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
3606#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
3607#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
3608#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
3609#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
3610
3611/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
3612#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
3613#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
3614#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
3615#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
3616
3617/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
3618#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
3619#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
3620#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
3621#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
3622
3623/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
3624#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
3625#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
3626#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
3627#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
3628
3629/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
3630#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
3631#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
3632#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
3633#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
3634
3635/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
3636#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
3637#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
3638#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
3639#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
3640
3641/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
3642#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
3643#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
3644#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
3645#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
3646
3647/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
3648#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
3649#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
3650#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
3651#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
3652
3653/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
3654#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
3655#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
3656#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
3657#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
3658
3659/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
3660#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
3661#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
3662#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
3663#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
3664
3665/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
3666#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
3667#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
3668#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
3669#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
3670
3671/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
3672#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
3673#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
3674#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
3675#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
3676
3677/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
3678#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
3679#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
3680#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
3681#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
3682
3683/* Register: MWU_REGIONEN */
3684/* Description: Enable/disable regions watch */
3685
3686/* Bit 27 : Enable/disable read access watch in PREGION[1] */
3687#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3688#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3689#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3690#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3691
3692/* Bit 26 : Enable/disable write access watch in PREGION[1] */
3693#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3694#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3695#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3696#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3697
3698/* Bit 25 : Enable/disable read access watch in PREGION[0] */
3699#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3700#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3701#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
3702#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
3703
3704/* Bit 24 : Enable/disable write access watch in PREGION[0] */
3705#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3706#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3707#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
3708#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
3709
3710/* Bit 7 : Enable/disable read access watch in region[3] */
3711#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3712#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3713#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
3714#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
3715
3716/* Bit 6 : Enable/disable write access watch in region[3] */
3717#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3718#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3719#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
3720#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
3721
3722/* Bit 5 : Enable/disable read access watch in region[2] */
3723#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3724#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3725#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
3726#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
3727
3728/* Bit 4 : Enable/disable write access watch in region[2] */
3729#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3730#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3731#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
3732#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
3733
3734/* Bit 3 : Enable/disable read access watch in region[1] */
3735#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3736#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3737#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
3738#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
3739
3740/* Bit 2 : Enable/disable write access watch in region[1] */
3741#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3742#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3743#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
3744#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
3745
3746/* Bit 1 : Enable/disable read access watch in region[0] */
3747#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3748#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3749#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
3750#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
3751
3752/* Bit 0 : Enable/disable write access watch in region[0] */
3753#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3754#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3755#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
3756#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
3757
3758/* Register: MWU_REGIONENSET */
3759/* Description: Enable regions watch */
3760
3761/* Bit 27 : Enable read access watch in PREGION[1] */
3762#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3763#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3764#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3765#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3766#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3767
3768/* Bit 26 : Enable write access watch in PREGION[1] */
3769#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3770#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3771#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3772#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3773#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3774
3775/* Bit 25 : Enable read access watch in PREGION[0] */
3776#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3777#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3778#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3779#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3780#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
3781
3782/* Bit 24 : Enable write access watch in PREGION[0] */
3783#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3784#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3785#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3786#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3787#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
3788
3789/* Bit 7 : Enable read access watch in region[3] */
3790#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3791#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3792#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3793#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3794#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
3795
3796/* Bit 6 : Enable write access watch in region[3] */
3797#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3798#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3799#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3800#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3801#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
3802
3803/* Bit 5 : Enable read access watch in region[2] */
3804#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3805#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3806#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3807#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3808#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
3809
3810/* Bit 4 : Enable write access watch in region[2] */
3811#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3812#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3813#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3814#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3815#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
3816
3817/* Bit 3 : Enable read access watch in region[1] */
3818#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3819#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3820#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3821#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3822#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
3823
3824/* Bit 2 : Enable write access watch in region[1] */
3825#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3826#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3827#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3828#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3829#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
3830
3831/* Bit 1 : Enable read access watch in region[0] */
3832#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3833#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3834#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3835#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3836#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
3837
3838/* Bit 0 : Enable write access watch in region[0] */
3839#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3840#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3841#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3842#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3843#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
3844
3845/* Register: MWU_REGIONENCLR */
3846/* Description: Disable regions watch */
3847
3848/* Bit 27 : Disable read access watch in PREGION[1] */
3849#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
3850#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
3851#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3852#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3853#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3854
3855/* Bit 26 : Disable write access watch in PREGION[1] */
3856#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
3857#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
3858#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3859#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3860#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3861
3862/* Bit 25 : Disable read access watch in PREGION[0] */
3863#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
3864#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
3865#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
3866#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
3867#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
3868
3869/* Bit 24 : Disable write access watch in PREGION[0] */
3870#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
3871#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
3872#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
3873#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
3874#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
3875
3876/* Bit 7 : Disable read access watch in region[3] */
3877#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
3878#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
3879#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3880#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3881#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
3882
3883/* Bit 6 : Disable write access watch in region[3] */
3884#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
3885#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
3886#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3887#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3888#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
3889
3890/* Bit 5 : Disable read access watch in region[2] */
3891#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
3892#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
3893#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3894#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3895#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
3896
3897/* Bit 4 : Disable write access watch in region[2] */
3898#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
3899#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
3900#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3901#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3902#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
3903
3904/* Bit 3 : Disable read access watch in region[1] */
3905#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
3906#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
3907#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3908#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3909#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
3910
3911/* Bit 2 : Disable write access watch in region[1] */
3912#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
3913#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
3914#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3915#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3916#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
3917
3918/* Bit 1 : Disable read access watch in region[0] */
3919#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
3920#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
3921#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
3922#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
3923#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
3924
3925/* Bit 0 : Disable write access watch in region[0] */
3926#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
3927#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
3928#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
3929#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
3930#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
3931
3932/* Register: MWU_REGION_START */
3933/* Description: Description cluster[0]: Start address for region 0 */
3934
3935/* Bits 31..0 : Start address for region */
3936#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
3937#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
3938
3939/* Register: MWU_REGION_END */
3940/* Description: Description cluster[0]: End address of region 0 */
3941
3942/* Bits 31..0 : End address of region. */
3943#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
3944#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
3945
3946/* Register: MWU_PREGION_START */
3947/* Description: Description cluster[0]: Reserved for future use */
3948
3949/* Bits 31..0 : Reserved for future use */
3950#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
3951#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
3952
3953/* Register: MWU_PREGION_END */
3954/* Description: Description cluster[0]: Reserved for future use */
3955
3956/* Bits 31..0 : Reserved for future use */
3957#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
3958#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
3959
3960/* Register: MWU_PREGION_SUBS */
3961/* Description: Description cluster[0]: Subregions of region 0 */
3962
3963/* Bit 31 : Include or exclude subregion 31 in region */
3964#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
3965#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
3966#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
3967#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
3968
3969/* Bit 30 : Include or exclude subregion 30 in region */
3970#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
3971#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
3972#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
3973#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
3974
3975/* Bit 29 : Include or exclude subregion 29 in region */
3976#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
3977#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
3978#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
3979#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
3980
3981/* Bit 28 : Include or exclude subregion 28 in region */
3982#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
3983#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
3984#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
3985#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
3986
3987/* Bit 27 : Include or exclude subregion 27 in region */
3988#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
3989#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
3990#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
3991#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
3992
3993/* Bit 26 : Include or exclude subregion 26 in region */
3994#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
3995#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
3996#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
3997#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
3998
3999/* Bit 25 : Include or exclude subregion 25 in region */
4000#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
4001#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
4002#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
4003#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
4004
4005/* Bit 24 : Include or exclude subregion 24 in region */
4006#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
4007#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
4008#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
4009#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
4010
4011/* Bit 23 : Include or exclude subregion 23 in region */
4012#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
4013#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
4014#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
4015#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
4016
4017/* Bit 22 : Include or exclude subregion 22 in region */
4018#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
4019#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
4020#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
4021#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
4022
4023/* Bit 21 : Include or exclude subregion 21 in region */
4024#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
4025#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
4026#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
4027#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
4028
4029/* Bit 20 : Include or exclude subregion 20 in region */
4030#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
4031#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
4032#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
4033#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
4034
4035/* Bit 19 : Include or exclude subregion 19 in region */
4036#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
4037#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
4038#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
4039#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
4040
4041/* Bit 18 : Include or exclude subregion 18 in region */
4042#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
4043#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
4044#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
4045#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
4046
4047/* Bit 17 : Include or exclude subregion 17 in region */
4048#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
4049#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
4050#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
4051#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
4052
4053/* Bit 16 : Include or exclude subregion 16 in region */
4054#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
4055#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
4056#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
4057#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
4058
4059/* Bit 15 : Include or exclude subregion 15 in region */
4060#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
4061#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
4062#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
4063#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
4064
4065/* Bit 14 : Include or exclude subregion 14 in region */
4066#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
4067#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
4068#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
4069#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
4070
4071/* Bit 13 : Include or exclude subregion 13 in region */
4072#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
4073#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
4074#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
4075#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
4076
4077/* Bit 12 : Include or exclude subregion 12 in region */
4078#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
4079#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
4080#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
4081#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
4082
4083/* Bit 11 : Include or exclude subregion 11 in region */
4084#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
4085#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
4086#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
4087#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
4088
4089/* Bit 10 : Include or exclude subregion 10 in region */
4090#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
4091#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
4092#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
4093#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
4094
4095/* Bit 9 : Include or exclude subregion 9 in region */
4096#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
4097#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
4098#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
4099#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
4100
4101/* Bit 8 : Include or exclude subregion 8 in region */
4102#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
4103#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
4104#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
4105#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
4106
4107/* Bit 7 : Include or exclude subregion 7 in region */
4108#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
4109#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
4110#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
4111#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
4112
4113/* Bit 6 : Include or exclude subregion 6 in region */
4114#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
4115#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
4116#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
4117#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
4118
4119/* Bit 5 : Include or exclude subregion 5 in region */
4120#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
4121#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
4122#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
4123#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
4124
4125/* Bit 4 : Include or exclude subregion 4 in region */
4126#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
4127#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
4128#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
4129#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
4130
4131/* Bit 3 : Include or exclude subregion 3 in region */
4132#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
4133#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
4134#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
4135#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
4136
4137/* Bit 2 : Include or exclude subregion 2 in region */
4138#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
4139#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
4140#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
4141#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
4142
4143/* Bit 1 : Include or exclude subregion 1 in region */
4144#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
4145#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
4146#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
4147#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
4148
4149/* Bit 0 : Include or exclude subregion 0 in region */
4150#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
4151#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
4152#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
4153#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
4154
4155
4156/* Peripheral: NFCT */
4157/* Description: NFC-A compatible radio */
4158
4159/* Register: NFCT_SHORTS */
4160/* Description: Shortcut register */
4161
4162/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
4163#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
4164#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
4165#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
4166#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
4167
4168/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
4169#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
4170#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
4171#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
4172#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
4173
4174/* Register: NFCT_INTEN */
4175/* Description: Enable or disable interrupt */
4176
4177/* Bit 20 : Enable or disable interrupt for STARTED event */
4178#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4179#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
4180#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
4181#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
4182
4183/* Bit 19 : Enable or disable interrupt for SELECTED event */
4184#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4185#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4186#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
4187#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
4188
4189/* Bit 18 : Enable or disable interrupt for COLLISION event */
4190#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4191#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4192#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
4193#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
4194
4195/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
4196#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4197#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4198#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
4199#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
4200
4201/* Bit 12 : Enable or disable interrupt for ENDTX event */
4202#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4203#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4204#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
4205#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
4206
4207/* Bit 11 : Enable or disable interrupt for ENDRX event */
4208#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4209#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4210#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
4211#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
4212
4213/* Bit 10 : Enable or disable interrupt for RXERROR event */
4214#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4215#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4216#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
4217#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
4218
4219/* Bit 7 : Enable or disable interrupt for ERROR event */
4220#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4221#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
4222#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
4223#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
4224
4225/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
4226#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4227#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4228#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
4229#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
4230
4231/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
4232#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4233#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4234#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
4235#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
4236
4237/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
4238#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4239#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4240#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
4241#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
4242
4243/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
4244#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4245#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4246#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
4247#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
4248
4249/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
4250#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4251#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4252#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
4253#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
4254
4255/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
4256#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4257#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4258#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
4259#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
4260
4261/* Bit 0 : Enable or disable interrupt for READY event */
4262#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
4263#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
4264#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
4265#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
4266
4267/* Register: NFCT_INTENSET */
4268/* Description: Enable interrupt */
4269
4270/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
4271#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4272#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
4273#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
4274#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
4275#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
4276
4277/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
4278#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4279#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4280#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4281#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4282#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
4283
4284/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
4285#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4286#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4287#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4288#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4289#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
4290
4291/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
4292#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4293#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4294#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4295#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4296#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
4297
4298/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
4299#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4300#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4301#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4302#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4303#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
4304
4305/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
4306#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4307#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4308#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4309#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4310#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
4311
4312/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
4313#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4314#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4315#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4316#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4317#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
4318
4319/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
4320#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4321#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
4322#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
4323#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
4324#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
4325
4326/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
4327#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4328#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4329#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4330#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4331#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
4332
4333/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
4334#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4335#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4336#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4337#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4338#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
4339
4340/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
4341#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4342#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4343#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4344#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4345#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
4346
4347/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
4348#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4349#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4350#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4351#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4352#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
4353
4354/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
4355#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4356#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4357#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4358#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4359#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
4360
4361/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
4362#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4363#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4364#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4365#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4366#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
4367
4368/* Bit 0 : Write '1' to Enable interrupt for READY event */
4369#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
4370#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
4371#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
4372#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
4373#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
4374
4375/* Register: NFCT_INTENCLR */
4376/* Description: Disable interrupt */
4377
4378/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
4379#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
4380#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
4381#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
4382#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
4383#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
4384
4385/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
4386#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
4387#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
4388#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
4389#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
4390#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
4391
4392/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
4393#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
4394#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
4395#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
4396#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
4397#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
4398
4399/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
4400#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
4401#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
4402#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
4403#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
4404#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
4405
4406/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
4407#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
4408#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
4409#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
4410#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
4411#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
4412
4413/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
4414#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
4415#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
4416#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
4417#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
4418#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
4419
4420/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
4421#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
4422#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
4423#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
4424#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
4425#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
4426
4427/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
4428#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
4429#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
4430#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
4431#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
4432#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
4433
4434/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
4435#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
4436#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
4437#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4438#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4439#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
4440
4441/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
4442#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
4443#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
4444#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4445#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4446#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
4447
4448/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
4449#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
4450#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
4451#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
4452#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
4453#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
4454
4455/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
4456#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
4457#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
4458#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
4459#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
4460#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
4461
4462/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
4463#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
4464#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
4465#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
4466#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
4467#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
4468
4469/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
4470#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
4471#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
4472#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
4473#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
4474#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
4475
4476/* Bit 0 : Write '1' to Disable interrupt for READY event */
4477#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
4478#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
4479#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
4480#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
4481#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
4482
4483/* Register: NFCT_ERRORSTATUS */
4484/* Description: NFC Error Status register */
4485
4486/* Bit 3 : Field level is too low at min load resistance */
4487#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
4488#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
4489
4490/* Bit 2 : Field level is too high at max load resistance */
4491#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
4492#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
4493
4494/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
4495#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
4496#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
4497
4498/* Register: NFCT_FRAMESTATUS_RX */
4499/* Description: Result of last incoming frames */
4500
4501/* Bit 3 : Overrun detected */
4502#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
4503#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
4504#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
4505#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
4506
4507/* Bit 2 : Parity status of received frame */
4508#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
4509#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
4510#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
4511#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
4512
4513/* Bit 0 : No valid End of Frame detected */
4514#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
4515#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
4516#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
4517#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
4518
4519/* Register: NFCT_CURRENTLOADCTRL */
4520/* Description: Current value driven to the NFC Load Control */
4521
4522/* Bits 5..0 : Current value driven to the NFC Load Control */
4523#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
4524#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
4525
4526/* Register: NFCT_FIELDPRESENT */
4527/* Description: Indicates the presence or not of a valid field */
4528
4529/* Bit 1 : Indicates if the low level has locked to the field */
4530#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
4531#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
4532#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
4533#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
4534
4535/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
4536#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
4537#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
4538#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
4539#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
4540
4541/* Register: NFCT_FRAMEDELAYMIN */
4542/* Description: Minimum frame delay */
4543
4544/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
4545#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
4546#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
4547
4548/* Register: NFCT_FRAMEDELAYMAX */
4549/* Description: Maximum frame delay */
4550
4551/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
4552#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
4553#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
4554
4555/* Register: NFCT_FRAMEDELAYMODE */
4556/* Description: Configuration register for the Frame Delay Timer */
4557
4558/* Bits 1..0 : Configuration register for the Frame Delay Timer */
4559#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
4560#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
4561#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
4562#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
4563#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
4564#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
4565
4566/* Register: NFCT_PACKETPTR */
4567/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
4568
4569/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
4570#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
4571#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
4572
4573/* Register: NFCT_MAXLEN */
4574/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
4575
4576/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
4577#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
4578#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
4579
4580/* Register: NFCT_TXD_FRAMECONFIG */
4581/* Description: Configuration of outgoing frames */
4582
4583/* Bit 4 : CRC mode for outgoing frames */
4584#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
4585#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
4586#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
4587#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
4588
4589/* Bit 2 : Adding SoF or not in TX frames */
4590#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4591#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4592#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
4593#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
4594
4595/* Bit 1 : Discarding unused bits in start or at end of a Frame */
4596#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
4597#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
4598#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
4599#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
4600
4601/* Bit 0 : Adding parity or not in the frame */
4602#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4603#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4604#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
4605#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
4606
4607/* Register: NFCT_TXD_AMOUNT */
4608/* Description: Size of outgoing frame */
4609
4610/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
4611#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
4612#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
4613
4614/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
4615#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
4616#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
4617
4618/* Register: NFCT_RXD_FRAMECONFIG */
4619/* Description: Configuration of incoming frames */
4620
4621/* Bit 4 : CRC mode for incoming frames */
4622#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
4623#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
4624#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
4625#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
4626
4627/* Bit 2 : SoF expected or not in RX frames */
4628#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
4629#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
4630#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
4631#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
4632
4633/* Bit 0 : Parity expected or not in RX frame */
4634#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
4635#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
4636#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
4637#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
4638
4639/* Register: NFCT_RXD_AMOUNT */
4640/* Description: Size of last incoming frame */
4641
4642/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
4643#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
4644#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
4645
4646/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
4647#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
4648#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
4649
4650/* Register: NFCT_NFCID1_LAST */
4651/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
4652
4653/* Bits 31..24 : NFCID1 byte W */
4654#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
4655#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
4656
4657/* Bits 23..16 : NFCID1 byte X */
4658#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
4659#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
4660
4661/* Bits 15..8 : NFCID1 byte Y */
4662#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
4663#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
4664
4665/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
4666#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
4667#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
4668
4669/* Register: NFCT_NFCID1_2ND_LAST */
4670/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
4671
4672/* Bits 23..16 : NFCID1 byte T */
4673#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
4674#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
4675
4676/* Bits 15..8 : NFCID1 byte U */
4677#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
4678#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
4679
4680/* Bits 7..0 : NFCID1 byte V */
4681#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
4682#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
4683
4684/* Register: NFCT_NFCID1_3RD_LAST */
4685/* Description: Third last NFCID1 part (10 bytes ID) */
4686
4687/* Bits 23..16 : NFCID1 byte Q */
4688#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
4689#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
4690
4691/* Bits 15..8 : NFCID1 byte R */
4692#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
4693#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
4694
4695/* Bits 7..0 : NFCID1 byte S */
4696#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
4697#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
4698
4699/* Register: NFCT_SENSRES */
4700/* Description: NFC-A SENS_RES auto-response settings */
4701
4702/* Bits 15..12 : Reserved for future use. Shall be 0. */
4703#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
4704#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
4705
4706/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4707#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
4708#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
4709
4710/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
4711#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
4712#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
4713#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
4714#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
4715#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
4716
4717/* Bit 5 : Reserved for future use. Shall be 0. */
4718#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
4719#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
4720
4721/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4722#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
4723#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
4724#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
4725#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
4726#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
4727#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
4728#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
4729#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
4730
4731/* Register: NFCT_SELRES */
4732/* Description: NFC-A SEL_RES auto-response settings */
4733
4734/* Bit 7 : Reserved for future use. Shall be 0. */
4735#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
4736#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
4737
4738/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
4739#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
4740#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
4741
4742/* Bits 4..3 : Reserved for future use. Shall be 0. */
4743#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
4744#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
4745
4746/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
4747#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
4748#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
4749#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
4750#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
4751
4752/* Bits 1..0 : Reserved for future use. Shall be 0. */
4753#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
4754#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
4755
4756
4757/* Peripheral: NVMC */
4758/* Description: Non Volatile Memory Controller */
4759
4760/* Register: NVMC_READY */
4761/* Description: Ready flag */
4762
4763/* Bit 0 : NVMC is ready or busy */
4764#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
4765#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
4766#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
4767#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
4768
4769/* Register: NVMC_CONFIG */
4770/* Description: Configuration register */
4771
4772/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
4773#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
4774#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
4775#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
4776#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
4777#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
4778
4779/* Register: NVMC_ERASEPAGE */
4780/* Description: Register for erasing a page in Code area */
4781
4782/* Bits 31..0 : Register for starting erase of a page in Code area */
4783#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
4784#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
4785
4786/* Register: NVMC_ERASEPCR1 */
4787/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4788
4789/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4790#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
4791#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
4792
4793/* Register: NVMC_ERASEALL */
4794/* Description: Register for erasing all non-volatile user memory */
4795
4796/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4797#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
4798#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
4799#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
4800#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
4801
4802/* Register: NVMC_ERASEPCR0 */
4803/* Description: Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
4804
4805/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
4806#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
4807#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
4808
4809/* Register: NVMC_ERASEUICR */
4810/* Description: Register for erasing User Information Configuration Registers */
4811
4812/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
4813#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
4814#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
4815#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
4816#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
4817
4818/* Register: NVMC_ICACHECNF */
4819/* Description: I-Code cache configuration register. */
4820
4821/* Bit 8 : Cache profiling enable */
4822#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
4823#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
4824#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
4825#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
4826
4827/* Bit 0 : Cache enable */
4828#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
4829#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
4830#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
4831#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
4832
4833/* Register: NVMC_IHIT */
4834/* Description: I-Code cache hit counter. */
4835
4836/* Bits 31..0 : Number of cache hits */
4837#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
4838#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
4839
4840/* Register: NVMC_IMISS */
4841/* Description: I-Code cache miss counter. */
4842
4843/* Bits 31..0 : Number of cache misses */
4844#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
4845#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
4846
4847
4848/* Peripheral: GPIO */
4849/* Description: GPIO Port 1 */
4850
4851/* Register: GPIO_OUT */
4852/* Description: Write GPIO port */
4853
4854/* Bit 31 : Pin 31 */
4855#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
4856#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
4857#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
4858#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
4859
4860/* Bit 30 : Pin 30 */
4861#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
4862#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
4863#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
4864#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
4865
4866/* Bit 29 : Pin 29 */
4867#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
4868#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
4869#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
4870#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
4871
4872/* Bit 28 : Pin 28 */
4873#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
4874#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
4875#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
4876#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
4877
4878/* Bit 27 : Pin 27 */
4879#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
4880#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
4881#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
4882#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
4883
4884/* Bit 26 : Pin 26 */
4885#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
4886#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
4887#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
4888#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
4889
4890/* Bit 25 : Pin 25 */
4891#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
4892#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
4893#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
4894#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
4895
4896/* Bit 24 : Pin 24 */
4897#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
4898#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
4899#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
4900#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
4901
4902/* Bit 23 : Pin 23 */
4903#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
4904#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
4905#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
4906#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
4907
4908/* Bit 22 : Pin 22 */
4909#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
4910#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
4911#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
4912#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
4913
4914/* Bit 21 : Pin 21 */
4915#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
4916#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
4917#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
4918#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
4919
4920/* Bit 20 : Pin 20 */
4921#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
4922#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
4923#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
4924#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
4925
4926/* Bit 19 : Pin 19 */
4927#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
4928#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
4929#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
4930#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
4931
4932/* Bit 18 : Pin 18 */
4933#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
4934#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
4935#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
4936#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
4937
4938/* Bit 17 : Pin 17 */
4939#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
4940#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
4941#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
4942#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
4943
4944/* Bit 16 : Pin 16 */
4945#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
4946#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
4947#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
4948#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
4949
4950/* Bit 15 : Pin 15 */
4951#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
4952#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
4953#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
4954#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
4955
4956/* Bit 14 : Pin 14 */
4957#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
4958#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
4959#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
4960#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
4961
4962/* Bit 13 : Pin 13 */
4963#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
4964#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
4965#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
4966#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
4967
4968/* Bit 12 : Pin 12 */
4969#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
4970#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
4971#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
4972#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
4973
4974/* Bit 11 : Pin 11 */
4975#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
4976#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
4977#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
4978#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
4979
4980/* Bit 10 : Pin 10 */
4981#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
4982#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
4983#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
4984#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
4985
4986/* Bit 9 : Pin 9 */
4987#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
4988#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
4989#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
4990#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
4991
4992/* Bit 8 : Pin 8 */
4993#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
4994#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
4995#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
4996#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
4997
4998/* Bit 7 : Pin 7 */
4999#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5000#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5001#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
5002#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
5003
5004/* Bit 6 : Pin 6 */
5005#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5006#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5007#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
5008#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
5009
5010/* Bit 5 : Pin 5 */
5011#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5012#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5013#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
5014#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
5015
5016/* Bit 4 : Pin 4 */
5017#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5018#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5019#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
5020#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
5021
5022/* Bit 3 : Pin 3 */
5023#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5024#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5025#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
5026#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
5027
5028/* Bit 2 : Pin 2 */
5029#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5030#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5031#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
5032#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
5033
5034/* Bit 1 : Pin 1 */
5035#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5036#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5037#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
5038#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
5039
5040/* Bit 0 : Pin 0 */
5041#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5042#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5043#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
5044#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
5045
5046/* Register: GPIO_OUTSET */
5047/* Description: Set individual bits in GPIO port */
5048
5049/* Bit 31 : Pin 31 */
5050#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5051#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5052#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
5053#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
5054#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5055
5056/* Bit 30 : Pin 30 */
5057#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5058#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5059#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
5060#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
5061#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5062
5063/* Bit 29 : Pin 29 */
5064#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5065#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5066#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
5067#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
5068#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5069
5070/* Bit 28 : Pin 28 */
5071#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5072#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5073#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
5074#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
5075#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5076
5077/* Bit 27 : Pin 27 */
5078#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5079#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5080#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
5081#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
5082#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5083
5084/* Bit 26 : Pin 26 */
5085#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5086#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5087#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
5088#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
5089#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5090
5091/* Bit 25 : Pin 25 */
5092#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5093#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5094#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
5095#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
5096#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5097
5098/* Bit 24 : Pin 24 */
5099#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5100#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5101#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
5102#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
5103#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5104
5105/* Bit 23 : Pin 23 */
5106#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5107#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5108#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
5109#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
5110#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5111
5112/* Bit 22 : Pin 22 */
5113#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5114#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5115#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
5116#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
5117#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5118
5119/* Bit 21 : Pin 21 */
5120#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5121#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5122#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
5123#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
5124#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5125
5126/* Bit 20 : Pin 20 */
5127#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5128#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5129#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
5130#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
5131#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5132
5133/* Bit 19 : Pin 19 */
5134#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5135#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5136#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
5137#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
5138#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5139
5140/* Bit 18 : Pin 18 */
5141#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5142#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5143#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
5144#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
5145#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5146
5147/* Bit 17 : Pin 17 */
5148#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5149#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5150#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
5151#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
5152#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5153
5154/* Bit 16 : Pin 16 */
5155#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5156#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5157#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
5158#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
5159#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5160
5161/* Bit 15 : Pin 15 */
5162#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5163#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5164#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
5165#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
5166#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5167
5168/* Bit 14 : Pin 14 */
5169#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5170#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5171#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
5172#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
5173#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5174
5175/* Bit 13 : Pin 13 */
5176#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5177#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5178#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
5179#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
5180#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5181
5182/* Bit 12 : Pin 12 */
5183#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5184#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5185#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
5186#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
5187#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5188
5189/* Bit 11 : Pin 11 */
5190#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5191#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5192#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
5193#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
5194#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5195
5196/* Bit 10 : Pin 10 */
5197#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5198#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5199#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
5200#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
5201#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5202
5203/* Bit 9 : Pin 9 */
5204#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5205#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5206#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
5207#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
5208#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5209
5210/* Bit 8 : Pin 8 */
5211#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5212#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5213#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
5214#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
5215#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5216
5217/* Bit 7 : Pin 7 */
5218#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5219#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5220#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
5221#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
5222#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5223
5224/* Bit 6 : Pin 6 */
5225#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5226#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5227#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
5228#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
5229#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5230
5231/* Bit 5 : Pin 5 */
5232#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5233#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5234#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
5235#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
5236#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5237
5238/* Bit 4 : Pin 4 */
5239#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5240#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5241#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
5242#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
5243#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5244
5245/* Bit 3 : Pin 3 */
5246#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5247#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5248#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
5249#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
5250#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5251
5252/* Bit 2 : Pin 2 */
5253#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5254#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5255#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
5256#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
5257#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5258
5259/* Bit 1 : Pin 1 */
5260#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5261#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5262#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
5263#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
5264#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5265
5266/* Bit 0 : Pin 0 */
5267#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5268#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5269#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
5270#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
5271#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
5272
5273/* Register: GPIO_OUTCLR */
5274/* Description: Clear individual bits in GPIO port */
5275
5276/* Bit 31 : Pin 31 */
5277#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5278#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5279#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
5280#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
5281#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5282
5283/* Bit 30 : Pin 30 */
5284#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5285#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5286#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
5287#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
5288#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5289
5290/* Bit 29 : Pin 29 */
5291#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5292#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5293#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
5294#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
5295#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5296
5297/* Bit 28 : Pin 28 */
5298#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5299#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5300#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
5301#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
5302#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5303
5304/* Bit 27 : Pin 27 */
5305#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5306#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5307#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
5308#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
5309#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5310
5311/* Bit 26 : Pin 26 */
5312#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5313#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5314#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
5315#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
5316#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5317
5318/* Bit 25 : Pin 25 */
5319#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5320#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5321#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
5322#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
5323#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5324
5325/* Bit 24 : Pin 24 */
5326#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5327#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5328#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
5329#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
5330#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5331
5332/* Bit 23 : Pin 23 */
5333#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5334#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5335#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
5336#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
5337#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5338
5339/* Bit 22 : Pin 22 */
5340#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5341#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5342#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
5343#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
5344#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5345
5346/* Bit 21 : Pin 21 */
5347#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5348#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5349#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
5350#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
5351#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5352
5353/* Bit 20 : Pin 20 */
5354#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5355#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5356#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
5357#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
5358#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5359
5360/* Bit 19 : Pin 19 */
5361#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5362#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5363#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
5364#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
5365#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5366
5367/* Bit 18 : Pin 18 */
5368#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5369#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5370#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
5371#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
5372#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5373
5374/* Bit 17 : Pin 17 */
5375#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5376#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5377#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
5378#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
5379#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5380
5381/* Bit 16 : Pin 16 */
5382#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5383#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5384#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
5385#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
5386#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5387
5388/* Bit 15 : Pin 15 */
5389#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5390#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5391#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
5392#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
5393#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5394
5395/* Bit 14 : Pin 14 */
5396#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5397#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5398#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
5399#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
5400#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5401
5402/* Bit 13 : Pin 13 */
5403#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5404#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5405#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
5406#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
5407#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5408
5409/* Bit 12 : Pin 12 */
5410#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5411#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5412#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
5413#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
5414#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5415
5416/* Bit 11 : Pin 11 */
5417#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5418#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5419#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
5420#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
5421#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5422
5423/* Bit 10 : Pin 10 */
5424#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5425#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5426#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
5427#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
5428#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5429
5430/* Bit 9 : Pin 9 */
5431#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5432#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5433#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
5434#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
5435#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5436
5437/* Bit 8 : Pin 8 */
5438#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5439#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5440#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
5441#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
5442#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5443
5444/* Bit 7 : Pin 7 */
5445#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5446#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5447#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
5448#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
5449#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5450
5451/* Bit 6 : Pin 6 */
5452#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5453#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5454#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
5455#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
5456#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5457
5458/* Bit 5 : Pin 5 */
5459#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5460#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5461#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
5462#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
5463#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5464
5465/* Bit 4 : Pin 4 */
5466#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5467#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5468#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
5469#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
5470#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5471
5472/* Bit 3 : Pin 3 */
5473#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5474#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5475#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
5476#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
5477#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5478
5479/* Bit 2 : Pin 2 */
5480#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5481#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5482#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
5483#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
5484#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5485
5486/* Bit 1 : Pin 1 */
5487#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5488#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5489#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
5490#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
5491#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5492
5493/* Bit 0 : Pin 0 */
5494#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5495#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5496#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
5497#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
5498#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
5499
5500/* Register: GPIO_IN */
5501/* Description: Read GPIO port */
5502
5503/* Bit 31 : Pin 31 */
5504#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5505#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5506#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
5507#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
5508
5509/* Bit 30 : Pin 30 */
5510#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5511#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5512#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
5513#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
5514
5515/* Bit 29 : Pin 29 */
5516#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5517#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5518#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
5519#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
5520
5521/* Bit 28 : Pin 28 */
5522#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5523#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5524#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
5525#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
5526
5527/* Bit 27 : Pin 27 */
5528#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5529#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5530#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
5531#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
5532
5533/* Bit 26 : Pin 26 */
5534#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5535#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5536#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
5537#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
5538
5539/* Bit 25 : Pin 25 */
5540#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5541#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5542#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
5543#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
5544
5545/* Bit 24 : Pin 24 */
5546#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5547#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5548#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
5549#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
5550
5551/* Bit 23 : Pin 23 */
5552#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5553#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5554#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
5555#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
5556
5557/* Bit 22 : Pin 22 */
5558#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5559#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5560#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
5561#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
5562
5563/* Bit 21 : Pin 21 */
5564#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5565#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5566#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
5567#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
5568
5569/* Bit 20 : Pin 20 */
5570#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5571#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5572#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
5573#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
5574
5575/* Bit 19 : Pin 19 */
5576#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5577#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5578#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
5579#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
5580
5581/* Bit 18 : Pin 18 */
5582#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5583#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5584#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
5585#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
5586
5587/* Bit 17 : Pin 17 */
5588#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5589#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5590#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
5591#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
5592
5593/* Bit 16 : Pin 16 */
5594#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5595#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5596#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
5597#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
5598
5599/* Bit 15 : Pin 15 */
5600#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5601#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5602#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
5603#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
5604
5605/* Bit 14 : Pin 14 */
5606#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5607#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5608#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
5609#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
5610
5611/* Bit 13 : Pin 13 */
5612#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5613#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5614#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
5615#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
5616
5617/* Bit 12 : Pin 12 */
5618#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5619#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5620#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
5621#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
5622
5623/* Bit 11 : Pin 11 */
5624#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5625#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5626#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
5627#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
5628
5629/* Bit 10 : Pin 10 */
5630#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5631#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5632#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
5633#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
5634
5635/* Bit 9 : Pin 9 */
5636#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5637#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5638#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
5639#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
5640
5641/* Bit 8 : Pin 8 */
5642#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5643#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5644#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
5645#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
5646
5647/* Bit 7 : Pin 7 */
5648#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5649#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5650#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
5651#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
5652
5653/* Bit 6 : Pin 6 */
5654#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5655#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5656#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
5657#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
5658
5659/* Bit 5 : Pin 5 */
5660#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5661#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5662#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
5663#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
5664
5665/* Bit 4 : Pin 4 */
5666#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5667#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5668#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
5669#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
5670
5671/* Bit 3 : Pin 3 */
5672#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5673#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5674#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
5675#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
5676
5677/* Bit 2 : Pin 2 */
5678#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5679#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5680#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
5681#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
5682
5683/* Bit 1 : Pin 1 */
5684#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5685#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5686#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
5687#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
5688
5689/* Bit 0 : Pin 0 */
5690#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5691#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5692#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
5693#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
5694
5695/* Register: GPIO_DIR */
5696/* Description: Direction of GPIO pins */
5697
5698/* Bit 31 : Pin 31 */
5699#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5700#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5701#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
5702#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
5703
5704/* Bit 30 : Pin 30 */
5705#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5706#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5707#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
5708#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
5709
5710/* Bit 29 : Pin 29 */
5711#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5712#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5713#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
5714#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
5715
5716/* Bit 28 : Pin 28 */
5717#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5718#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5719#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
5720#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
5721
5722/* Bit 27 : Pin 27 */
5723#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5724#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5725#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
5726#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
5727
5728/* Bit 26 : Pin 26 */
5729#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5730#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5731#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
5732#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
5733
5734/* Bit 25 : Pin 25 */
5735#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5736#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5737#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
5738#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
5739
5740/* Bit 24 : Pin 24 */
5741#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5742#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5743#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
5744#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
5745
5746/* Bit 23 : Pin 23 */
5747#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5748#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5749#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
5750#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
5751
5752/* Bit 22 : Pin 22 */
5753#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5754#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5755#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
5756#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
5757
5758/* Bit 21 : Pin 21 */
5759#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5760#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5761#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
5762#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
5763
5764/* Bit 20 : Pin 20 */
5765#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5766#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5767#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
5768#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
5769
5770/* Bit 19 : Pin 19 */
5771#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5772#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5773#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
5774#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
5775
5776/* Bit 18 : Pin 18 */
5777#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5778#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5779#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
5780#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
5781
5782/* Bit 17 : Pin 17 */
5783#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5784#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5785#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
5786#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
5787
5788/* Bit 16 : Pin 16 */
5789#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
5790#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
5791#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
5792#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
5793
5794/* Bit 15 : Pin 15 */
5795#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
5796#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
5797#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
5798#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
5799
5800/* Bit 14 : Pin 14 */
5801#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
5802#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
5803#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
5804#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
5805
5806/* Bit 13 : Pin 13 */
5807#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
5808#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
5809#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
5810#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
5811
5812/* Bit 12 : Pin 12 */
5813#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
5814#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
5815#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
5816#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
5817
5818/* Bit 11 : Pin 11 */
5819#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
5820#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
5821#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
5822#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
5823
5824/* Bit 10 : Pin 10 */
5825#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
5826#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
5827#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
5828#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
5829
5830/* Bit 9 : Pin 9 */
5831#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
5832#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
5833#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
5834#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
5835
5836/* Bit 8 : Pin 8 */
5837#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
5838#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
5839#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
5840#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
5841
5842/* Bit 7 : Pin 7 */
5843#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
5844#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
5845#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
5846#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
5847
5848/* Bit 6 : Pin 6 */
5849#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
5850#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
5851#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
5852#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
5853
5854/* Bit 5 : Pin 5 */
5855#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
5856#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
5857#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
5858#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
5859
5860/* Bit 4 : Pin 4 */
5861#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
5862#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
5863#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
5864#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
5865
5866/* Bit 3 : Pin 3 */
5867#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
5868#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
5869#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
5870#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
5871
5872/* Bit 2 : Pin 2 */
5873#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
5874#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
5875#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
5876#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
5877
5878/* Bit 1 : Pin 1 */
5879#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
5880#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
5881#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
5882#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
5883
5884/* Bit 0 : Pin 0 */
5885#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
5886#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
5887#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
5888#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
5889
5890/* Register: GPIO_DIRSET */
5891/* Description: DIR set register */
5892
5893/* Bit 31 : Set as output pin 31 */
5894#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
5895#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
5896#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
5897#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
5898#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5899
5900/* Bit 30 : Set as output pin 30 */
5901#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
5902#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
5903#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
5904#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
5905#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5906
5907/* Bit 29 : Set as output pin 29 */
5908#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
5909#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
5910#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
5911#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
5912#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5913
5914/* Bit 28 : Set as output pin 28 */
5915#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
5916#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
5917#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
5918#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
5919#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5920
5921/* Bit 27 : Set as output pin 27 */
5922#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
5923#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
5924#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
5925#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
5926#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5927
5928/* Bit 26 : Set as output pin 26 */
5929#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
5930#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
5931#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
5932#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
5933#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5934
5935/* Bit 25 : Set as output pin 25 */
5936#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
5937#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
5938#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
5939#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
5940#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5941
5942/* Bit 24 : Set as output pin 24 */
5943#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
5944#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
5945#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
5946#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
5947#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5948
5949/* Bit 23 : Set as output pin 23 */
5950#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
5951#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
5952#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
5953#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
5954#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5955
5956/* Bit 22 : Set as output pin 22 */
5957#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
5958#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
5959#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
5960#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
5961#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5962
5963/* Bit 21 : Set as output pin 21 */
5964#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
5965#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
5966#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
5967#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
5968#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5969
5970/* Bit 20 : Set as output pin 20 */
5971#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
5972#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
5973#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
5974#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
5975#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5976
5977/* Bit 19 : Set as output pin 19 */
5978#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
5979#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
5980#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
5981#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
5982#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5983
5984/* Bit 18 : Set as output pin 18 */
5985#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
5986#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
5987#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
5988#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
5989#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5990
5991/* Bit 17 : Set as output pin 17 */
5992#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
5993#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
5994#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
5995#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
5996#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
5997
5998/* Bit 16 : Set as output pin 16 */
5999#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6000#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6001#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
6002#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
6003#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6004
6005/* Bit 15 : Set as output pin 15 */
6006#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6007#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6008#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
6009#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
6010#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6011
6012/* Bit 14 : Set as output pin 14 */
6013#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6014#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6015#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
6016#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
6017#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6018
6019/* Bit 13 : Set as output pin 13 */
6020#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6021#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6022#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
6023#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
6024#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6025
6026/* Bit 12 : Set as output pin 12 */
6027#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6028#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6029#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
6030#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
6031#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6032
6033/* Bit 11 : Set as output pin 11 */
6034#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6035#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6036#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
6037#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
6038#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6039
6040/* Bit 10 : Set as output pin 10 */
6041#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6042#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6043#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
6044#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
6045#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6046
6047/* Bit 9 : Set as output pin 9 */
6048#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6049#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6050#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
6051#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
6052#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6053
6054/* Bit 8 : Set as output pin 8 */
6055#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6056#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6057#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
6058#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
6059#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6060
6061/* Bit 7 : Set as output pin 7 */
6062#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6063#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6064#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
6065#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
6066#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6067
6068/* Bit 6 : Set as output pin 6 */
6069#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6070#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6071#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
6072#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
6073#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6074
6075/* Bit 5 : Set as output pin 5 */
6076#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6077#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6078#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
6079#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
6080#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6081
6082/* Bit 4 : Set as output pin 4 */
6083#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6084#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6085#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
6086#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
6087#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6088
6089/* Bit 3 : Set as output pin 3 */
6090#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6091#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6092#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
6093#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
6094#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6095
6096/* Bit 2 : Set as output pin 2 */
6097#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6098#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6099#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
6100#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
6101#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6102
6103/* Bit 1 : Set as output pin 1 */
6104#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6105#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6106#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
6107#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
6108#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6109
6110/* Bit 0 : Set as output pin 0 */
6111#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6112#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6113#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
6114#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
6115#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
6116
6117/* Register: GPIO_DIRCLR */
6118/* Description: DIR clear register */
6119
6120/* Bit 31 : Set as input pin 31 */
6121#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6122#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6123#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
6124#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
6125#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6126
6127/* Bit 30 : Set as input pin 30 */
6128#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6129#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6130#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
6131#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
6132#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6133
6134/* Bit 29 : Set as input pin 29 */
6135#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6136#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6137#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
6138#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
6139#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6140
6141/* Bit 28 : Set as input pin 28 */
6142#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6143#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6144#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
6145#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
6146#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6147
6148/* Bit 27 : Set as input pin 27 */
6149#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6150#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6151#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
6152#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
6153#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6154
6155/* Bit 26 : Set as input pin 26 */
6156#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6157#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6158#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
6159#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
6160#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6161
6162/* Bit 25 : Set as input pin 25 */
6163#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6164#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6165#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
6166#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
6167#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6168
6169/* Bit 24 : Set as input pin 24 */
6170#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6171#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6172#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
6173#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
6174#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6175
6176/* Bit 23 : Set as input pin 23 */
6177#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6178#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6179#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
6180#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
6181#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6182
6183/* Bit 22 : Set as input pin 22 */
6184#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6185#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6186#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
6187#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
6188#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6189
6190/* Bit 21 : Set as input pin 21 */
6191#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6192#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6193#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
6194#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
6195#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6196
6197/* Bit 20 : Set as input pin 20 */
6198#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6199#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6200#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
6201#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
6202#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6203
6204/* Bit 19 : Set as input pin 19 */
6205#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6206#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6207#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
6208#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
6209#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6210
6211/* Bit 18 : Set as input pin 18 */
6212#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6213#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6214#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
6215#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
6216#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6217
6218/* Bit 17 : Set as input pin 17 */
6219#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6220#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6221#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
6222#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
6223#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6224
6225/* Bit 16 : Set as input pin 16 */
6226#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6227#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6228#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
6229#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
6230#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6231
6232/* Bit 15 : Set as input pin 15 */
6233#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6234#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6235#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
6236#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
6237#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6238
6239/* Bit 14 : Set as input pin 14 */
6240#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6241#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6242#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
6243#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
6244#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6245
6246/* Bit 13 : Set as input pin 13 */
6247#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6248#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6249#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
6250#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
6251#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6252
6253/* Bit 12 : Set as input pin 12 */
6254#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6255#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6256#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
6257#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
6258#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6259
6260/* Bit 11 : Set as input pin 11 */
6261#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6262#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6263#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
6264#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
6265#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6266
6267/* Bit 10 : Set as input pin 10 */
6268#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6269#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6270#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
6271#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
6272#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6273
6274/* Bit 9 : Set as input pin 9 */
6275#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6276#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6277#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
6278#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
6279#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6280
6281/* Bit 8 : Set as input pin 8 */
6282#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6283#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6284#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
6285#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
6286#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6287
6288/* Bit 7 : Set as input pin 7 */
6289#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6290#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6291#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
6292#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
6293#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6294
6295/* Bit 6 : Set as input pin 6 */
6296#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6297#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6298#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
6299#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
6300#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6301
6302/* Bit 5 : Set as input pin 5 */
6303#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6304#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6305#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
6306#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
6307#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6308
6309/* Bit 4 : Set as input pin 4 */
6310#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6311#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6312#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
6313#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
6314#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6315
6316/* Bit 3 : Set as input pin 3 */
6317#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6318#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6319#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
6320#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
6321#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6322
6323/* Bit 2 : Set as input pin 2 */
6324#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6325#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6326#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
6327#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
6328#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6329
6330/* Bit 1 : Set as input pin 1 */
6331#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6332#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6333#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
6334#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
6335#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6336
6337/* Bit 0 : Set as input pin 0 */
6338#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6339#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6340#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
6341#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
6342#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
6343
6344/* Register: GPIO_LATCH */
6345/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
6346
6347/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
6348#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
6349#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
6350#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
6351#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
6352
6353/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
6354#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
6355#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
6356#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
6357#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
6358
6359/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
6360#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
6361#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
6362#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
6363#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
6364
6365/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
6366#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
6367#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
6368#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
6369#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
6370
6371/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
6372#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
6373#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
6374#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
6375#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
6376
6377/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
6378#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
6379#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
6380#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
6381#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
6382
6383/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
6384#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
6385#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
6386#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
6387#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
6388
6389/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
6390#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
6391#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
6392#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
6393#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
6394
6395/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
6396#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
6397#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
6398#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
6399#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
6400
6401/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
6402#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
6403#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
6404#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
6405#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
6406
6407/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
6408#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
6409#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
6410#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
6411#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
6412
6413/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
6414#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
6415#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
6416#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
6417#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
6418
6419/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
6420#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
6421#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
6422#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
6423#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
6424
6425/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
6426#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
6427#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
6428#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
6429#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
6430
6431/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
6432#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
6433#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
6434#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
6435#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
6436
6437/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
6438#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
6439#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
6440#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
6441#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
6442
6443/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
6444#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
6445#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
6446#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
6447#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
6448
6449/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
6450#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
6451#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
6452#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
6453#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
6454
6455/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
6456#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
6457#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
6458#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
6459#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
6460
6461/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
6462#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
6463#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
6464#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
6465#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
6466
6467/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
6468#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
6469#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
6470#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
6471#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
6472
6473/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
6474#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
6475#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
6476#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
6477#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
6478
6479/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
6480#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
6481#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
6482#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
6483#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
6484
6485/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
6486#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
6487#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
6488#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
6489#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
6490
6491/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
6492#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
6493#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
6494#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
6495#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
6496
6497/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
6498#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
6499#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
6500#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
6501#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
6502
6503/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
6504#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
6505#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
6506#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
6507#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
6508
6509/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
6510#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
6511#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
6512#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
6513#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
6514
6515/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
6516#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
6517#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
6518#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
6519#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
6520
6521/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
6522#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
6523#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
6524#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
6525#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
6526
6527/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
6528#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
6529#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
6530#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
6531#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
6532
6533/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
6534#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
6535#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
6536#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
6537#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
6538
6539/* Register: GPIO_DETECTMODE */
6540/* Description: Select between default DETECT signal behaviour and LDETECT mode */
6541
6542/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
6543#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
6544#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
6545#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
6546#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
6547
6548/* Register: GPIO_PIN_CNF */
6549/* Description: Description collection[0]: Configuration of GPIO pins */
6550
6551/* Bits 17..16 : Pin sensing mechanism */
6552#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
6553#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
6554#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
6555#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
6556#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
6557
6558/* Bits 10..8 : Drive configuration */
6559#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
6560#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
6561#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
6562#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
6563#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
6564#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
6565#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
6566#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
6567#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
6568#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
6569
6570/* Bits 3..2 : Pull configuration */
6571#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
6572#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
6573#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
6574#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
6575#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
6576
6577/* Bit 1 : Connect or disconnect input buffer */
6578#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
6579#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
6580#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
6581#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
6582
6583/* Bit 0 : Pin direction. Same physical register as DIR register */
6584#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
6585#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
6586#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
6587#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
6588
6589
6590/* Peripheral: PDM */
6591/* Description: Pulse Density Modulation (Digital Microphone) Interface */
6592
6593/* Register: PDM_INTEN */
6594/* Description: Enable or disable interrupt */
6595
6596/* Bit 2 : Enable or disable interrupt for END event */
6597#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
6598#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
6599#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
6600#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
6601
6602/* Bit 1 : Enable or disable interrupt for STOPPED event */
6603#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6604#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6605#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
6606#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
6607
6608/* Bit 0 : Enable or disable interrupt for STARTED event */
6609#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6610#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
6611#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
6612#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
6613
6614/* Register: PDM_INTENSET */
6615/* Description: Enable interrupt */
6616
6617/* Bit 2 : Write '1' to Enable interrupt for END event */
6618#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
6619#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
6620#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
6621#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
6622#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
6623
6624/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
6625#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6626#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6627#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6628#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6629#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
6630
6631/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
6632#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6633#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
6634#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
6635#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
6636#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
6637
6638/* Register: PDM_INTENCLR */
6639/* Description: Disable interrupt */
6640
6641/* Bit 2 : Write '1' to Disable interrupt for END event */
6642#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
6643#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
6644#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
6645#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
6646#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
6647
6648/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
6649#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
6650#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
6651#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
6652#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
6653#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
6654
6655/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
6656#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
6657#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
6658#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
6659#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
6660#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
6661
6662/* Register: PDM_ENABLE */
6663/* Description: PDM module enable register */
6664
6665/* Bit 0 : Enable or disable PDM module */
6666#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
6667#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
6668#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
6669#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
6670
6671/* Register: PDM_PDMCLKCTRL */
6672/* Description: PDM clock generator control */
6673
6674/* Bits 31..0 : PDM_CLK frequency */
6675#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
6676#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
6677#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
6678#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
6679#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
6680
6681/* Register: PDM_MODE */
6682/* Description: Defines the routing of the connected PDM microphones' signals */
6683
6684/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
6685#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
6686#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
6687#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
6688#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
6689
6690/* Bit 0 : Mono or stereo operation */
6691#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
6692#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
6693#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
6694#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
6695
6696/* Register: PDM_GAINL */
6697/* Description: Left output gain adjustment */
6698
6699/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust */
6700#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
6701#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
6702#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6703#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6704#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6705
6706/* Register: PDM_GAINR */
6707/* Description: Right output gain adjustment */
6708
6709/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
6710#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
6711#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
6712#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
6713#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
6714#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
6715
6716/* Register: PDM_PSEL_CLK */
6717/* Description: Pin number configuration for PDM CLK signal */
6718
6719/* Bit 31 : Connection */
6720#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6721#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6722#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
6723#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
6724
6725/* Bits 4..0 : Pin number */
6726#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
6727#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
6728
6729/* Register: PDM_PSEL_DIN */
6730/* Description: Pin number configuration for PDM DIN signal */
6731
6732/* Bit 31 : Connection */
6733#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
6734#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
6735#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
6736#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
6737
6738/* Bits 4..0 : Pin number */
6739#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
6740#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
6741
6742/* Register: PDM_SAMPLE_PTR */
6743/* Description: RAM address pointer to write samples to with EasyDMA */
6744
6745/* Bits 31..0 : Address to write PDM samples to over DMA */
6746#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
6747#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
6748
6749/* Register: PDM_SAMPLE_MAXCNT */
6750/* Description: Number of samples to allocate memory for in EasyDMA mode */
6751
6752/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
6753#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
6754#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
6755
6756
6757/* Peripheral: POWER */
6758/* Description: Power control */
6759
6760/* Register: POWER_INTENSET */
6761/* Description: Enable interrupt */
6762
6763/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
6764#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6765#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6766#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6767#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6768#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
6769
6770/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
6771#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6772#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6773#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6774#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6775#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
6776
6777/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
6778#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6779#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6780#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6781#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6782#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
6783
6784/* Register: POWER_INTENCLR */
6785/* Description: Disable interrupt */
6786
6787/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
6788#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
6789#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
6790#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
6791#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
6792#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
6793
6794/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
6795#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
6796#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
6797#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
6798#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
6799#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
6800
6801/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
6802#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
6803#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
6804#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
6805#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
6806#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
6807
6808/* Register: POWER_RESETREAS */
6809/* Description: Reset reason */
6810
6811/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
6812#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
6813#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
6814#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
6815#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
6816
6817/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
6818#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
6819#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
6820#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
6821#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
6822
6823/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
6824#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
6825#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
6826#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
6827#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
6828
6829/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
6830#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
6831#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
6832#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
6833#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
6834
6835/* Bit 3 : Reset from CPU lock-up detected */
6836#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
6837#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
6838#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
6839#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
6840
6841/* Bit 2 : Reset from soft reset detected */
6842#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
6843#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
6844#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
6845#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
6846
6847/* Bit 1 : Reset from watchdog detected */
6848#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
6849#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
6850#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
6851#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
6852
6853/* Bit 0 : Reset from pin-reset detected */
6854#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
6855#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
6856#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
6857#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
6858
6859/* Register: POWER_RAMSTATUS */
6860/* Description: Deprecated register - RAM status register */
6861
6862/* Bit 3 : RAM block 3 is on or off/powering up */
6863#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
6864#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
6865#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
6866#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
6867
6868/* Bit 2 : RAM block 2 is on or off/powering up */
6869#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
6870#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
6871#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
6872#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
6873
6874/* Bit 1 : RAM block 1 is on or off/powering up */
6875#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
6876#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
6877#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
6878#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
6879
6880/* Bit 0 : RAM block 0 is on or off/powering up */
6881#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
6882#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
6883#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
6884#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
6885
6886/* Register: POWER_SYSTEMOFF */
6887/* Description: System OFF register */
6888
6889/* Bit 0 : Enable System OFF mode */
6890#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
6891#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
6892#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
6893
6894/* Register: POWER_POFCON */
6895/* Description: Power failure comparator configuration */
6896
6897/* Bits 4..1 : Power failure comparator threshold setting */
6898#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
6899#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
6900#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
6901#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
6902#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
6903#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
6904#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
6905#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
6906#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
6907#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
6908#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
6909#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
6910#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
6911#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
6912
6913/* Bit 0 : Enable or disable power failure comparator */
6914#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
6915#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
6916#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
6917#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
6918
6919/* Register: POWER_GPREGRET */
6920/* Description: General purpose retention register */
6921
6922/* Bits 7..0 : General purpose retention register */
6923#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6924#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6925
6926/* Register: POWER_GPREGRET2 */
6927/* Description: General purpose retention register */
6928
6929/* Bits 7..0 : General purpose retention register */
6930#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
6931#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
6932
6933/* Register: POWER_RAMON */
6934/* Description: Deprecated register - RAM on/off register (this register is retained) */
6935
6936/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
6937#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
6938#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
6939#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
6940#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
6941
6942/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
6943#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
6944#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
6945#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
6946#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
6947
6948/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
6949#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
6950#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
6951#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
6952#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
6953
6954/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
6955#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
6956#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
6957#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
6958#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
6959
6960/* Register: POWER_RAMONB */
6961/* Description: Deprecated register - RAM on/off register (this register is retained) */
6962
6963/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
6964#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
6965#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
6966#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
6967#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
6968
6969/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
6970#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
6971#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
6972#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
6973#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
6974
6975/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
6976#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
6977#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
6978#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
6979#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
6980
6981/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
6982#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
6983#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
6984#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
6985#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
6986
6987/* Register: POWER_DCDCEN */
6988/* Description: DC/DC enable register */
6989
6990/* Bit 0 : Enable or disable DC/DC converter */
6991#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
6992#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
6993#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
6994#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
6995
6996/* Register: POWER_RAM_POWER */
6997/* Description: Description cluster[0]: RAM0 power control register */
6998
6999/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
7000#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7001#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7002#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
7003#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
7004
7005/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
7006#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7007#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7008#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
7009#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
7010
7011/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
7012#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7013#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7014#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
7015#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
7016
7017/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
7018#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7019#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7020#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
7021#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
7022
7023/* Register: POWER_RAM_POWERSET */
7024/* Description: Description cluster[0]: RAM0 power control set register */
7025
7026/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7027#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7028#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7029#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
7030
7031/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7032#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7033#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7034#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
7035
7036/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7037#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7038#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7039#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
7040
7041/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7042#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7043#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7044#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
7045
7046/* Register: POWER_RAM_POWERCLR */
7047/* Description: Description cluster[0]: RAM0 power control clear register */
7048
7049/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
7050#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
7051#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
7052#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
7053
7054/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
7055#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
7056#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
7057#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
7058
7059/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
7060#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
7061#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
7062#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
7063
7064/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
7065#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
7066#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
7067#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
7068
7069
7070/* Peripheral: PPI */
7071/* Description: Programmable Peripheral Interconnect */
7072
7073/* Register: PPI_CHEN */
7074/* Description: Channel enable register */
7075
7076/* Bit 31 : Enable or disable channel 31 */
7077#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
7078#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
7079#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
7080#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
7081
7082/* Bit 30 : Enable or disable channel 30 */
7083#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
7084#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
7085#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
7086#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
7087
7088/* Bit 29 : Enable or disable channel 29 */
7089#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
7090#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
7091#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
7092#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
7093
7094/* Bit 28 : Enable or disable channel 28 */
7095#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
7096#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
7097#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
7098#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
7099
7100/* Bit 27 : Enable or disable channel 27 */
7101#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
7102#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
7103#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
7104#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
7105
7106/* Bit 26 : Enable or disable channel 26 */
7107#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
7108#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
7109#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
7110#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
7111
7112/* Bit 25 : Enable or disable channel 25 */
7113#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
7114#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
7115#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
7116#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
7117
7118/* Bit 24 : Enable or disable channel 24 */
7119#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
7120#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
7121#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
7122#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
7123
7124/* Bit 23 : Enable or disable channel 23 */
7125#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
7126#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
7127#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
7128#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
7129
7130/* Bit 22 : Enable or disable channel 22 */
7131#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
7132#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
7133#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
7134#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
7135
7136/* Bit 21 : Enable or disable channel 21 */
7137#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
7138#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
7139#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
7140#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
7141
7142/* Bit 20 : Enable or disable channel 20 */
7143#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
7144#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
7145#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
7146#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
7147
7148/* Bit 19 : Enable or disable channel 19 */
7149#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
7150#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
7151#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
7152#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
7153
7154/* Bit 18 : Enable or disable channel 18 */
7155#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
7156#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
7157#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
7158#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
7159
7160/* Bit 17 : Enable or disable channel 17 */
7161#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
7162#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
7163#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
7164#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
7165
7166/* Bit 16 : Enable or disable channel 16 */
7167#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
7168#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
7169#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
7170#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
7171
7172/* Bit 15 : Enable or disable channel 15 */
7173#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
7174#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
7175#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
7176#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
7177
7178/* Bit 14 : Enable or disable channel 14 */
7179#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
7180#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
7181#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
7182#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
7183
7184/* Bit 13 : Enable or disable channel 13 */
7185#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
7186#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
7187#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
7188#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
7189
7190/* Bit 12 : Enable or disable channel 12 */
7191#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
7192#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
7193#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
7194#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
7195
7196/* Bit 11 : Enable or disable channel 11 */
7197#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
7198#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
7199#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
7200#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
7201
7202/* Bit 10 : Enable or disable channel 10 */
7203#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
7204#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
7205#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
7206#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
7207
7208/* Bit 9 : Enable or disable channel 9 */
7209#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
7210#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
7211#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
7212#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
7213
7214/* Bit 8 : Enable or disable channel 8 */
7215#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
7216#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
7217#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
7218#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
7219
7220/* Bit 7 : Enable or disable channel 7 */
7221#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
7222#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
7223#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
7224#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
7225
7226/* Bit 6 : Enable or disable channel 6 */
7227#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
7228#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
7229#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
7230#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
7231
7232/* Bit 5 : Enable or disable channel 5 */
7233#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
7234#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
7235#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
7236#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
7237
7238/* Bit 4 : Enable or disable channel 4 */
7239#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
7240#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
7241#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
7242#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
7243
7244/* Bit 3 : Enable or disable channel 3 */
7245#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
7246#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
7247#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
7248#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
7249
7250/* Bit 2 : Enable or disable channel 2 */
7251#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
7252#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
7253#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
7254#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
7255
7256/* Bit 1 : Enable or disable channel 1 */
7257#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
7258#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
7259#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
7260#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
7261
7262/* Bit 0 : Enable or disable channel 0 */
7263#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
7264#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
7265#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
7266#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
7267
7268/* Register: PPI_CHENSET */
7269/* Description: Channel enable set register */
7270
7271/* Bit 31 : Channel 31 enable set register. Writing '0' has no effect */
7272#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
7273#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
7274#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
7275#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
7276#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
7277
7278/* Bit 30 : Channel 30 enable set register. Writing '0' has no effect */
7279#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
7280#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
7281#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
7282#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
7283#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
7284
7285/* Bit 29 : Channel 29 enable set register. Writing '0' has no effect */
7286#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
7287#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
7288#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
7289#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
7290#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
7291
7292/* Bit 28 : Channel 28 enable set register. Writing '0' has no effect */
7293#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
7294#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
7295#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
7296#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
7297#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
7298
7299/* Bit 27 : Channel 27 enable set register. Writing '0' has no effect */
7300#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
7301#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
7302#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
7303#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
7304#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
7305
7306/* Bit 26 : Channel 26 enable set register. Writing '0' has no effect */
7307#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
7308#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
7309#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
7310#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
7311#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
7312
7313/* Bit 25 : Channel 25 enable set register. Writing '0' has no effect */
7314#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
7315#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
7316#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
7317#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
7318#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
7319
7320/* Bit 24 : Channel 24 enable set register. Writing '0' has no effect */
7321#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
7322#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
7323#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
7324#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
7325#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
7326
7327/* Bit 23 : Channel 23 enable set register. Writing '0' has no effect */
7328#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
7329#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
7330#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
7331#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
7332#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
7333
7334/* Bit 22 : Channel 22 enable set register. Writing '0' has no effect */
7335#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
7336#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
7337#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
7338#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
7339#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
7340
7341/* Bit 21 : Channel 21 enable set register. Writing '0' has no effect */
7342#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
7343#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
7344#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
7345#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
7346#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
7347
7348/* Bit 20 : Channel 20 enable set register. Writing '0' has no effect */
7349#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
7350#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
7351#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
7352#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
7353#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
7354
7355/* Bit 19 : Channel 19 enable set register. Writing '0' has no effect */
7356#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
7357#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
7358#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
7359#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
7360#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
7361
7362/* Bit 18 : Channel 18 enable set register. Writing '0' has no effect */
7363#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
7364#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
7365#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
7366#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
7367#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
7368
7369/* Bit 17 : Channel 17 enable set register. Writing '0' has no effect */
7370#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
7371#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
7372#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
7373#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
7374#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
7375
7376/* Bit 16 : Channel 16 enable set register. Writing '0' has no effect */
7377#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
7378#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
7379#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
7380#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
7381#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
7382
7383/* Bit 15 : Channel 15 enable set register. Writing '0' has no effect */
7384#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
7385#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
7386#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
7387#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
7388#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
7389
7390/* Bit 14 : Channel 14 enable set register. Writing '0' has no effect */
7391#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
7392#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
7393#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
7394#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
7395#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
7396
7397/* Bit 13 : Channel 13 enable set register. Writing '0' has no effect */
7398#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
7399#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
7400#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
7401#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
7402#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
7403
7404/* Bit 12 : Channel 12 enable set register. Writing '0' has no effect */
7405#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
7406#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
7407#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
7408#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
7409#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
7410
7411/* Bit 11 : Channel 11 enable set register. Writing '0' has no effect */
7412#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
7413#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
7414#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
7415#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
7416#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
7417
7418/* Bit 10 : Channel 10 enable set register. Writing '0' has no effect */
7419#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
7420#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
7421#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
7422#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
7423#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
7424
7425/* Bit 9 : Channel 9 enable set register. Writing '0' has no effect */
7426#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
7427#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
7428#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
7429#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
7430#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
7431
7432/* Bit 8 : Channel 8 enable set register. Writing '0' has no effect */
7433#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
7434#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
7435#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
7436#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
7437#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
7438
7439/* Bit 7 : Channel 7 enable set register. Writing '0' has no effect */
7440#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
7441#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
7442#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
7443#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
7444#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
7445
7446/* Bit 6 : Channel 6 enable set register. Writing '0' has no effect */
7447#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
7448#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
7449#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
7450#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
7451#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
7452
7453/* Bit 5 : Channel 5 enable set register. Writing '0' has no effect */
7454#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
7455#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
7456#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
7457#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
7458#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
7459
7460/* Bit 4 : Channel 4 enable set register. Writing '0' has no effect */
7461#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
7462#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
7463#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
7464#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
7465#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
7466
7467/* Bit 3 : Channel 3 enable set register. Writing '0' has no effect */
7468#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
7469#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
7470#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
7471#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
7472#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
7473
7474/* Bit 2 : Channel 2 enable set register. Writing '0' has no effect */
7475#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
7476#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
7477#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
7478#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
7479#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
7480
7481/* Bit 1 : Channel 1 enable set register. Writing '0' has no effect */
7482#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
7483#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
7484#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
7485#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
7486#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
7487
7488/* Bit 0 : Channel 0 enable set register. Writing '0' has no effect */
7489#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
7490#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
7491#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
7492#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
7493#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
7494
7495/* Register: PPI_CHENCLR */
7496/* Description: Channel enable clear register */
7497
7498/* Bit 31 : Channel 31 enable clear register. Writing '0' has no effect */
7499#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
7500#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
7501#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
7502#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
7503#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
7504
7505/* Bit 30 : Channel 30 enable clear register. Writing '0' has no effect */
7506#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
7507#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
7508#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
7509#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
7510#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
7511
7512/* Bit 29 : Channel 29 enable clear register. Writing '0' has no effect */
7513#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
7514#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
7515#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
7516#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
7517#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
7518
7519/* Bit 28 : Channel 28 enable clear register. Writing '0' has no effect */
7520#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
7521#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
7522#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
7523#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
7524#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
7525
7526/* Bit 27 : Channel 27 enable clear register. Writing '0' has no effect */
7527#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
7528#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
7529#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
7530#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
7531#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
7532
7533/* Bit 26 : Channel 26 enable clear register. Writing '0' has no effect */
7534#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
7535#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
7536#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
7537#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
7538#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
7539
7540/* Bit 25 : Channel 25 enable clear register. Writing '0' has no effect */
7541#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
7542#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
7543#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
7544#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
7545#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
7546
7547/* Bit 24 : Channel 24 enable clear register. Writing '0' has no effect */
7548#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
7549#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
7550#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
7551#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
7552#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
7553
7554/* Bit 23 : Channel 23 enable clear register. Writing '0' has no effect */
7555#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
7556#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
7557#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
7558#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
7559#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
7560
7561/* Bit 22 : Channel 22 enable clear register. Writing '0' has no effect */
7562#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
7563#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
7564#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
7565#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
7566#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
7567
7568/* Bit 21 : Channel 21 enable clear register. Writing '0' has no effect */
7569#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
7570#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
7571#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
7572#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
7573#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
7574
7575/* Bit 20 : Channel 20 enable clear register. Writing '0' has no effect */
7576#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
7577#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
7578#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
7579#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
7580#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
7581
7582/* Bit 19 : Channel 19 enable clear register. Writing '0' has no effect */
7583#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
7584#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
7585#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
7586#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
7587#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
7588
7589/* Bit 18 : Channel 18 enable clear register. Writing '0' has no effect */
7590#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
7591#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
7592#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
7593#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
7594#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
7595
7596/* Bit 17 : Channel 17 enable clear register. Writing '0' has no effect */
7597#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
7598#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
7599#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
7600#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
7601#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
7602
7603/* Bit 16 : Channel 16 enable clear register. Writing '0' has no effect */
7604#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
7605#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
7606#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
7607#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
7608#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
7609
7610/* Bit 15 : Channel 15 enable clear register. Writing '0' has no effect */
7611#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
7612#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
7613#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
7614#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
7615#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
7616
7617/* Bit 14 : Channel 14 enable clear register. Writing '0' has no effect */
7618#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
7619#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
7620#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
7621#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
7622#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
7623
7624/* Bit 13 : Channel 13 enable clear register. Writing '0' has no effect */
7625#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
7626#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
7627#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
7628#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
7629#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
7630
7631/* Bit 12 : Channel 12 enable clear register. Writing '0' has no effect */
7632#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
7633#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
7634#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
7635#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
7636#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
7637
7638/* Bit 11 : Channel 11 enable clear register. Writing '0' has no effect */
7639#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
7640#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
7641#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
7642#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
7643#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
7644
7645/* Bit 10 : Channel 10 enable clear register. Writing '0' has no effect */
7646#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
7647#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
7648#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
7649#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
7650#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
7651
7652/* Bit 9 : Channel 9 enable clear register. Writing '0' has no effect */
7653#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
7654#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
7655#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
7656#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
7657#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
7658
7659/* Bit 8 : Channel 8 enable clear register. Writing '0' has no effect */
7660#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
7661#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
7662#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
7663#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
7664#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
7665
7666/* Bit 7 : Channel 7 enable clear register. Writing '0' has no effect */
7667#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
7668#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
7669#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
7670#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
7671#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
7672
7673/* Bit 6 : Channel 6 enable clear register. Writing '0' has no effect */