424 files changed, 159370 insertions, 0 deletions

diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/driver.mk b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/driver.mk
new file mode 100644
index 000000000..83db5502f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_CAN TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
+endif
+else
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
+endif
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CAN
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
new file mode 100644
index 000000000..4deb9dd0f
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.c
@@ -0,0 +1,825 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    CAN/hal_can_lld.c
+ * @brief   GD32 CAN subsystem low level driver source.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*
+ * Addressing differences in the headers, they seem unable to agree on names.
+ */
+#if GD32_CAN_USE_CAN0
+#if !defined(CAN0)
+#define CAN0 CAN
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief CAN0 driver identifier.*/
+#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
+CANDriver CAND1;
+#endif
+
+/** @brief CAN1 driver identifier.*/
+#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
+CANDriver CAND2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+/**
+ * @brief   Programs the filters of CAN 1 and CAN 2.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] can2sb    number of the first filter assigned to CAN1
+ * @param[in] num       number of entries in the filters array, if zero then
+ *                      a default filter is programmed
+ * @param[in] cfp       pointer to the filters array, can be @p NULL if
+ *                      (num == 0)
+ *
+ * @notapi
+ */
+static void can_lld_set_filters(CANDriver* canp,
+                                uint32_t can2sb,
+                                uint32_t num,
+                                const CANFilter *cfp) {
+
+#if GD32_CAN_USE_CAN1
+  if (canp == &CAND2) {
+    /* Set handle to CAN0, because CAN0 manages the filters of CAN1.*/
+    canp = &CAND1;
+  }
+#endif
+
+  /* Temporarily enabling CAN clock.*/
+#if GD32_CAN_USE_CAN0
+  if (canp == &CAND1) {
+    rcuEnableCAN0(true);
+    /* Filters initialization.*/
+    canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | CAN_FCTL_FLD;
+    canp->can->FCTL = (canp->can->FCTL & 0xFFFF0000) | (can2sb << 8) | CAN_FCTL_FLD;
+  }
+#endif
+
+  if (num > 0) {
+    uint32_t i, fmask;
+
+    /* All filters cleared.*/
+    canp->can->FW = 0;
+    canp->can->FMCFG = 0;
+    canp->can->FSCFG = 0;
+    canp->can->FAFIFO = 0;
+
+#if GD32_CAN_USE_CAN0
+    if (canp == &CAND1) {
+      for (i = 0; i < GD32_CAN_MAX_FILTERS; i++) {
+        canp->can->sFilterRegister[i].FR1 = 0;
+        canp->can->sFilterRegister[i].FR2 = 0;
+      }
+    }
+#endif
+
+    /* Scanning the filters array.*/
+    for (i = 0; i < num; i++) {
+      fmask = 1 << cfp->filter;
+      if (cfp->mode)
+        canp->can->FMCFG |= fmask;
+      if (cfp->scale)
+        canp->can->FSCFG |= fmask;
+      if (cfp->assignment)
+        canp->can->FAFIFO |= fmask;
+      canp->can->sFilterRegister[cfp->filter].FR1 = cfp->register1;
+      canp->can->sFilterRegister[cfp->filter].FR2 = cfp->register2;
+      canp->can->FW |= fmask;
+      cfp++;
+    }
+  }
+  else {
+    /* Setting up a single default filter that enables everything for both
+       CANs.*/
+    canp->can->sFilterRegister[0].FR1 = 0;
+    canp->can->sFilterRegister[0].FR2 = 0;
+#if GD32_CAN_USE_CAN1
+    if (canp == &CAND1) {
+      canp->can->sFilterRegister[can2sb].FR1 = 0;
+      canp->can->sFilterRegister[can2sb].FR2 = 0;
+    }
+#endif
+    canp->can->FMCFG = 0;
+    canp->can->FAFIFO = 0;
+    canp->can->FSCFG = 1;
+    canp->can->FW = 1;
+#if GD32_CAN_USE_CAN1
+    if (canp == &CAND1) {
+      canp->can->FSCFG |= 1 << can2sb;
+      canp->can->FW |= 1 << can2sb;
+    }
+#endif
+  }
+  canp->can->FCTL &= ~CAN_FCTL_FLD;
+
+  /* Clock disabled, it will be enabled again in can_lld_start().*/
+  /* Temporarily enabling CAN clock.*/
+#if GD32_CAN_USE_CAN0
+  if (canp == &CAND1) {
+    rcuDisableCAN0();
+  }
+#endif
+}
+
+/**
+ * @brief   Common TX ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_tx_handler(CANDriver *canp) {
+  uint32_t tstat;
+  eventflags_t flags;
+
+  /* Clearing IRQ sources.*/
+  tstat = canp->can->TSTAT;
+  canp->can->TSTAT = tstat;
+
+  /* Flags to be signaled through the TX event source.*/
+  flags = 0U;
+
+  /* Checking mailbox 0.*/
+  if ((tstat & CAN_TSTAT_MTF0) != 0U) {
+    if ((tstat & (CAN_TSTAT_MAL0 | CAN_TSTAT_MTE0)) != 0U) {
+      flags |= CAN_MAILBOX_TO_MASK(1U) << 16U;
+    }
+    else {
+      flags |= CAN_MAILBOX_TO_MASK(1U);
+    }
+  }
+
+  /* Checking mailbox 1.*/
+  if ((tstat & CAN_TSTAT_MTF1) != 0U) {
+    if ((tstat & (CAN_TSTAT_MAL1 | CAN_TSTAT_MTE1)) != 0U) {
+      flags |= CAN_MAILBOX_TO_MASK(2U) << 16U;
+    }
+    else {
+      flags |= CAN_MAILBOX_TO_MASK(2U);
+    }
+  }
+
+  /* Checking mailbox 2.*/
+  if ((tstat & CAN_TSTAT_MTF2) != 0U) {
+    if ((tstat & (CAN_TSTAT_MAL2 | CAN_TSTAT_MTE2)) != 0U) {
+      flags |= CAN_MAILBOX_TO_MASK(3U) << 16U;
+    }
+    else {
+      flags |= CAN_MAILBOX_TO_MASK(3U);
+    }
+  }
+
+  /* Signaling flags and waking up threads waiting for a transmission slot.*/
+  _can_tx_empty_isr(canp, flags);
+}
+
+/**
+ * @brief   Common RX0 ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_rx0_handler(CANDriver *canp) {
+  uint32_t rfifo0;
+
+  rfifo0 = canp->can->RFIFO0;
+  if ((rfifo0 & CAN_RFIFO0_RFL0) > 0) {
+    /* No more receive events until the queue 0 has been emptied.*/
+    canp->can->INTEN &= ~CAN_INTEN_RFNEIE0;
+    _can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(1U));
+  }
+  if ((rfifo0 & CAN_RFIFO0_RFO0) > 0) {
+    /* Overflow events handling.*/
+    canp->can->RFIFO0 = CAN_RFIFO0_RFO0;
+    _can_error_isr(canp, CAN_OVERFLOW_ERROR);
+  }
+}
+
+/**
+ * @brief   Common RX1 ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_rx1_handler(CANDriver *canp) {
+  uint32_t rfifo1;
+
+  rfifo1 = canp->can->RFIFO1;
+  if ((rfifo1 & CAN_RFIFO1_RFL1) > 0) {
+    /* No more receive events until the queue 0 has been emptied.*/
+    canp->can->INTEN &= ~CAN_INTEN_RFNEIE1;
+    _can_rx_full_isr(canp, CAN_MAILBOX_TO_MASK(2U));
+  }
+  if ((rfifo1 & CAN_RFIFO1_RFO1) > 0) {
+    /* Overflow events handling.*/
+    canp->can->RFIFO1 = CAN_RFIFO1_RFO1;
+    _can_error_isr(canp, CAN_OVERFLOW_ERROR);
+  }
+}
+
+/**
+ * @brief   Common SCE ISR handler.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+static void can_lld_sce_handler(CANDriver *canp) {
+  uint32_t stat;
+
+  /* Clearing IRQ sources.*/
+  stat = canp->can->STAT;
+  canp->can->STAT = stat;
+
+  /* Wakeup event.*/
+#if CAN_USE_SLEEP_MODE
+  if (stat & CAN_STAT_WUIF) {
+    canp->state = CAN_READY;
+    canp->can->CTL &= ~CAN_CTL_SLPWMOD;
+    _can_wakeup_isr(canp);
+  }
+#endif /* CAN_USE_SLEEP_MODE */
+  /* Error event.*/
+  if (stat & CAN_STAT_ERRIF) {
+    eventflags_t flags;
+    uint32_t err = canp->can->ERR;
+
+#if GD32_CAN_REPORT_ALL_ERRORS
+    flags = (eventflags_t)(err & 7);
+    if ((err & CAN_ERR_ERRN) > 0)
+      flags |= CAN_FRAMING_ERROR;
+#else
+    flags = 0;
+#endif
+
+    /* The content of the ESR register is copied unchanged in the upper
+       half word of the listener flags mask.*/
+    _can_error_isr(canp, flags | (eventflags_t)(err << 16U));
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if GD32_CAN_USE_CAN0 || defined(__DOXYGEN__)
+#if !defined(GD32_CAN0_TX_HANDLER)
+#error "GD32_CAN0_TX_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_RX0_HANDLER)
+#error "GD32_CAN0_RX0_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_RX1_HANDLER)
+#error "GD32_CAN0_RX1_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_EWMC_HANDLER)
+#error "GD32_CAN0_EWMC_HANDLER not defined"
+#endif
+
+/**
+ * @brief   CAN0 TX interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_tx_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN0 RX0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx0_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN0 RX1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx1_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN0 SCE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_sce_handler(&CAND1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* GD32_CAN_USE_CAN0 */
+
+#if GD32_CAN_USE_CAN1 || defined(__DOXYGEN__)
+#if !defined(GD32_CAN0_TX_HANDLER)
+#error "GD32_CAN0_TX_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_RX0_HANDLER)
+#error "GD32_CAN0_RX0_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_RX1_HANDLER)
+#error "GD32_CAN0_RX1_HANDLER not defined"
+#endif
+#if !defined(GD32_CAN0_EWMC_HANDLER)
+#error "GD32_CAN0_EWMC_HANDLER not defined"
+#endif
+
+/**
+ * @brief   CAN1 TX interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_TX_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_tx_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN1 RX0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_RX0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx0_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN1 RX1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_RX1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_rx1_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   CAN1 SCE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_CAN0_EWMC_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  can_lld_sce_handler(&CAND2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* GD32_CAN_USE_CAN1 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level CAN driver initialization.
+ *
+ * @notapi
+ */
+void can_lld_init(void) {
+
+#if GD32_CAN_USE_CAN0
+  /* Driver initialization.*/
+  canObjectInit(&CAND1);
+  CAND1.can = CAN0;
+    eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN0_IRQ_PRIORITY, GD32_CAN_CAN0_IRQ_TRIGGER);
+#endif
+
+#if GD32_CAN_USE_CAN1
+  /* Driver initialization.*/
+  canObjectInit(&CAND2);
+  CAND2.can = CAN1;
+    eclicEnableVector(GD32_CAN0_TX_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_RX0_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_RX1_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
+    eclicEnableVector(GD32_CAN0_EWMC_NUMBER, GD32_CAN_CAN1_IRQ_PRIORITY, GD32_CAN_CAN1_IRQ_TRIGGER);
+#endif
+
+  /* Filters initialization.*/
+#if GD32_CAN_USE_CAN0
+#if GD32_HAS_CAN1
+  can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS / 2, 0, NULL);
+#else
+  can_lld_set_filters(&CAND1, GD32_CAN_MAX_FILTERS, 0, NULL);
+#endif
+#endif
+}
+
+/**
+ * @brief   Configures and activates the CAN peripheral.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_start(CANDriver *canp) {
+
+  /* Clock activation.*/
+#if GD32_CAN_USE_CAN0
+  if (&CAND1 == canp) {
+    rcuEnableCAN0(true);
+  }
+#endif
+
+#if GD32_CAN_USE_CAN1
+  if (&CAND2 == canp) {
+    rcuEnableCAN0(true);    /* CAN 2 requires CAN0, so enabling it first.*/
+    rcuEnableCAN1(true);
+  }
+#endif
+
+  /* Configuring CAN. */
+  canp->can->CTL = CAN_CTL_IWMOD;
+  while ((canp->can->STAT & CAN_STAT_IWS) == 0)
+    osalThreadSleepS(1);
+  canp->can->BT = canp->config->bt;
+  canp->can->CTL = canp->config->ctl;
+
+  /* Interrupt sources initialization.*/
+#if GD32_CAN_REPORT_ALL_ERRORS
+  canp->can->INTEN = CAN_INTEN_TMEIE  | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
+                   CAN_INTEN_WIE  | CAN_INTEN_ERRIE  | CAN_INTEN_ERRNIE  |
+                   CAN_INTEN_BOIE  | CAN_INTEN_PERRIE  | CAN_INTEN_WERRIE  |
+                   CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
+#else
+  canp->can->INTEN = CAN_INTEN_TMEIE  | CAN_INTEN_RFNEIE0 | CAN_INTEN_RFNEIE1 |
+                   CAN_INTEN_WIE  | CAN_INTEN_ERRIE  |
+                   CAN_INTEN_BOIE  | CAN_INTEN_PERRIE  | CAN_INTEN_WERRIE  |
+                   CAN_INTEN_RFOIE0 | CAN_INTEN_RFOIE1;
+#endif
+}
+
+/**
+ * @brief   Deactivates the CAN peripheral.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_stop(CANDriver *canp) {
+
+  /* If in ready state then disables the CAN peripheral.*/
+  if (canp->state == CAN_READY) {
+#if GD32_CAN_USE_CAN0
+    if (&CAND1 == canp) {
+      CAN0->CTL = 0x00010002;                   /* Register reset value.    */
+      CAN0->INTEN = 0x00000000;                   /* All sources disabled.    */
+#if GD32_CAN_USE_CAN1
+      /* If CAND2 is stopped then CAN0 clock is stopped here.*/
+      if (CAND2.state == CAN_STOP)
+#endif
+      {
+        rcuDisableCAN0();
+      }
+    }
+#endif
+
+#if GD32_CAN_USE_CAN1
+    if (&CAND2 == canp) {
+      CAN1->CTL = 0x00010002;                   /* Register reset value.    */
+      CAN1->INTEN = 0x00000000;                   /* All sources disabled.    */
+#if GD32_CAN_USE_CAN0
+      /* If CAND1 is stopped then CAN0 clock is stopped here.*/
+      if (CAND1.state == CAN_STOP)
+#endif
+      {
+        rcuDisableCAN0();
+      }
+      rcuDisableCAN1();
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Determines whether a frame can be transmitted.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return              The queue space availability.
+ * @retval false        no space in the transmit queue.
+ * @retval true         transmit slot available.
+ *
+ * @notapi
+ */
+bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox) {
+
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    return (canp->can->TSTAT & CAN_TSTAT_TME) != 0;
+  case 1:
+    return (canp->can->TSTAT & CAN_TSTAT_TME0) != 0;
+  case 2:
+    return (canp->can->TSTAT & CAN_TSTAT_TME1) != 0;
+  case 3:
+    return (canp->can->TSTAT & CAN_TSTAT_TME2) != 0;
+  default:
+    return false;
+  }
+}
+
+/**
+ * @brief   Inserts a frame into the transmit queue.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] ctfp      pointer to the CAN frame to be transmitted
+ * @param[in] mailbox   mailbox number,  @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @notapi
+ */
+void can_lld_transmit(CANDriver *canp,
+                      canmbx_t mailbox,
+                      const CANTxFrame *ctfp) {
+  uint32_t tmi;
+  CAN_TxMailBox_TypeDef *tmbp;
+
+  /* Pointer to a free transmission mailbox.*/
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    tmbp = &canp->can->sTxMailBox[(canp->can->TSTAT & CAN_TSTAT_NUM) >> 24];
+    break;
+  case 1:
+    tmbp = &canp->can->sTxMailBox[0];
+    break;
+  case 2:
+    tmbp = &canp->can->sTxMailBox[1];
+    break;
+  case 3:
+    tmbp = &canp->can->sTxMailBox[2];
+    break;
+  default:
+    return;
+  }
+
+  /* Preparing the message.*/
+  if (ctfp->IDE)
+    tmi = ((uint32_t)ctfp->EID << 3) | ((uint32_t)ctfp->RTR << 1) |
+          CAN_TMI0_FF;
+  else
+    tmi = ((uint32_t)ctfp->SID << 21) | ((uint32_t)ctfp->RTR << 1);
+  tmbp->TMP = ctfp->DLC;
+  tmbp->TMDATA0 = ctfp->data32[0];
+  tmbp->TMDATA1 = ctfp->data32[1];
+  tmbp->TMI  = tmi | CAN_TMI0_TEN;
+}
+
+/**
+ * @brief   Determines whether a frame has been received.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ *
+ * @return              The queue space availability.
+ * @retval false        no space in the transmit queue.
+ * @retval true         transmit slot available.
+ *
+ * @notapi
+ */
+bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox) {
+
+  switch (mailbox) {
+  case CAN_ANY_MAILBOX:
+    return ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0 ||
+            (canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0);
+  case 1:
+    return (canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0;
+  case 2:
+    return (canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0;
+  default:
+    return false;
+  }
+}
+
+/**
+ * @brief   Receives a frame from the input queue.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number, @p CAN_ANY_MAILBOX for any mailbox
+ * @param[out] crfp     pointer to the buffer where the CAN frame is copied
+ *
+ * @notapi
+ */
+void can_lld_receive(CANDriver *canp,
+                     canmbx_t mailbox,
+                     CANRxFrame *crfp) {
+  uint32_t rfifomi, rfifomp;
+
+  if (mailbox == CAN_ANY_MAILBOX) {
+    if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) != 0)
+      mailbox = 1;
+    else if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) != 0)
+      mailbox = 2;
+    else {
+      /* Should not happen, do nothing.*/
+      return;
+    }
+  }
+  switch (mailbox) {
+  case 1:
+    /* Fetches the message.*/
+    rfifomi  = canp->can->sFIFOMailBox[0].RFIFOMI;
+    rfifomp = canp->can->sFIFOMailBox[0].RFIFOMP;
+    crfp->data32[0] = canp->can->sFIFOMailBox[0].RFIFOMDATA0;
+    crfp->data32[1] = canp->can->sFIFOMailBox[0].RFIFOMDATA1;
+
+    /* Releases the mailbox.*/
+    canp->can->RFIFO0 = CAN_RFIFO0_RFD0;
+
+    /* If the queue is empty re-enables the interrupt in order to generate
+       events again.*/
+    if ((canp->can->RFIFO0 & CAN_RFIFO0_RFL0) == 0)
+      canp->can->INTEN |= CAN_INTEN_RFNEIE0;
+    break;
+  case 2:
+    /* Fetches the message.*/
+    rfifomi  = canp->can->sFIFOMailBox[1].RFIFOMI;
+    rfifomp = canp->can->sFIFOMailBox[1].RFIFOMP;
+    crfp->data32[0] = canp->can->sFIFOMailBox[1].RFIFOMDATA0;
+    crfp->data32[1] = canp->can->sFIFOMailBox[1].RFIFOMDATA1;
+
+    /* Releases the mailbox.*/
+    canp->can->RFIFO1 = CAN_RFIFO1_RFD1;
+
+    /* If the queue is empty re-enables the interrupt in order to generate
+       events again.*/
+    if ((canp->can->RFIFO1 & CAN_RFIFO1_RFL1) == 0)
+      canp->can->INTEN |= CAN_INTEN_RFNEIE1;
+    break;
+  default:
+    /* Should not happen, do nothing.*/
+    return;
+  }
+
+  /* Decodes the various fields in the RX frame.*/
+  crfp->RTR = (rfifomi & CAN_RFIFOMI0_FT) >> 1;
+  crfp->IDE = (rfifomi & CAN_RFIFOMI0_FF) >> 2;
+  if (crfp->IDE)
+    crfp->EID = rfifomi >> 3;
+  else
+    crfp->SID = rfifomi >> 21;
+  crfp->DLC = rfifomp & CAN_RFIFOMP0_DLENC;
+  crfp->FMI = (uint8_t)(rfifomp >> 8);
+  crfp->TIME = (uint16_t)(rfifomp >> 16);
+}
+
+/**
+ * @brief   Tries to abort an ongoing transmission.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] mailbox   mailbox number
+ *
+ * @notapi
+ */
+void can_lld_abort(CANDriver *canp,
+                   canmbx_t mailbox) {
+
+  canp->can->TSTAT = 128U << ((mailbox - 1U) * 8U);
+}
+
+#if CAN_USE_SLEEP_MODE || defined(__DOXYGEN__)
+/**
+ * @brief   Enters the sleep mode.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_sleep(CANDriver *canp) {
+
+  canp->can->CTL |= CAN_CTL_SLPWMOD;
+}
+
+/**
+ * @brief   Enforces leaving the sleep mode.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ *
+ * @notapi
+ */
+void can_lld_wakeup(CANDriver *canp) {
+
+  canp->can->CTL &= ~CAN_CTL_SLPWMOD;
+}
+#endif /* CAN_USE_SLEEP_MODE */
+
+/**
+ * @brief   Programs the filters.
+ * @note    This is an GD32-specific API.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object
+ * @param[in] can2sb    number of the first filter assigned to CAN1
+ * @param[in] num       number of entries in the filters array, if zero then
+ *                      a default filter is programmed
+ * @param[in] cfp       pointer to the filters array, can be @p NULL if
+ *                      (num == 0)
+ *
+ * @api
+ */
+void canGD32SetFilters(CANDriver *canp, uint32_t can2sb,
+                        uint32_t num, const CANFilter *cfp) {
+
+#if GD32_CAN_USE_CAN1
+  osalDbgCheck((can2sb <= GD32_CAN_MAX_FILTERS) &&
+               (num <= GD32_CAN_MAX_FILTERS));
+#endif
+
+#if GD32_CAN_USE_CAN0
+  osalDbgAssert(CAND1.state == CAN_STOP, "invalid state");
+#endif
+#if GD32_CAN_USE_CAN1
+  osalDbgAssert(CAND2.state == CAN_STOP, "invalid state");
+#endif
+
+#if GD32_CAN_USE_CAN0
+  if (canp == &CAND1) {
+    can_lld_set_filters(canp, can2sb, num, cfp);
+  }
+#endif
+}
+
+#endif /* HAL_USE_CAN */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.h b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.h
new file mode 100644
index 000000000..f91ff1ba0
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CAN/hal_can_lld.h
@@ -0,0 +1,455 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    CAN/hal_can_lld.h
+ * @brief   GD32 CAN subsystem low level driver header.
+ *
+ * @addtogroup CAN
+ * @{
+ */
+
+#ifndef HAL_CAN_LLD_H
+#define HAL_CAN_LLD_H
+
+#if HAL_USE_CAN || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*
+ * The following macros from the ST header file are replaced with better
+ * equivalents.
+ */
+#undef CAN_BT_BAUDPSC
+#undef CAN_BT_BS1
+#undef CAN_BT_BS2
+#undef CAN_BT_SJW
+
+/**
+ * @brief   This switch defines whether the driver implementation supports
+ *          a low power switch mode with automatic an wakeup feature.
+ */
+#define CAN_SUPPORTS_SLEEP          TRUE
+
+/**
+ * @brief   This implementation supports three transmit mailboxes.
+ */
+#define CAN_TX_MAILBOXES            3
+
+/**
+ * @brief   This implementation supports two receive mailboxes.
+ */
+#define CAN_RX_MAILBOXES            2
+
+/**
+ * @name    CAN registers helper macros
+ * @{
+ */
+#define CAN_BT_BAUDPSC(n)          (n)         /**< @brief BRP field macro.*/
+#define CAN_BT_BS1(n)              ((n) << 16) /**< @brief TS1 field macro.*/
+#define CAN_BT_BS2(n)              ((n) << 20) /**< @brief TS2 field macro.*/
+#define CAN_BT_SJW(n)              ((n) << 24) /**< @brief SJW field macro.*/
+
+#define CAN_IDE_STD                 0           /**< @brief Standard id.    */
+#define CAN_IDE_EXT                 1           /**< @brief Extended id.    */
+
+#define CAN_RTR_DATA                0           /**< @brief Data frame.     */
+#define CAN_RTR_REMOTE              1           /**< @brief Remote frame.   */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   CAN pedantic errors report.
+ * @details Use of this option is IRQ-intensive.
+ */
+#if !defined(GD32_CAN_REPORT_ALL_ERRORS) || defined(__DOXYGEN__)
+#define GD32_CAN_REPORT_ALL_ERRORS         FALSE
+#endif
+
+/**
+ * @brief   CAN0 driver enable switch.
+ * @details If set to @p TRUE the support for CAN0 is included.
+ */
+#if !defined(GD32_CAN_USE_CAN0) || defined(__DOXYGEN__)
+#define GD32_CAN_USE_CAN0                  FALSE
+#endif
+
+/**
+ * @brief   CAN1 driver enable switch.
+ * @details If set to @p TRUE the support for CAN1 is included.
+ */
+#if !defined(GD32_CAN_USE_CAN1) || defined(__DOXYGEN__)
+#define GD32_CAN_USE_CAN1                  FALSE
+#endif
+
+/**
+ * @brief   CAN0 interrupt priority level setting.
+ */
+#if !defined(GD32_CAN_CAN0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_CAN_CAN0_IRQ_PRIORITY         11
+#endif
+/** @} */
+
+/**
+ * @brief   CAN1 interrupt priority level setting.
+ */
+#if !defined(GD32_CAN_CAN1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_CAN_CAN1_IRQ_PRIORITY         11
+#endif
+ 
+/**
+ * @brief   CAN0 interrupt trigger setting.
+ */
+#if !defined(GD32_CAN_CAN0_IRQ_TRIGGER) || defined(__DOXYGEN__)
+#define GD32_CAN_CAN0_IRQ_TRIGGER         ECLIC_TRIGGER_DEFAULT
+#endif
+/** @} */
+
+/**
+ * @brief   CAN1 interrupt trigger setting.
+ */
+#if !defined(GD32_CAN_CAN1_IRQ_TRIGGER) || defined(__DOXYGEN__)
+#define GD32_CAN_CAN1_IRQ_TRIGGER         ECLIC_TRIGGER_DEFAULT
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !defined(GD32_HAS_CAN0)
+#error "GD32_HAS_CAN0 not defined in registry"
+#endif
+
+#if !defined(GD32_HAS_CAN1)
+#error "GD32_HAS_CAN1 not defined in registry"
+#endif
+
+#if (GD32_HAS_CAN0 | GD32_HAS_CAN1) && !defined(GD32_CAN_MAX_FILTERS)
+#error "GD32_CAN_MAX_FILTERS not defined in registry"
+#endif
+
+#if GD32_CAN_USE_CAN0 && !GD32_HAS_CAN0
+#error "CAN0 not present in the selected device"
+#endif
+
+#if GD32_CAN_USE_CAN1 && !GD32_HAS_CAN1
+#error "CAN1 not present in the selected device"
+#endif
+
+#if !GD32_CAN_USE_CAN0 && !GD32_CAN_USE_CAN1 
+#error "CAN driver activated but no CAN peripheral assigned"
+#endif
+
+#if !GD32_CAN_USE_CAN0 && GD32_CAN_USE_CAN1
+#error "CAN1 requires CAN0, it cannot operate independently"
+#endif
+
+#if CAN_USE_SLEEP_MODE && !CAN_SUPPORTS_SLEEP
+#error "CAN sleep mode not supported in this architecture"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an CAN driver.
+ */
+typedef struct CANDriver CANDriver;
+
+/**
+ * @brief   Type of a transmission mailbox index.
+ */
+typedef uint32_t canmbx_t;
+
+#if (CAN_ENFORCE_USE_CALLBACKS == TRUE) || defined(__DOXYGEN__)
+/**
+ * @brief   Type of a CAN notification callback.
+ *
+ * @param[in] canp      pointer to the @p CANDriver object triggering the
+ *                      callback
+ * @param[in] flags     flags associated to the mailbox callback
+ */
+typedef void (*can_callback_t)(CANDriver *canp, uint32_t flags);
+#endif
+
+/**
+ * @brief   CAN transmission frame.
+ * @note    Accessing the frame data as word16 or word32 is not portable because
+ *          machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+  struct {
+    uint8_t                 DLC:4;          /**< @brief Data length.        */
+    uint8_t                 RTR:1;          /**< @brief Frame type.         */
+    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
+  };
+  union {
+    struct {
+      uint32_t              SID:11;         /**< @brief Standard identifier.*/
+    };
+    struct {
+      uint32_t              EID:29;         /**< @brief Extended identifier.*/
+    };
+  };
+  union {
+    uint8_t                 data8[8];       /**< @brief Frame data.         */
+    uint16_t                data16[4];      /**< @brief Frame data.         */
+    uint32_t                data32[2];      /**< @brief Frame data.         */
+    uint64_t                data64[1];      /**< @brief Frame data.         */
+  };
+} CANTxFrame;
+
+/**
+ * @brief   CAN received frame.
+ * @note    Accessing the frame data as word16 or word32 is not portable because
+ *          machine data endianness, it can be still useful for a quick filling.
+ */
+typedef struct {
+  struct {
+    uint8_t                 FMI;            /**< @brief Filter id.          */
+    uint16_t                TIME;           /**< @brief Time stamp.         */
+  };
+  struct {
+    uint8_t                 DLC:4;          /**< @brief Data length.        */
+    uint8_t                 RTR:1;          /**< @brief Frame type.         */
+    uint8_t                 IDE:1;          /**< @brief Identifier type.    */
+  };
+  union {
+    struct {
+      uint32_t              SID:11;         /**< @brief Standard identifier.*/
+    };
+    struct {
+      uint32_t              EID:29;         /**< @brief Extended identifier.*/
+    };
+  };
+  union {
+    uint8_t                 data8[8];       /**< @brief Frame data.         */
+    uint16_t                data16[4];      /**< @brief Frame data.         */
+    uint32_t                data32[2];      /**< @brief Frame data.         */
+    uint64_t                data64[1];      /**< @brief Frame data.         */
+  };
+} CANRxFrame;
+
+/**
+ * @brief   CAN filter.
+ * @note    Refer to the GD32 reference manual for info about filters.
+ */
+typedef struct {
+  /**
+   * @brief   Number of the filter bank to be programmed.
+   */
+  uint32_t                  filter:16;
+  /**
+   * @brief   Filter mode.
+   * @note    This bit represent the CAN_FMCFG register bit associated to this
+   *          filter (0=mask mode, 1=list mode).
+   */
+  uint32_t                  mode:1;
+  /**
+   * @brief   Filter scale.
+   * @note    This bit represent the CAN_FSCFG register bit associated to this
+   *          filter (0=16 bits mode, 1=32 bits mode).
+   */
+  uint32_t                  scale:1;
+  /**
+   * @brief   Filter mode.
+   * @note    This bit represent the CAN_FAFIFO register bit associated to this
+   *          filter, must be set to zero in this version of the driver.
+   */
+  uint32_t                  assignment:1;
+  /**
+   * @brief   Filter register 1 (identifier).
+   */
+  uint32_t                  register1;
+  /**
+   * @brief   Filter register 2 (mask/identifier depending on mode=0/1).
+   */
+  uint32_t                  register2;
+} CANFilter;
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   CAN CTL register initialization data.
+   * @note    Some bits in this register are enforced by the driver regardless
+   *          their status in this field.
+   */
+  uint32_t                  ctl;
+  /**
+   * @brief   CAN BT register initialization data.
+   * @note    Some bits in this register are enforced by the driver regardless
+   *          their status in this field.
+   */
+  uint32_t                  bt;
+} CANConfig;
+
+/**
+ * @brief   Structure representing an CAN driver.
+ */
+struct CANDriver {
+  /**
+   * @brief   Driver state.
+   */
+  canstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const CANConfig           *config;
+  /**
+   * @brief   Transmission threads queue.
+   */
+  threads_queue_t           txqueue;
+  /**
+   * @brief   Receive threads queue.
+   */
+  threads_queue_t           rxqueue;
+#if (CAN_ENFORCE_USE_CALLBACKS == FALSE) || defined(__DOXYGEN__)
+  /**
+   * @brief   One or more frames become available.
+   * @note    After broadcasting this event it will not be broadcasted again
+   *          until the received frames queue has been completely emptied. It
+   *          is <b>not</b> broadcasted for each received frame. It is
+   *          responsibility of the application to empty the queue by
+   *          repeatedly invoking @p canReceive() when listening to this event.
+   *          This behavior minimizes the interrupt served by the system
+   *          because CAN traffic.
+   * @note    The flags associated to the listeners will indicate which
+   *          receive mailboxes become non-empty.
+   */
+  event_source_t            rxfull_event;
+  /**
+   * @brief   One or more transmission mailbox become available.
+   * @note    The flags associated to the listeners will indicate which
+   *          transmit mailboxes become empty.
+   * @note    The upper 16 bits are transmission error flags associated
+   *          to the transmit mailboxes.
+   */
+  event_source_t            txempty_event;
+  /**
+   * @brief   A CAN bus error happened.
+   * @note    The flags associated to the listeners will indicate that
+   *          receive error(s) have occurred.
+   * @note    In this implementation the upper 16 bits are filled with the
+   *          unprocessed content of the ESR register.
+   */
+  event_source_t            error_event;
+#if CAN_USE_SLEEP_MODE || defined (__DOXYGEN__)
+  /**
+   * @brief   Entering sleep state event.
+   */
+  event_source_t            sleep_event;
+  /**
+   * @brief   Exiting sleep state event.
+   */
+  event_source_t            wakeup_event;
+#endif /* CAN_USE_SLEEP_MODE */
+#else /* CAN_ENFORCE_USE_CALLBACKS == TRUE */
+  /**
+   * @brief   One or more frames become available.
+   * @note    After calling this function it will not be called again
+   *          until the received frames queue has been completely emptied. It
+   *          is <b>not</b> called for each received frame. It is
+   *          responsibility of the application to empty the queue by
+   *          repeatedly invoking @p chTryReceiveI().
+   *          This behavior minimizes the interrupt served by the system
+   *          because CAN traffic.
+   */
+  can_callback_t            rxfull_cb;
+  /**
+   * @brief   One or more transmission mailbox become available.
+   * @note    The flags associated to the callback will indicate which
+   *          transmit mailboxes become empty.
+   */
+  can_callback_t            txempty_cb;
+  /**
+   * @brief   A CAN bus error happened.
+   */
+  can_callback_t            error_cb;
+#if (CAN_USE_SLEEP_MODE == TRUE) || defined (__DOXYGEN__)
+  /**
+   * @brief   Exiting sleep state.
+   */
+  can_callback_t            wakeup_cb;
+#endif
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the CAN registers.
+   */
+  CAN_TypeDef               *can;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if GD32_CAN_USE_CAN0 && !defined(__DOXYGEN__)
+extern CANDriver CAND1;
+#endif
+
+#if GD32_CAN_USE_CAN1 && !defined(__DOXYGEN__)
+extern CANDriver CAND2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void can_lld_init(void);
+  void can_lld_start(CANDriver *canp);
+  void can_lld_stop(CANDriver *canp);
+  bool can_lld_is_tx_empty(CANDriver *canp, canmbx_t mailbox);
+  void can_lld_transmit(CANDriver *canp,
+                        canmbx_t mailbox,
+                        const CANTxFrame *crfp);
+  bool can_lld_is_rx_nonempty(CANDriver *canp, canmbx_t mailbox);
+  void can_lld_receive(CANDriver *canp,
+                       canmbx_t mailbox,
+                       CANRxFrame *ctfp);
+  void can_lld_abort(CANDriver *canp,
+                     canmbx_t mailbox);
+#if CAN_USE_SLEEP_MODE
+  void can_lld_sleep(CANDriver *canp);
+  void can_lld_wakeup(CANDriver *canp);
+#endif /* CAN_USE_SLEEP_MODE */
+  void canGD32SetFilters(CANDriver *canp, uint32_t can2sb,
+                          uint32_t num, const CANFilter *cfp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_CAN */
+
+#endif /* HAL_CAN_LLD_H */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/driver.mk b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/driver.mk
new file mode 100644
index 000000000..48a731550
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/driver.mk
@@ -0,0 +1,11 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_CRC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c \
+               ${CHIBIOS_CONTRIB}/os/various/crcsw.c
+endif
+else
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c \
+               ${CHIBIOS_CONTRIB}/os/various/crcsw.c
+endif
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/CRC
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c
new file mode 100755
index 000000000..8ea3d8e9d
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.c
@@ -0,0 +1,259 @@
+/*
+    ChibiOS - Copyright (C) 2015 Michael D. Spradling
+    ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    GD32VF103/CRC/hal_crc_lld.c
+ * @brief   GD32 CRC subsystem low level driver source.
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
+/**
+ * Allow CRC Software override for ST drivers.  Some ST CRC implimentations
+ * have limited capabilities.
+ */
+#if CRCSW_USE_CRC1 != TRUE
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   CRC default configuration.
+ */
+static const CRCConfig default_config = {
+  .poly_size         = 32,
+  .poly              = 0x04C11DB7,
+  .initial_val       = 0xFFFFFFFF,
+  .final_val         = 0xFFFFFFFF,
+  .reflect_data      = 1,
+  .reflect_remainder = 1
+};
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief CRC1 driver identifier.*/
+#if GD32_CRC_USE_CRC0 || defined(__DOXYGEN__)
+CRCDriver CRCD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+void _crc_lld_calc_byte(CRCDriver *crcp, uint8_t data) {
+  __IO uint8_t *crc8 = (__IO uint8_t*)&(crcp->crc->DATA);
+  *crc8 = data;
+}
+
+/*
+ * @brief   Returns calculated CRC from last reset
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ * @param[in] data      data to be added to crc
+ *
+ * @notapi
+ */
+void _crc_lld_calc_halfword(CRCDriver *crcp, uint16_t data) {
+  __IO uint16_t *crc16 = (__IO uint16_t*)&(crcp->crc->DATA);
+  *crc16 = data;
+}
+
+/*
+ * @brief   Returns calculated CRC from last reset
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ * @param[in] data      data to be added to crc
+ *
+ * @notapi
+ */
+void _crc_lld_calc_word(CRCDriver *crcp, uint32_t data) {
+  crcp->crc->DATA = data;
+}
+
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared end-of-rx service routine.
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+#if CRC_USE_DMA == TRUE
+static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+#if defined(GD32_CRC_DMA_ERROR_HOOK)
+  if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
+    GD32_CRC_DMA_ERROR_HOOK(crcp);
+  }
+#else
+  (void)flags;
+#endif
+
+  /* Stop everything.*/
+  dmaStreamDisable(crcp->dmastp);
+
+  if (crcp->rem_data_size) {
+    /* Start DMA follow up transfer for next data chunk */
+    crc_lld_start_calc(crcp, crcp->rem_data_size,
+      (const void *)crcp->dmastp->channel->PADDR+0xffff);
+  } else {
+    /* Portable CRC ISR code defined in the high level driver, note, it is a macro.*/
+    _crc_isr_code(crcp, crcp->crc->DATA ^ crcp->config->final_val);
+  }
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level CRC driver initialization.
+ *
+ * @notapi
+ */
+void crc_lld_init(void) {
+  crcObjectInit(&CRCD1);
+  CRCD1.crc    = CRC;
+}
+
+/**
+ * @brief   Configures and activates the CRC peripheral.
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_start(CRCDriver *crcp) {
+  if (crcp->config == NULL)
+    crcp->config = &default_config;
+
+  rcuEnableCRC( FALSE );
+
+  osalDbgAssert(crcp->config->initial_val == default_config.initial_val,
+      "hardware doesn't support programmable initial value");
+  osalDbgAssert(crcp->config->poly_size == default_config.poly_size,
+      "hardware doesn't support programmable polynomial size");
+  osalDbgAssert(crcp->config->poly == default_config.poly,
+      "hardware doesn't support programmable polynomial");
+  osalDbgAssert(crcp->config->reflect_data == default_config.reflect_data,
+      "hardware doesn't support reflect of input data");
+  osalDbgAssert(crcp->config->reflect_remainder == default_config.reflect_remainder,
+      "hardware doesn't support reflect of output remainder");
+
+#if CRC_USE_DMA == TRUE
+  crcp->dmamode = GD32_DMA_CTL_DIR_M2M     | GD32_DMA_CTL_PNAGA |
+                  GD32_DMA_CTL_MWIDTH_WORD | GD32_DMA_CTL_PWIDTH_WORD |
+                  GD32_DMA_CTL_ERRIE       | GD32_DMA_CTL_FTFIE |
+                  GD32_DMA_CTL_PRIO(GD32_CRC_CRC0_DMA_PRIORITY);
+  {
+    crcp->dmastp = dmaStreamAlloc(GD32_CRC_CRC0_DMA_STREAM,
+                                                 GD32_CRC_CRC0_DMA_IRQ_PRIORITY,
+                                                 (gd32_dmaisr_t)crc_lld_serve_interrupt,
+                                                 (void *)crcp);
+    osalDbgAssert(crcp->dmastp != NULL, "unable to allocate stream");
+  }
+#endif
+}
+
+
+/**
+ * @brief   Deactivates the CRC peripheral.
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_stop(CRCDriver *crcp) {
+#if CRC_USE_DMA == TRUE
+  dmaStreamFree(crcp->dmastp);
+#else
+  (void)crcp;
+#endif
+  rcuDisableCRC();
+}
+
+/**
+ * @brief   Resets current CRC calculation.
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ *
+ * @notapi
+ */
+void crc_lld_reset(CRCDriver *crcp) {
+  crcp->crc->CTL |= CRC_CTL_RST;
+}
+
+/**
+ * @brief   Returns calculated CRC from last reset
+ *
+ * @param[in] crcp      pointer to the @p CRCDriver object
+ * @param[in] n         size of buf in bytes
+ * @param[in] buf       @p buffer location
+ *
+ * @notapi
+ */
+uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
+#if CRC_USE_DMA == TRUE
+  crc_lld_start_calc(crcp, n, buf);
+  (void) osalThreadSuspendS(&crcp->thread);
+#else
+    while(n > 3) {
+      _crc_lld_calc_word(crcp, *(uint32_t*)buf);
+      buf+=4;
+      n-=4;
+    }
+  osalDbgAssert(n == 0, "GD32 CRC Unit only supports WORD accesses");
+#endif
+  return crcp->crc->DATA ^ crcp->config->final_val;
+}
+
+#if CRC_USE_DMA == TRUE
+void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) {
+  /* The GD32 DMA can only handle max 65535 bytes per transfer
+   * because it's data count register has only 16 bit. */
+  size_t sz = (n > 0xffff) ? 0xffff : n;
+  crcp->rem_data_size = n-sz;
+
+  dmaStreamSetPeripheral(crcp->dmastp, buf);
+  dmaStreamSetMemory0(crcp->dmastp, &crcp->crc->DATA);
+  dmaStreamSetTransactionSize(crcp->dmastp, (sz / 4));
+  dmaStreamSetMode(crcp->dmastp, crcp->dmamode);
+
+  dmaStreamEnable(crcp->dmastp);
+}
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.h b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.h
new file mode 100644
index 000000000..926bdb62b
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/CRC/hal_crc_lld.h
@@ -0,0 +1,255 @@
+/*
+    ChibiOS - Copyright (C) 2015 Michael D. Spradling
+    ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    GD32VF103/CRC/hal_crc_lld.h
+ * @brief   GD CRC subsystem low level driver header.
+ *
+ * @addtogroup CRC
+ * @{
+ */
+
+#ifndef HAL_CRC_LLD_H_
+#define HAL_CRC_LLD_H_
+
+#if (HAL_USE_CRC == TRUE) || defined(__DOXYGEN__)
+/*
+ * This error check must occur outsite of CRCSW_USE_CRC1 to check if
+ * two LLD drivers are enabled at the same time
+ */
+#if GD32_CRC_USE_CRC0 == TRUE &&                                           \
+    CRCSW_USE_CRC1 == TRUE
+#error "Software CRC can't be enable with GD32_CRC_USE_CRC0"
+#endif
+
+/**
+ * Allow CRC Software override for ST drivers.  Some ST CRC implimentations
+ * have limited capabilities.
+ */
+#if CRCSW_USE_CRC1 != TRUE
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   CRC0 driver enable switch.
+ * @details If set to @p TRUE the support for CRC1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(GD32_CRC_USE_CRC0) || defined(__DOXYGEN__)
+#define GD32_CRC_USE_CRC0                  FALSE
+#endif
+
+/**
+ * @brief   CRC0 DMA priority (0..3|lowest..highest).
+ * @note    The priority level is for CRC DMA stream.
+ */
+#if !defined(GD32_CRC_CRC0_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_CRC_CRC0_DMA_PRIORITY         2
+#endif
+
+/**
+ * @brief   CRC0 DMA interrupt priority level setting.
+ */
+#if !defined(GD32_CRC_CRC0_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_CRC_CRC0_DMA_IRQ_PRIORITY     14
+#endif
+
+/**
+ * @brief   CRC0 DMA STREAM to use when performing CRC calculation.
+ */
+#if !defined(GD32_CRC_CRC0_DMA_STREAM) || defined(__DOXYGEN__)
+#define GD32_CRC_CRC0_DMA_STREAM           GD32_DMA_STREAM_ID(0, 1)
+#endif
+
+/**
+ * @brief   CRC DMA error hook.
+ */
+#if !defined(GD32_CRC_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define GD32_CRC_DMA_ERROR_HOOK(spip)      osalSysHalt("DMA failure")
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if GD32_CRC_USE_CRC0 && !GD32_HAS_CRC
+#error "Hardware CRC not present in the selected device"
+#error "Use CRCSW_USE_CRC1 for software implementation"
+#endif
+
+#if CRC_USE_DMA
+#if GD32_CRC_USE_CRC0 &&                                                   \
+    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_CRC_CRC0_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to CRC0"
+#endif
+
+#if GD32_CRC_USE_CRC0 &&                                                   \
+    !GD32_DMA_IS_VALID_PRIORITY(GD32_CRC_CRC0_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to CRC0"
+#endif
+
+#if !defined(GD32_DMA_REQUIRED)
+#define GD32_DMA_REQUIRED
+#endif
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an CRC driver.
+ */
+typedef struct CRCDriver CRCDriver;
+
+/**
+ * @brief   CRC notification callback type
+ *
+ * @param[in] crcp      pointer to the @ CRCDriver object triggering the
+ *                      callback
+ */
+typedef void (*crccallback_t)(CRCDriver *crcp, uint32_t crc);
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief The size of polynomial to be used for CRC.
+   */
+  uint32_t                 poly_size;
+  /**
+   * @brief The coefficients of the polynomial to be used for CRC.
+   */
+  uint32_t                 poly;
+  /**
+   * @brief The inital value
+   */
+  uint32_t                 initial_val;
+  /**
+   * @brief The final XOR value
+   */
+  uint32_t                 final_val;
+  /**
+   * @brief Reflect bit order data going into CRC
+   */
+  bool                     reflect_data;
+  /**
+   * @brief Reflect bit order of final remainder
+   */
+  bool                     reflect_remainder;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Operation complete callback or @p NULL
+   */
+  crccallback_t            end_cb;
+} CRCConfig;
+
+
+/**
+ * @brief   Structure representing an CRC driver.
+ */
+struct CRCDriver {
+  /**
+   * @brief Driver state.
+   */
+  crcstate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const CRCConfig           *config;
+#if CRC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* CRC_USE_MUTUAL_EXCLUSION */
+#if defined(CRC_DRIVER_EXT_FIELDS)
+  CRC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the CRCx registers block.
+   */
+  CRC_TypeDef               *crc;
+
+#if CRC_USE_DMA == TRUE
+  /**
+   * @brief   Waiting thread.
+   */
+  thread_reference_t        thread;
+  /**
+   * @brief   Remaining data size.
+   * @note    The DMA can handle only 65535 bytes per transfer because
+   *            it's data count register is only 16 bits wide.
+   */
+  size_t rem_data_size;
+  /**
+   * @brief CRC DMA stream
+   */
+  const gd32_dma_stream_t  *dmastp;
+  /**
+   * @brief DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+#endif
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if GD32_CRC_USE_CRC0 && !defined(__DOXYGEN__)
+extern CRCDriver CRCD1;
+#endif /* GD32_CRC_USE_CRC0 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void crc_lld_init(void);
+  void crc_lld_start(CRCDriver *crcp);
+  void crc_lld_stop(CRCDriver *crcp);
+  void crc_lld_reset(CRCDriver *crcp);
+  uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf);
+#if CRC_USE_DMA
+  void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf);
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CRCSW_USE_CRC1 */
+
+#endif /* HAL_USE_CRC */
+
+#endif /* HAL_CRC_LLD_H_ */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/driver.mk b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/driver.mk
new file mode 100644
index 000000000..1f2a501fa
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_DAC TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
+endif
+else
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
+endif
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DAC
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
new file mode 100644
index 000000000..baeecbda3
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.c
@@ -0,0 +1,462 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    DAC/hal_dac_lld.c
+ * @brief   GD32 DAC subsystem low level driver source.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#define DAC_CH1_DMA_CHANNEL                                                \
+  GD32_DMA_GETCHANNEL(GD32_DAC_CH1_DMA_STREAM,                       \
+                       GD32_DAC_CH1_DMA_CHN)
+
+#define DAC_CH2_DMA_CHANNEL                                                \
+  GD32_DMA_GETCHANNEL(GD32_DAC_CH2_DMA_STREAM,                       \
+                       GD32_DAC_CH2_DMA_CHN)
+
+#define CHANNEL_DATA_OFFSET 3U
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief DAC CH1 driver identifier.*/
+#if GD32_DAC_USE_DAC_CH1 || defined(__DOXYGEN__)
+DACDriver DACD1;
+#endif
+
+/** @brief DAC CH2 driver identifier.*/
+#if (GD32_DAC_USE_DAC_CH2 && !GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+DACDriver DACD2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+#if GD32_DAC_USE_DAC_CH1 == TRUE
+static const dacparams_t dac1_ch1_params = {
+  .dac          = DAC,
+  .dataoffset   = 0U,
+  .regshift     = 0U,
+  .regmask      = 0xFFFF0000U,
+  .dmastream    = GD32_DAC_CH1_DMA_STREAM,
+  .dmamode      = GD32_DMA_CTL_CHSEL(DAC_CH1_DMA_CHANNEL) |
+                  GD32_DMA_CTL_PRIO(GD32_DAC_CH1_DMA_PRIORITY) |
+                  GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
+                  GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
+                  GD32_DMA_CTL_FTFIE,
+  .dmairqprio   = GD32_DAC_CH1_IRQ_PRIORITY
+};
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 == TRUE
+static const dacparams_t dac1_ch2_params = {
+  .dac          = DAC,
+  .dataoffset   = CHANNEL_DATA_OFFSET,
+  .regshift     = 16U,
+  .regmask      = 0x0000FFFFU,
+  .dmastream    = GD32_DAC_CH2_DMA_STREAM,
+  .dmamode      = GD32_DMA_CTL_CHSEL(DAC_CH2_DMA_CHANNEL) |
+                  GD32_DMA_CTL_PRIO(GD32_DAC_CH2_DMA_PRIORITY) |
+                  GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_CMEN | GD32_DMA_CTL_DIR_M2P |
+                  GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_HTFIE |
+                  GD32_DMA_CTL_FTFIE,
+  .dmairqprio   = GD32_DAC_CH2_IRQ_PRIORITY
+};
+#endif
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Shared end/half-of-tx service routine.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void dac_lld_serve_tx_interrupt(DACDriver *dacp, uint32_t flags) {
+
+  if ((flags & (GD32_DMA_INTF_ERRIF)) != 0) {
+    /* DMA errors handling.*/
+    dac_lld_stop_conversion(dacp);
+    _dac_isr_error_code(dacp, DAC_ERR_DMAFAILURE);
+  }
+  else {
+    if ((flags & GD32_DMA_INTF_HTFIF) != 0) {
+      /* Half transfer processing.*/
+      _dac_isr_half_code(dacp);
+    }
+    if ((flags & GD32_DMA_INTF_FTFIF) != 0) {
+      /* Transfer complete processing.*/
+      _dac_isr_full_code(dacp);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level DAC driver initialization.
+ *
+ * @notapi
+ */
+void dac_lld_init(void) {
+
+#if GD32_DAC_USE_DAC_CH1
+  dacObjectInit(&DACD1);
+  DACD1.params  = &dac1_ch1_params;
+  DACD1.dma = NULL;
+#endif
+
+#if GD32_DAC_USE_DAC_CH2
+  dacObjectInit(&DACD2);
+  DACD2.params  = &dac1_ch2_params;
+  DACD2.dma = NULL;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the DAC peripheral.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start(DACDriver *dacp) {
+
+  /* If the driver is in DAC_STOP state then a full initialization is
+     required.*/
+  if (dacp->state == DAC_STOP) {
+    dacchannel_t channel = 0;
+
+    /* Enabling the clock source.*/
+#if GD32_DAC_USE_DAC_CH1
+    if (&DACD1 == dacp) {
+      rcuEnableDAC(true);
+    }
+#endif
+
+#if GD32_DAC_USE_DAC_CH2
+    if (&DACD2 == dacp) {
+      rcuEnableDAC(true);
+      channel = 1;
+    }
+#endif
+
+    /* Enabling DAC in SW triggering mode initially, initializing data to
+       zero.*/
+#if GD32_DAC_DUAL_MODE == FALSE
+    {
+      uint32_t ctl;
+
+      ctl = dacp->params->dac->CTL;
+      ctl &= dacp->params->regmask;
+      ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
+      dacp->params->dac->CTL = ctl;
+      dac_lld_put_channel(dacp, channel, dacp->config->init);
+    }
+#else
+    if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
+        (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
+        (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
+      dacp->params->dac->CTL = DAC_CTL_DEN1 | (dacp->config->ctl << 16) | DAC_CTL_DEN0 | dacp->config->ctl;
+      dac_lld_put_channel(dacp, 1U, dacp->config->init);
+    }
+    else {
+      dacp->params->dac->CTL = DAC_CTL_DEN0 | dacp->config->ctl;
+    }
+    dac_lld_put_channel(dacp, channel, dacp->config->init);
+#endif
+  }
+}
+
+/**
+ * @brief   Deactivates the DAC peripheral.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_stop(DACDriver *dacp) {
+
+  /* If in ready state then disables the DAC clock.*/
+  if (dacp->state == DAC_READY) {
+
+    /* Disabling DAC.*/
+    dacp->params->dac->CTL &= dacp->params->regmask;
+
+#if GD32_DAC_USE_DAC_CH1
+    if (&DACD1 == dacp) {
+      if ((dacp->params->dac->CTL & DAC_CTL_DEN1) == 0U) {
+        rcuDisableDAC();
+      }
+    }
+#endif
+
+#if GD32_DAC_USE_DAC_CH2
+    if (&DACD2 == dacp) {
+      if ((dacp->params->dac->CTL & DAC_CTL_DEN0) == 0U) {
+        rcuDisableDAC();
+      }
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Outputs a value directly on a DAC channel.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ * @param[in] channel   DAC channel number
+ * @param[in] sample    value to be output
+ *
+ * @api
+ */
+void dac_lld_put_channel(DACDriver *dacp,
+                         dacchannel_t channel,
+                         dacsample_t sample) {
+
+  switch (dacp->config->datamode) {
+  case DAC_DHRM_12BIT_RIGHT:
+#if GD32_DAC_DUAL_MODE
+  case DAC_DHRM_12BIT_RIGHT_DUAL:
+#endif
+    if (channel == 0U) {
+#if GD32_DAC_DUAL_MODE
+      dacp->params->dac->R12DH0 = (uint32_t)sample;
+#else
+      *(&dacp->params->dac->R12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+    }
+#if (GD32_HAS_DAC_CH2)
+    else {
+      dacp->params->dac->R12DH1 = (uint32_t)sample;
+    }
+#endif
+    break;
+  case DAC_DHRM_12BIT_LEFT:
+#if GD32_DAC_DUAL_MODE
+  case DAC_DHRM_12BIT_LEFT_DUAL:
+#endif
+    if (channel == 0U) {
+#if GD32_DAC_DUAL_MODE
+      dacp->params->dac->L12DH0 = (uint32_t)sample;
+#else
+      *(&dacp->params->dac->L12DH0 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+    }
+#if (GD32_HAS_DAC_CH2)
+    else {
+      dacp->params->dac->L12DH1 = (uint32_t)sample;
+    }
+#endif
+    break;
+  case DAC_DHRM_8BIT_RIGHT:
+#if GD32_DAC_DUAL_MODE
+  case DAC_DHRM_8BIT_RIGHT_DUAL:
+#endif
+    if (channel == 0U) {
+#if GD32_DAC_DUAL_MODE
+      dacp->params->dac->R8DH0 = (uint32_t)sample;
+#else
+      *(&dacp->params->dac->R8DH0 + dacp->params->dataoffset) = (uint32_t)sample;
+#endif
+    }
+#if (GD32_HAS_DAC_CH2)
+    else {
+      dacp->params->dac->R8DH1 = (uint32_t)sample;
+    }
+#endif
+    break;
+  default:
+    osalDbgAssert(false, "unexpected DAC mode");
+    break;
+  }
+}
+
+/**
+ * @brief   Starts a DAC conversion.
+ * @details Starts an asynchronous conversion operation.
+ * @note    In @p DAC_DHRM_8BIT_RIGHT mode the parameters passed to the
+ *          callback are wrong because two samples are packed in a single
+ *          dacsample_t element. This will not be corrected, do not rely
+ *          on those parameters.
+ * @note    In @p DAC_DHRM_8BIT_RIGHT_DUAL mode two samples are treated
+ *          as a single 16 bits sample and packed into a single dacsample_t
+ *          element. The num_channels must be set to one in the group
+ *          conversion configuration structure.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @notapi
+ */
+void dac_lld_start_conversion(DACDriver *dacp) {
+  uint32_t n, ctl, dmamode;
+
+  /* Number of DMA operations per buffer.*/
+  n = dacp->depth * dacp->grpp->num_channels;
+
+  /* Allocating the DMA channel.*/
+  dacp->dma = dmaStreamAllocI(dacp->params->dmastream,
+                              dacp->params->dmairqprio,
+                              (gd32_dmaisr_t)dac_lld_serve_tx_interrupt,
+                              (void *)dacp);
+  osalDbgAssert(dacp->dma != NULL, "unable to allocate stream");
+
+  /* DMA settings depend on the chosen DAC mode.*/
+  switch (dacp->config->datamode) {
+  /* Sets the DAC data register */
+  case DAC_DHRM_12BIT_RIGHT:
+    osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH0 +
+                                      dacp->params->dataoffset);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
+    break;
+  case DAC_DHRM_12BIT_LEFT:
+    osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH0 +
+                                      dacp->params->dataoffset);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
+    break;
+  case DAC_DHRM_8BIT_RIGHT:
+    osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH0 +
+                                      dacp->params->dataoffset);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_BYTE | GD32_DMA_CTL_MWIDTH_BYTE;
+
+    /* In this mode the size of the buffer is halved because two samples
+       packed in a single dacsample_t element.*/
+    n = (n + 1) / 2;
+    break;
+#if GD32_DAC_DUAL_MODE == TRUE
+  case DAC_DHRM_12BIT_RIGHT_DUAL:
+    osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R12DH);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD;
+    n /= 2;
+    break;
+  case DAC_DHRM_12BIT_LEFT_DUAL:
+    osalDbgAssert(dacp->grpp->num_channels == 2, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->L12DH);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_WORD | GD32_DMA_CTL_MWIDTH_WORD;
+    n /= 2;
+    break;
+  case DAC_DHRM_8BIT_RIGHT_DUAL:
+    osalDbgAssert(dacp->grpp->num_channels == 1, "invalid number of channels");
+
+    dmaStreamSetPeripheral(dacp->dma, &dacp->params->dac->R8DH);
+    dmamode = dacp->params->dmamode |
+              GD32_DMA_CTL_PWIDTH_HWORD | GD32_DMA_CTL_MWIDTH_HWORD;
+    n /= 2;
+    break;
+#endif
+  default:
+    osalDbgAssert(false, "unexpected DAC mode");
+    return;
+  }
+
+  dmaStreamSetMemory0(dacp->dma, dacp->samples);
+  dmaStreamSetTransactionSize(dacp->dma, n);
+  dmaStreamSetMode(dacp->dma, dmamode            |
+                              GD32_DMA_CTL_ERRIE |
+                              GD32_DMA_CTL_HTFIE  | GD32_DMA_CTL_FTFIE);
+  dmaStreamEnable(dacp->dma);
+
+  /* DAC configuration.*/
+  ctl = dacp->params->dac->CTL;
+
+#if GD32_DAC_DUAL_MODE == FALSE
+  ctl &= dacp->params->regmask;
+  ctl |= (DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
+#else
+  ctl = DAC_CTL_DDMAEN0 | (dacp->grpp->trigger << DAC_CTL_DTSEL0_Pos) | DAC_CTL_DTEN0 | DAC_CTL_DEN0 | dacp->config->ctl
+                     | (dacp->grpp->trigger << DAC_CTL_DTSEL1_Pos) | DAC_CTL_DTEN1 | DAC_CTL_DEN1 | (dacp->config->ctl << 16);
+#endif
+
+  dacp->params->dac->CTL = ctl;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ * @details This function stops the currently ongoing conversion and returns
+ *          the driver in the @p DAC_READY state. If there was no conversion
+ *          being processed then the function does nothing.
+ *
+ * @param[in] dacp      pointer to the @p DACDriver object
+ *
+ * @iclass
+ */
+void dac_lld_stop_conversion(DACDriver *dacp) {
+  uint32_t ctl;
+
+  /* DMA channel disabled and released.*/
+  dmaStreamDisable(dacp->dma);
+  dmaStreamFreeI(dacp->dma);
+  dacp->dma = NULL;
+
+  ctl = dacp->params->dac->CTL;
+
+#if GD32_DAC_DUAL_MODE == FALSE
+  ctl &= dacp->params->regmask;
+  ctl |= (DAC_CTL_DEN0 | dacp->config->ctl) << dacp->params->regshift;
+#else
+  if ((dacp->config->datamode == DAC_DHRM_12BIT_RIGHT_DUAL) ||
+      (dacp->config->datamode == DAC_DHRM_12BIT_LEFT_DUAL) ||
+      (dacp->config->datamode == DAC_DHRM_8BIT_RIGHT_DUAL)) {
+    ctl = DAC_CTL_DEN1 | (dacp->config->ctl << 16) |
+         DAC_CTL_DEN0 | dacp->config->ctl;
+  }
+  else {
+    ctl = DAC_CTL_DEN0 | dacp->config->ctl;
+  }
+#endif
+
+  dacp->params->dac->CTL = ctl;
+}
+
+#endif /* HAL_USE_DAC */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h
new file mode 100644
index 000000000..27fe38acb
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DAC/hal_dac_lld.h
@@ -0,0 +1,304 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    DAC/hal_dac_lld.h
+ * @brief   GD32 DAC subsystem low level driver header.
+ *
+ * @addtogroup DAC
+ * @{
+ */
+
+#ifndef HAL_DAC_LLD_H
+#define HAL_DAC_LLD_H
+
+#if HAL_USE_DAC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    DAC trigger modes
+ * @{
+ */
+#define DAC_TRG_MASK                    7U
+#define DAC_TRG(n)                      (n)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Enables the DAC dual mode.
+ * @note    In dual mode DAC second channels cannot be accessed individually.
+ */
+#if !defined(GD32_DAC_DUAL_MODE) || defined(__DOXYGEN__)
+#define GD32_DAC_DUAL_MODE                 FALSE
+#endif
+
+/**
+ * @brief   DAC CH1 driver enable switch.
+ * @details If set to @p TRUE the support for DAC channel 1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(GD32_DAC_USE_DAC_CH1) || defined(__DOXYGEN__)
+#define GD32_DAC_USE_DAC_CH1              FALSE
+#endif
+
+/**
+ * @brief   DAC CH2 driver enable switch.
+ * @details If set to @p TRUE the support for DAC channel 2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(GD32_DAC_USE_DAC_CH2) || defined(__DOXYGEN__)
+#define GD32_DAC_USE_DAC_CH2              FALSE
+#endif
+
+/**
+ * @brief   DAC CH1 interrupt priority level setting.
+ */
+#if !defined(GD32_DAC_CH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_DAC_CH1_IRQ_PRIORITY     10
+#endif
+
+/**
+ * @brief   DAC CH2 interrupt priority level setting.
+ */
+#if !defined(GD32_DAC_CH2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_DAC_CH2_IRQ_PRIORITY     10
+#endif
+
+/**
+ * @brief   DAC CH1 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(GD32_DAC_CH1_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_DAC_CH1_DMA_PRIORITY     2
+#endif
+
+/**
+ * @brief   DAC CH2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(GD32_DAC_CH2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define GD32_DAC_CH2_DMA_PRIORITY     2
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/* Handling missing registry keys.*/
+#if !defined(GD32_HAS_DAC_CH1)
+#define GD32_HAS_DAC_CH1                  FALSE
+#endif
+#if !defined(GD32_HAS_DAC_CH2)
+#define GD32_HAS_DAC_CH2                  FALSE
+#endif
+
+#if GD32_DAC_USE_DAC_CH1 && !GD32_HAS_DAC_CH1
+#error "DAC CH1 not present in the selected device"
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 && !GD32_HAS_DAC_CH2
+#error "DAC CH2 not present in the selected device"
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 && GD32_DAC_DUAL_MODE
+#error "DACx CH2 cannot be used independently in dual mode"
+#endif
+
+#if !GD32_DAC_USE_DAC_CH1 && !GD32_DAC_USE_DAC_CH2
+#error "DAC driver activated but no DAC peripheral assigned"
+#endif
+
+#if GD32_DAC_USE_DAC_CH1 &&                                               \
+    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_CH1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC CH1"
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 &&                                               \
+    !OSAL_IRQ_IS_VALID_PRIORITY(GD32_DAC_CH2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to DAC CH2"
+#endif
+
+
+#if GD32_DAC_USE_DAC_CH1 &&                                               \
+    !GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_CH1_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC CH1"
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 &&                                               \
+    !GD32_DMA_IS_VALID_PRIORITY(GD32_DAC_CH2_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to DAC CH2"
+#endif
+
+#if !defined(GD32_DMA_REQUIRED)
+#define GD32_DMA_REQUIRED
+#endif
+
+/**
+ * @brief   Max DAC channels.
+ */
+#if GD32_DAC_DUAL_MODE == FALSE
+#define DAC_MAX_CHANNELS                    2
+#else
+#define DAC_MAX_CHANNELS                    1
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a DAC channel index.
+ */
+typedef uint32_t dacchannel_t;
+
+/**
+ * @brief   Type representing a DAC sample.
+ */
+typedef uint16_t dacsample_t;
+
+/**
+ * @brief   DAC channel parameters type.
+ */
+typedef struct {
+  /**
+   * @brief   Pointer to the DAC registers block.
+   */
+  DAC_TypeDef               *dac;
+  /**
+   * @brief   DAC data registers offset.
+   */
+  uint32_t                  dataoffset;
+  /**
+   * @brief   DAC CR register bit offset.
+   */
+  uint32_t                  regshift;
+  /**
+   * @brief   DAC CR register mask.
+   */
+  uint32_t                  regmask;
+  /**
+   * @brief   Associated DMA stream.
+   */
+  uint32_t                  dmastream;
+  /**
+   * @brief   Mode bits for the DMA.
+   */
+  uint32_t                  dmamode;
+  /**
+   * @brief   DMA channel IRQ priority.
+   */
+  uint32_t                  dmairqprio;
+} dacparams_t;
+
+/**
+ * @brief   Possible DAC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  DAC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  DAC_ERR_UNDERFLOW = 1                     /**< DAC overflow condition.    */
+} dacerror_t;
+
+/**
+ * @brief   Samples alignment and size mode.
+ */
+typedef enum {
+  DAC_DHRM_12BIT_RIGHT = 0,
+  DAC_DHRM_12BIT_LEFT = 1,
+  DAC_DHRM_8BIT_RIGHT = 2,
+#if GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+  DAC_DHRM_12BIT_RIGHT_DUAL = 3,
+  DAC_DHRM_12BIT_LEFT_DUAL = 4,
+  DAC_DHRM_8BIT_RIGHT_DUAL = 5
+#endif
+} dacdhrmode_t;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level fields of the DAC driver structure.
+ */
+#define dac_lld_driver_fields                                               \
+  /* DAC channel parameters.*/                                              \
+  const dacparams_t         *params;                                        \
+  /* Associated DMA.*/                                                      \
+  const gd32_dma_stream_t  *dma
+
+/**
+ * @brief   Low level fields of the DAC configuration structure.
+ */
+#define dac_lld_config_fields                                               \
+  /* Initial output on DAC channels.*/                                      \
+  dacsample_t               init;                                           \
+  /* DAC data holding register mode.*/                                      \
+  dacdhrmode_t              datamode;                                       \
+  /* DAC control register lower 16 bits.*/                                  \
+  uint32_t                  ctl
+
+/**
+ * @brief   Low level fields of the DAC group configuration structure.
+ */
+#define dac_lld_conversion_group_fields                                     \
+  /* DAC initialization data. This field contains the (not shifted) value   \
+     to be put into the TSEL field of the DAC CR register during            \
+     initialization. All other fields are handled internally.*/             \
+  uint32_t                  trigger
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if GD32_DAC_USE_DAC_CH1 && !defined(__DOXYGEN__)
+extern DACDriver DACD1;
+#endif
+
+#if GD32_DAC_USE_DAC_CH2 && !GD32_DAC_DUAL_MODE && !defined(__DOXYGEN__)
+extern DACDriver DACD2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dac_lld_init(void);
+  void dac_lld_start(DACDriver *dacp);
+  void dac_lld_stop(DACDriver *dacp);
+  void dac_lld_put_channel(DACDriver *dacp,
+                           dacchannel_t channel,
+                           dacsample_t sample);
+  void dac_lld_start_conversion(DACDriver *dacp);
+  void dac_lld_stop_conversion(DACDriver *dacp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_DAC */
+
+#endif /* HAL_DAC_LLD_H */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/driver.mk b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/driver.mk
new file mode 100644
index 000000000..bf1fdf5ed
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/driver.mk
@@ -0,0 +1,2 @@
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/DMA
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c
new file mode 100644
index 000000000..542842711
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.c
@@ -0,0 +1,590 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    DMA/gd32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup GD32_DMA
+ * @details DMA sharing helper driver. In the GD32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(GD32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA0 streams in @p dma_streams_mask.
+ */
+#define GD32_DMA0_STREAMS_MASK     ((1U << GD32_DMA0_NUM_CHANNELS) - 1U)
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define GD32_DMA1_STREAMS_MASK     (((1U << GD32_DMA1_NUM_CHANNELS) -     \
+                                      1U) << GD32_DMA0_NUM_CHANNELS)
+
+#define DMA0_CH0_VARIANT            0
+#define DMA0_CH1_VARIANT            0
+#define DMA0_CH2_VARIANT            0
+#define DMA0_CH3_VARIANT            0
+#define DMA0_CH4_VARIANT            0
+#define DMA0_CH5_VARIANT            0
+#define DMA0_CH6_VARIANT            0
+#define DMA1_CH0_VARIANT            0
+#define DMA1_CH1_VARIANT            0
+#define DMA1_CH2_VARIANT            0
+#define DMA1_CH3_VARIANT            0
+#define DMA1_CH4_VARIANT            0
+
+/*
+ * Default ISR collision masks.
+ */
+#if !defined(GD32_DMA0_CH0_CMASK)
+#define GD32_DMA0_CH0_CMASK        (1U << 0U)
+#endif
+
+#if !defined(GD32_DMA0_CH1_CMASK)
+#define GD32_DMA0_CH1_CMASK        (1U << 1U)
+#endif
+
+#if !defined(GD32_DMA0_CH2_CMASK)
+#define GD32_DMA0_CH2_CMASK        (1U << 2U)
+#endif
+
+#if !defined(GD32_DMA0_CH3_CMASK)
+#define GD32_DMA0_CH3_CMASK        (1U << 3U)
+#endif
+
+#if !defined(GD32_DMA0_CH4_CMASK)
+#define GD32_DMA0_CH4_CMASK        (1U << 4U)
+#endif
+
+#if !defined(GD32_DMA0_CH5_CMASK)
+#define GD32_DMA0_CH5_CMASK        (1U << 5U)
+#endif
+
+#if !defined(GD32_DMA0_CH6_CMASK)
+#define GD32_DMA0_CH6_CMASK        (1U << 6U)
+#endif
+
+#if !defined(GD32_DMA1_CH0_CMASK)
+#define GD32_DMA1_CH0_CMASK        (1U << (GD32_DMA0_NUM_CHANNELS + 0U))
+#endif
+
+#if !defined(GD32_DMA1_CH1_CMASK)
+#define GD32_DMA1_CH1_CMASK        (1U << (GD32_DMA0_NUM_CHANNELS + 1U))
+#endif
+
+#if !defined(GD32_DMA1_CH2_CMASK)
+#define GD32_DMA1_CH2_CMASK        (1U << (GD32_DMA0_NUM_CHANNELS + 2U))
+#endif
+
+#if !defined(GD32_DMA1_CH3_CMASK)
+#define GD32_DMA1_CH3_CMASK        (1U << (GD32_DMA0_NUM_CHANNELS + 3U))
+#endif
+
+#if !defined(GD32_DMA1_CH4_CMASK)
+#define GD32_DMA1_CH4_CMASK        (1U << (GD32_DMA0_NUM_CHANNELS + 4U))
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p GD32_DMA0_STREAM0, @p GD32_DMA0_STREAM1 etc.
+ */
+const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS] = {
+  {DMA0, DMA0_Channel0, GD32_DMA0_CH0_CMASK, DMA0_CH0_VARIANT,  0, 0, GD32_DMA0_CH0_NUMBER},
+  {DMA0, DMA0_Channel1, GD32_DMA0_CH1_CMASK, DMA0_CH1_VARIANT,  4, 1, GD32_DMA0_CH1_NUMBER},
+  {DMA0, DMA0_Channel2, GD32_DMA0_CH2_CMASK, DMA0_CH2_VARIANT,  8, 2, GD32_DMA0_CH2_NUMBER},
+  {DMA0, DMA0_Channel3, GD32_DMA0_CH3_CMASK, DMA0_CH3_VARIANT, 12, 3, GD32_DMA0_CH3_NUMBER},
+  {DMA0, DMA0_Channel4, GD32_DMA0_CH4_CMASK, DMA0_CH4_VARIANT, 16, 4, GD32_DMA0_CH4_NUMBER},
+  {DMA0, DMA0_Channel5, GD32_DMA0_CH5_CMASK, DMA0_CH5_VARIANT, 20, 5, GD32_DMA0_CH5_NUMBER},
+  {DMA0, DMA0_Channel6, GD32_DMA0_CH6_CMASK, DMA0_CH6_VARIANT, 24, 6, GD32_DMA0_CH6_NUMBER},
+  {DMA1, DMA1_Channel0, GD32_DMA1_CH0_CMASK, DMA1_CH0_VARIANT,  0, 0 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH0_NUMBER},
+  {DMA1, DMA1_Channel1, GD32_DMA1_CH1_CMASK, DMA1_CH1_VARIANT,  4, 1 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH1_NUMBER},
+  {DMA1, DMA1_Channel2, GD32_DMA1_CH2_CMASK, DMA1_CH2_VARIANT,  8, 2 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH2_NUMBER},
+  {DMA1, DMA1_Channel3, GD32_DMA1_CH3_CMASK, DMA1_CH3_VARIANT, 12, 3 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH3_NUMBER},
+  {DMA1, DMA1_Channel4, GD32_DMA1_CH4_CMASK, DMA1_CH4_VARIANT, 16, 4 + GD32_DMA0_NUM_CHANNELS, GD32_DMA1_CH4_NUMBER},
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Global DMA-related data structures.
+ */
+static struct {
+  /**
+   * @brief   Mask of the allocated streams.
+   */
+  uint32_t          allocated_mask;
+  /**
+   * @brief   Mask of the enabled streams ISRs.
+   */
+  uint32_t          isr_mask;
+  /**
+   * @brief   DMA IRQ redirectors.
+   */
+  struct {
+    /**
+     * @brief   DMA callback function.
+     */
+    gd32_dmaisr_t    func;
+    /**
+     * @brief   DMA callback parameter.
+     */
+    void              *param;
+  } streams[GD32_DMA_STREAMS];
+} dma;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if defined(GD32_DMA0_CH0_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 0 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH1_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 1 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH2_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 2 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH3_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 3 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH4_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 4 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH5_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 5 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH5_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA0_CH6_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA0 stream 6 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA0_CH6_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA0_STREAM6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA1_CH0_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA1 stream 0 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA1_CH0_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA1_STREAM0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA1_CH1_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA1 stream 1 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA1_CH1_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA1_STREAM1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA1_CH2_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA1 stream 2 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA1_CH2_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA1_STREAM2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA1_CH3_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA1 stream 3 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA1_CH3_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA1_STREAM3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if defined(GD32_DMA1_CH4_HANDLER) || defined(__DOXYGEN__)
+/**
+ * @brief   DMA1 stream 4 shared ISR.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(GD32_DMA1_CH4_HANDLER) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  dmaServeInterrupt(GD32_DMA1_STREAM4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   GD32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma.allocated_mask = 0U;
+  dma.isr_mask       = 0U;
+  for (i = 0; i < GD32_DMA_STREAMS; i++) {
+    _gd32_dma_streams[i].channel->CTL = GD32_DMA_CTL_RESET_VALUE;
+    dma.streams[i].func = NULL;
+  }
+  DMA0->INTC = 0xFFFFFFFFU;
+  DMA1->INTC = 0xFFFFFFFFU;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ *
+ * @param[in] id        numeric identifiers of a specific stream or:
+ *                      - @p GD32_DMA_STREAM_ID_ANY for any stream.
+ *                      - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
+ *                        on DMA0.
+ *                      - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
+ *                        on DMA1.
+ *                      .
+ * @param[in] priority  IRQ priority for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              Pointer to the allocated @p gd32_dma_stream_t
+ *                      structure.
+ * @retval NULL         if a/the stream is not available.
+ *
+ * @iclass
+ */
+const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
+                                          uint32_t priority,
+                                          gd32_dmaisr_t func,
+                                          void *param) {
+  uint32_t i, startid, endid;
+
+  osalDbgCheckClassI();
+
+  if (id < GD32_DMA_STREAMS) {
+    startid = id;
+    endid   = id;
+  } else {
+    osalDbgCheck(false);
+    return NULL;
+  }
+
+  for (i = startid; i <= endid; i++) {
+    uint32_t mask = (1U << i);
+    if ((dma.allocated_mask & mask) == 0U) {
+      const gd32_dma_stream_t *dmastp = GD32_DMA_STREAM(i);
+
+      /* Installs the DMA handler.*/
+      dma.streams[i].func  = func;
+      dma.streams[i].param = param;
+      dma.allocated_mask  |= mask;
+
+      /* Enabling DMA clocks required by the current streams set.*/
+      if ((GD32_DMA0_STREAMS_MASK & mask) != 0U) {
+        rcuEnableDMA0(true);
+      }
+
+      if ((GD32_DMA1_STREAMS_MASK & mask) != 0U) {
+        rcuEnableDMA1(true);
+      }
+
+      /* Enables the associated IRQ vector if not already enabled and if a
+         callback is defined.*/
+      if (func != NULL) {
+        if ((dma.isr_mask & dmastp->cmask) == 0U) {
+          eclicEnableVector(dmastp->vector, priority, ECLIC_DMA_TRIGGER);
+        }
+        dma.isr_mask |= mask;
+      }
+
+      /* Putting the stream in a known state.*/
+      dmaStreamDisable(dmastp);
+      dmastp->channel->CTL = GD32_DMA_CTL_RESET_VALUE;
+
+      return dmastp;
+    }
+  }
+
+  return NULL;
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ *
+ * @param[in] id        numeric identifiers of a specific stream or:
+ *                      - @p GD32_DMA_STREAM_ID_ANY for any stream.
+ *                      - @p GD32_DMA_STREAM_ID_ANY_DMA0 for any stream
+ *                        on DMA0.
+ *                      - @p GD32_DMA_STREAM_ID_ANY_DMA1 for any stream
+ *                        on DMA1.
+ *                      .
+ * @param[in] priority  IRQ priority for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              Pointer to the allocated @p gd32_dma_stream_t
+ *                      structure.
+ * @retval NULL         if a/the stream is not available.
+ *
+ * @api
+ */
+const gd32_dma_stream_t *dmaStreamAlloc(uint32_t id,
+                                         uint32_t priority,
+                                         gd32_dmaisr_t func,
+                                         void *param) {
+  const gd32_dma_stream_t *dmastp;
+
+  osalSysLock();
+  dmastp = dmaStreamAllocI(id, priority, func, param);
+  osalSysUnlock();
+
+  return dmastp;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @iclass
+ */
+void dmaStreamFreeI(const gd32_dma_stream_t *dmastp) {
+  uint32_t selfindex = (uint32_t)dmastp->selfindex;
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma.allocated_mask & (1 << selfindex)) != 0U,
+                "not allocated");
+
+  /* Marks the stream as not allocated.*/
+  dma.allocated_mask &= ~(1U << selfindex);
+  dma.isr_mask &= ~(1U << selfindex);
+
+  /* Disables the associated IRQ vector if it is no more in use.*/
+  if ((dma.isr_mask & dmastp->cmask) == 0U) {
+    eclicDisableVector(dmastp->vector);
+  }
+
+  /* Removes the DMA handler.*/
+  dma.streams[selfindex].func  = NULL;
+  dma.streams[selfindex].param = NULL;
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma.allocated_mask & GD32_DMA0_STREAMS_MASK) == 0U) {
+    rcuDisableDMA0();
+  }
+  if ((dma.allocated_mask & GD32_DMA1_STREAMS_MASK) == 0U) {
+    rcuDisableDMA1();
+  }
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @api
+ */
+void dmaStreamFree(const gd32_dma_stream_t *dmastp) {
+
+  osalSysLock();
+  dmaStreamFreeI(dmastp);
+  osalSysUnlock();
+}
+
+/**
+ * @brief   Serves a DMA IRQ.
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaServeInterrupt(const gd32_dma_stream_t *dmastp) {
+  uint32_t flags;
+  uint32_t selfindex = (uint32_t)dmastp->selfindex;
+
+  flags = (dmastp->dma->INTF >> dmastp->shift) & GD32_DMA_INTF_MASK;
+  if (flags & dmastp->channel->CTL) {
+    dmastp->dma->INTC = flags << dmastp->shift;
+    if (dma.streams[selfindex].func) {
+      dma.streams[selfindex].func(dma.streams[selfindex].param, flags);
+    }
+  }
+}
+
+#endif /* GD32_DMA_REQUIRED */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.h b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.h
new file mode 100644
index 000000000..3af7b44ef
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/DMA/gd32_dma.h
@@ -0,0 +1,439 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    DMA/gd32_dma.h
+ * @brief   DMA helper driver header.
+
+ * @addtogroup GD32_DMA
+ * @{
+ */
+
+#ifndef GD32_DMA_H
+#define GD32_DMA_H
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @details This is the total number of streams among all the DMA units.
+ */
+#define GD32_DMA_STREAMS           (GD32_DMA0_NUM_CHANNELS +              \
+                                     GD32_DMA1_NUM_CHANNELS)
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define GD32_DMA_INTF_MASK          0x0E
+
+/**
+ * @brief   Returns the request line associated to the specified stream.
+ * @note    In some GD32 manuals the request line is named confusingly
+ *          channel.
+ *
+ * @param[in] id        the unique numeric stream identifier
+ * @param[in] c         a stream/request association word, one request per
+ *                      nibble
+ * @return              Returns the request associated to the stream.
+ */
+#define GD32_DMA_GETCHANNEL(id, c)                                         \
+  (((uint32_t)(c) >> (((uint32_t)(id) % (uint32_t)GD32_DMA0_NUM_CHANNELS) * 4U)) & 15U)
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval false        invalid DMA priority.
+ * @retval true         correct DMA priority.
+ */
+#define GD32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0U) && ((prio) <= 3U))
+
+/**
+ * @brief   Checks if a DMA stream id is within the valid range.
+ *
+ * @param[in] id        DMA stream id
+ * @retval              The check result.
+ * @retval false        invalid DMA channel.
+ * @retval true         correct DMA channel.
+ */
+#define GD32_DMA_IS_VALID_STREAM(id) (((id) >= 0U) &&                      \
+                                       ((id) < GD32_DMA_STREAMS))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define GD32_DMA_STREAM_ID(dma, stream)                                    \
+  ((((dma)) * GD32_DMA0_NUM_CHANNELS) + ((stream)))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define GD32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1U << GD32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval false        id does not belong to the mask.
+ * @retval true         id belongs to the mask.
+ */
+#define GD32_DMA_IS_VALID_ID(id, mask) (((1U << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a gd32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the gd32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define GD32_DMA_STREAM(id)        (&_gd32_dma_streams[id])
+
+#define GD32_DMA0_STREAM0          GD32_DMA_STREAM(0)
+#define GD32_DMA0_STREAM1          GD32_DMA_STREAM(1)
+#define GD32_DMA0_STREAM2          GD32_DMA_STREAM(2)
+#define GD32_DMA0_STREAM3          GD32_DMA_STREAM(3)
+#define GD32_DMA0_STREAM4          GD32_DMA_STREAM(4)
+#define GD32_DMA0_STREAM5          GD32_DMA_STREAM(5)
+#define GD32_DMA0_STREAM6          GD32_DMA_STREAM(6)
+#define GD32_DMA1_STREAM0          GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 0)
+#define GD32_DMA1_STREAM1          GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 1)
+#define GD32_DMA1_STREAM2          GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 2)
+#define GD32_DMA1_STREAM3          GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 3)
+#define GD32_DMA1_STREAM4          GD32_DMA_STREAM(GD32_DMA0_NUM_CHANNELS + 4)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define GD32_DMA_CTL_RESET_VALUE   0x00000000U
+#define GD32_DMA_CTL_EN             DMA_CTL_CHEN
+#define GD32_DMA_CTL_ERRIE           DMA_CTL_ERRIE
+#define GD32_DMA_CTL_HTFIE           DMA_CTL_HTFIE
+#define GD32_DMA_CTL_FTFIE           DMA_CTL_FTFIE
+#define GD32_DMA_CTL_DIR_MASK       (DMA_CTL_DIR | DMA_CTL_M2M)
+#define GD32_DMA_CTL_DIR_P2M        0U
+#define GD32_DMA_CTL_DIR_M2P        DMA_CTL_DIR
+#define GD32_DMA_CTL_DIR_M2M        DMA_CTL_M2M
+#define GD32_DMA_CTL_CMEN           DMA_CTL_CMEN
+#define GD32_DMA_CTL_PNAGA           DMA_CTL_PNAGA
+#define GD32_DMA_CTL_MNAGA           DMA_CTL_MNAGA
+#define GD32_DMA_CTL_PWIDTH_MASK     DMA_CTL_PWIDTH
+#define GD32_DMA_CTL_PWIDTH_BYTE     0U
+#define GD32_DMA_CTL_PWIDTH_HWORD    DMA_CTL_PWIDTH_0
+#define GD32_DMA_CTL_PWIDTH_WORD     DMA_CTL_PWIDTH_1
+#define GD32_DMA_CTL_MWIDTH_MASK     DMA_CTL_MWIDTH
+#define GD32_DMA_CTL_MWIDTH_BYTE     0U
+#define GD32_DMA_CTL_MWIDTH_HWORD    DMA_CTL_MWIDTH_0
+#define GD32_DMA_CTL_MWIDTH_WORD     DMA_CTL_MWIDTH_1
+#define GD32_DMA_CTL_SIZE_MASK      (GD32_DMA_CTL_PWIDTH_MASK |              \
+                                     GD32_DMA_CTL_MWIDTH_MASK)
+#define GD32_DMA_CTL_PRIO_MASK        DMA_CTL_PRIO
+#define GD32_DMA_CTL_PRIO(n)          ((n) << 12U)
+/** @} */
+
+/**
+ * @name    Request line selector macro
+ * @{
+ */
+#define GD32_DMA_CTL_CHSEL_MASK     0U
+#define GD32_DMA_CTL_CHSEL(n)       0U
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define GD32_DMA_INTF_FEIF          0U
+#define GD32_DMA_INTF_ERRIF          DMA_INTF_ERRIF0
+#define GD32_DMA_INTF_HTFIF          DMA_INTF_HTFIF0
+#define GD32_DMA_INTF_FTFIF          DMA_INTF_FTFIF0
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !defined(GD32_DMA0_NUM_CHANNELS)
+#error "GD32_DMA0_NUM_CHANNELS not defined in registry"
+#endif
+
+#if !defined(GD32_DMA1_NUM_CHANNELS)
+#error "GD32_DMA1_NUM_CHANNELS not defined in registry"
+#endif
+
+#if (GD32_DMA0_NUM_CHANNELS < 0) || (GD32_DMA0_NUM_CHANNELS > 7)
+#error "unsupported channels configuration"
+#endif
+
+#if (GD32_DMA1_NUM_CHANNELS < 0) || (GD32_DMA1_NUM_CHANNELS > 5)
+#error "unsupported channels configuration"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a DMA callback.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*gd32_dmaisr_t)(void *p, uint32_t flags);
+
+/**
+ * @brief   GD32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_TypeDef           *dma;           /**< @brief Associated DMA.         */
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  uint32_t              cmask;          /**< @brief Mask of streams sharing
+                                             the same ISR.                  */
+  uint8_t               dummy;          /**< @brief Filler.                 */
+  uint8_t               shift;          /**< @brief Bit offset in ISR, IFCR
+                                             and CSELR registers.           */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} gd32_dma_stream_t;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @param[in] addr      value to be written in the PADDR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->PADDR = (uint32_t)(addr);                               \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @param[in] addr      value to be written in the MADDR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->MADDR = (uint32_t)(addr);                               \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNT register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNT = (uint32_t)(size);                              \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNT))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CTL  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CTL |= GD32_DMA_CTL_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CTL &= ~(GD32_DMA_CTL_FTFIE | GD32_DMA_CTL_HTFIE |       \
+                              GD32_DMA_CTL_ERRIE | GD32_DMA_CTL_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  (dmastp)->dma->INTC = GD32_DMA_INTF_MASK << (dmastp)->shift;              \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p GD32_DMA_CTL_MNAGA
+ *                      - @p GD32_DMA_CTL_PNAGA
+ *                      - @p GD32_DMA_CTL_DIR_M2M
+ *                      - @p GD32_DMA_CTL_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           GD32_DMA_CTL_MNAGA | GD32_DMA_CTL_PNAGA |          \
+                           GD32_DMA_CTL_DIR_M2M | GD32_DMA_CTL_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAlloc().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a gd32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNT > 0U)                                     \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const gd32_dma_stream_t _gd32_dma_streams[GD32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  const gd32_dma_stream_t *dmaStreamAllocI(uint32_t id,
+                                            uint32_t priority,
+                                            gd32_dmaisr_t func,
+                                            void *param);
+  const gd32_dma_stream_t *dmaStreamAlloc(uint32_t id,
+                                           uint32_t priority,
+                                           gd32_dmaisr_t func,
+                                           void *param);
+  void dmaStreamFreeI(const gd32_dma_stream_t *dmastp);
+  void dmaStreamFree(const gd32_dma_stream_t *dmastp);
+  void dmaServeInterrupt(const gd32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* GD32_DMA_H */
+
+/** @} */
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/driver.mk b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/driver.mk
new file mode 100644
index 000000000..2f0fca3ff
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/driver.mk
@@ -0,0 +1,9 @@
+ifeq ($(USE_SMART_BUILD),yes)
+ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
+endif
+else
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
+endif
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/GD/GD32VF103/GPIO
diff --git a/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
new file mode 100644
index 000000000..3d0768d69
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/GD/GD32VF103/GPIO/hal_pal_lld.c
@@ -0,0 +1,286 @@
+/*
+     ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+     ChibiOS - Copyright (C) 2021 Stefan Kerkmann
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    GPIO/hal_pal_lld.c
+ * @brief   GD32 PAL low level driver code.
+ *
+ * @addtogroup PAL
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+