1 files changed, 534 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h b/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h
new file mode 100644
index 000000000..116f5cb5b
--- /dev/null
+++ b/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h
@@ -0,0 +1,534 @@
+/*
+    Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/**
+ * @file    TIMv1/wb32_tim.h
+ * @brief   WB32 TIM units common header.
+ * @note    This file requires definitions from the ST WB32 header file.
+ *
+ * @addtogroup WB32_TIMv1
+ * @{
+ */
+#ifndef WB32_TIM_H
+#define WB32_TIM_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/**
+ * @name    TIM_CR1 register
+ * @{
+ */
+#define WB32_TIM_CR1_CEN                       (1U << 0)
+#define WB32_TIM_CR1_UDIS                      (1U << 1)
+#define WB32_TIM_CR1_URS                       (1U << 2)
+#define WB32_TIM_CR1_OPM                       (1U << 3)
+#define WB32_TIM_CR1_DIR                       (1U << 4)
+#define WB32_TIM_CR1_CMS_MASK                  (3U << 5)
+#define WB32_TIM_CR1_CMS(n)                    ((n) << 5)
+#define WB32_TIM_CR1_ARPE                      (1U << 7)
+#define WB32_TIM_CR1_CKD_MASK                  (3U << 8)
+#define WB32_TIM_CR1_CKD(n)                    ((n) << 8)
+#define WB32_TIM_CR1_UIFREMAP                  (1U << 11)
+/** @} */
+/**
+ * @name    TIM_CR2 register
+ * @{
+ */
+#define WB32_TIM_CR2_CCPC                      (1U << 0)
+#define WB32_TIM_CR2_CCUS                      (1U << 2)
+#define WB32_TIM_CR2_CCDS                      (1U << 3)
+#define WB32_TIM_CR2_MMS_MASK                  (7U << 4)
+#define WB32_TIM_CR2_MMS(n)                    ((n) << 4)
+#define WB32_TIM_CR2_TI1S                      (1U << 7)
+#define WB32_TIM_CR2_OIS1                      (1U << 8)
+#define WB32_TIM_CR2_OIS1N                     (1U << 9)
+#define WB32_TIM_CR2_OIS2                      (1U << 10)
+#define WB32_TIM_CR2_OIS2N                     (1U << 11)
+#define WB32_TIM_CR2_OIS3                      (1U << 12)
+#define WB32_TIM_CR2_OIS3N                     (1U << 13)
+#define WB32_TIM_CR2_OIS4                      (1U << 14)
+#define WB32_TIM_CR2_OIS5                      (1U << 16)
+#define WB32_TIM_CR2_OIS6                      (1U << 18)
+#define WB32_TIM_CR2_MMS2_MASK                 (15U << 20)
+#define WB32_TIM_CR2_MMS2(n)                   ((n) << 20)
+/** @} */
+/**
+ * @name    TIM_SMCR register
+ * @{
+ */
+#define WB32_TIM_SMCR_SMS_MASK                 ((7U << 0) | (1U << 16))
+#define WB32_TIM_SMCR_SMS(n)                   ((((n) & 7) << 0) |          \
+                                                (((n) >> 3) << 16))
+#define WB32_TIM_SMCR_OCCS                     (1U << 3)
+#define WB32_TIM_SMCR_TS_MASK                  (7U << 4)
+#define WB32_TIM_SMCR_TS(n)                    ((n) << 4)
+#define WB32_TIM_SMCR_MSM                      (1U << 7)
+#define WB32_TIM_SMCR_ETF_MASK                 (15U << 8)
+#define WB32_TIM_SMCR_ETF(n)                   ((n) << 8)
+#define WB32_TIM_SMCR_ETPS_MASK                (3U << 12)
+#define WB32_TIM_SMCR_ETPS(n)                  ((n) << 12)
+#define WB32_TIM_SMCR_ECE                      (1U << 14)
+#define WB32_TIM_SMCR_ETP                      (1U << 15)
+/** @} */
+/**
+ * @name    TIM_DIER register
+ * @{
+ */
+#define WB32_TIM_DIER_UIE                      (1U << 0)
+#define WB32_TIM_DIER_CC1IE                    (1U << 1)
+#define WB32_TIM_DIER_CC2IE                    (1U << 2)
+#define WB32_TIM_DIER_CC3IE                    (1U << 3)
+#define WB32_TIM_DIER_CC4IE                    (1U << 4)
+#define WB32_TIM_DIER_COMIE                    (1U << 5)
+#define WB32_TIM_DIER_TIE                      (1U << 6)
+#define WB32_TIM_DIER_BIE                      (1U << 7)
+#define WB32_TIM_DIER_UDE                      (1U << 8)
+#define WB32_TIM_DIER_CC1DE                    (1U << 9)
+#define WB32_TIM_DIER_CC2DE                    (1U << 10)
+#define WB32_TIM_DIER_CC3DE                    (1U << 11)
+#define WB32_TIM_DIER_CC4DE                    (1U << 12)
+#define WB32_TIM_DIER_COMDE                    (1U << 13)
+#define WB32_TIM_DIER_TDE                      (1U << 14)
+#define WB32_TIM_DIER_IRQ_MASK                 (WB32_TIM_DIER_UIE   |       \
+                                                WB32_TIM_DIER_CC1IE |       \
+                                                WB32_TIM_DIER_CC2IE |       \
+                                                WB32_TIM_DIER_CC3IE |       \
+                                                WB32_TIM_DIER_CC4IE |       \
+                                                WB32_TIM_DIER_COMIE |       \
+                                                WB32_TIM_DIER_TIE   |       \
+                                                WB32_TIM_DIER_BIE)
+/** @} */
+/**
+ * @name    TIM_SR register
+ * @{
+ */
+#define WB32_TIM_SR_UIF                        (1U << 0)
+#define WB32_TIM_SR_CC1IF                      (1U << 1)
+#define WB32_TIM_SR_CC2IF                      (1U << 2)
+#define WB32_TIM_SR_CC3IF                      (1U << 3)
+#define WB32_TIM_SR_CC4IF                      (1U << 4)
+#define WB32_TIM_SR_COMIF                      (1U << 5)
+#define WB32_TIM_SR_TIF                        (1U << 6)
+#define WB32_TIM_SR_BIF                        (1U << 7)
+#define WB32_TIM_SR_B2IF                       (1U << 8)
+#define WB32_TIM_SR_CC1OF                      (1U << 9)
+#define WB32_TIM_SR_CC2OF                      (1U << 10)
+#define WB32_TIM_SR_CC3OF                      (1U << 11)
+#define WB32_TIM_SR_CC4OF                      (1U << 12)
+#define WB32_TIM_SR_CC5IF                      (1U << 16)
+#define WB32_TIM_SR_CC6IF                      (1U << 17)
+/** @} */
+/**
+ * @name    TIM_EGR register
+ * @{
+ */
+#define WB32_TIM_EGR_UG                        (1U << 0)
+#define WB32_TIM_EGR_CC1G                      (1U << 1)
+#define WB32_TIM_EGR_CC2G                      (1U << 2)
+#define WB32_TIM_EGR_CC3G                      (1U << 3)
+#define WB32_TIM_EGR_CC4G                      (1U << 4)
+#define WB32_TIM_EGR_COMG                      (1U << 5)
+#define WB32_TIM_EGR_TG                        (1U << 6)
+#define WB32_TIM_EGR_BG                        (1U << 7)
+#define WB32_TIM_EGR_B2G                       (1U << 8)
+/** @} */
+/**
+ * @name    TIM_CCMR1 register (output)
+ * @{
+ */
+#define WB32_TIM_CCMR1_CC1S_MASK               (3U << 0)
+#define WB32_TIM_CCMR1_CC1S(n)                 ((n) << 0)
+#define WB32_TIM_CCMR1_OC1FE                   (1U << 2)
+#define WB32_TIM_CCMR1_OC1PE                   (1U << 3)
+#define WB32_TIM_CCMR1_OC1M_MASK               ((7U << 4) | (1U << 16))
+#define WB32_TIM_CCMR1_OC1M(n)                 ((((n) & 7) << 4) |          \
+                                                (((n) >> 3) << 16))
+#define WB32_TIM_CCMR1_OC1CE                   (1U << 7)
+#define WB32_TIM_CCMR1_CC2S_MASK               (3U << 8)
+#define WB32_TIM_CCMR1_CC2S(n)                 ((n) << 8)
+#define WB32_TIM_CCMR1_OC2FE                   (1U << 10)
+#define WB32_TIM_CCMR1_OC2PE                   (1U << 11)
+#define WB32_TIM_CCMR1_OC2M_MASK               ((7U << 12) | (1U << 24))
+#define WB32_TIM_CCMR1_OC2M(n)                 ((((n) & 7) << 12) |         \
+                                                (((n) >> 3) << 24))
+#define WB32_TIM_CCMR1_OC2CE                   (1U << 15)
+/** @} */
+/**
+ * @name    CCMR1 register (input)
+ * @{
+ */
+#define WB32_TIM_CCMR1_IC1PSC_MASK             (3U << 2)
+#define WB32_TIM_CCMR1_IC1PSC(n)               ((n) << 2)
+#define WB32_TIM_CCMR1_IC1F_MASK               (15U << 4)
+#define WB32_TIM_CCMR1_IC1F(n)                 ((n) << 4)
+#define WB32_TIM_CCMR1_IC2PSC_MASK             (3U << 10)
+#define WB32_TIM_CCMR1_IC2PSC(n)               ((n) << 10)
+#define WB32_TIM_CCMR1_IC2F_MASK               (15U << 12)
+#define WB32_TIM_CCMR1_IC2F(n)                 ((n) << 12)
+/** @} */
+/**
+ * @name    TIM_CCMR2 register (output)
+ * @{
+ */
+#define WB32_TIM_CCMR2_CC3S_MASK               (3U << 0)
+#define WB32_TIM_CCMR2_CC3S(n)                 ((n) << 0)
+#define WB32_TIM_CCMR2_OC3FE                   (1U << 2)
+#define WB32_TIM_CCMR2_OC3PE                   (1U << 3)
+#define WB32_TIM_CCMR2_OC3M_MASK               ((7U << 4) | (1U << 16))
+#define WB32_TIM_CCMR2_OC3M(n)                 ((((n) & 7) << 4) |          \
+                                                (((n) >> 3) << 16))
+#define WB32_TIM_CCMR2_OC3CE                   (1U << 7)
+#define WB32_TIM_CCMR2_CC4S_MASK               (3U << 8)
+#define WB32_TIM_CCMR2_CC4S(n)                 ((n) << 8)
+#define WB32_TIM_CCMR2_OC4FE                   (1U << 10)
+#define WB32_TIM_CCMR2_OC4PE                   (1U << 11)
+#define WB32_TIM_CCMR2_OC4M_MASK               ((7U << 12) | (1U << 24))
+#define WB32_TIM_CCMR2_OC4M(n)                 ((((n) & 7) << 12) |         \
+                                                (((n) >> 3) << 24))
+#define WB32_TIM_CCMR2_OC4CE                   (1U << 15)
+/** @} */
+/**
+ * @name    TIM_CCMR2 register (input)
+ * @{
+ */
+#define WB32_TIM_CCMR2_IC3PSC_MASK             (3U << 2)
+#define WB32_TIM_CCMR2_IC3PSC(n)               ((n) << 2)
+#define WB32_TIM_CCMR2_IC3F_MASK               (15U << 4)
+#define WB32_TIM_CCMR2_IC3F(n)                 ((n) << 4)
+#define WB32_TIM_CCMR2_IC4PSC_MASK             (3U << 10)
+#define WB32_TIM_CCMR2_IC4PSC(n)               ((n) << 10)
+#define WB32_TIM_CCMR2_IC4F_MASK               (15U << 12)
+#define WB32_TIM_CCMR2_IC4F(n)                 ((n) << 12)
+/** @} */
+/**
+ * @name    TIM_CCER register
+ * @{
+ */
+#define WB32_TIM_CCER_CC1E                     (1U << 0)
+#define WB32_TIM_CCER_CC1P                     (1U << 1)
+#define WB32_TIM_CCER_CC1NE                    (1U << 2)
+#define WB32_TIM_CCER_CC1NP                    (1U << 3)
+#define WB32_TIM_CCER_CC2E                     (1U << 4)
+#define WB32_TIM_CCER_CC2P                     (1U << 5)
+#define WB32_TIM_CCER_CC2NE                    (1U << 6)
+#define WB32_TIM_CCER_CC2NP                    (1U << 7)
+#define WB32_TIM_CCER_CC3E                     (1U << 8)
+#define WB32_TIM_CCER_CC3P                     (1U << 9)
+#define WB32_TIM_CCER_CC3NE                    (1U << 10)
+#define WB32_TIM_CCER_CC3NP                    (1U << 11)
+#define WB32_TIM_CCER_CC4E                     (1U << 12)
+#define WB32_TIM_CCER_CC4P                     (1U << 13)
+#define WB32_TIM_CCER_CC4NE                    (1U << 14)
+#define WB32_TIM_CCER_CC4NP                    (1U << 15)
+#define WB32_TIM_CCER_CC5E                     (1U << 16)
+#define WB32_TIM_CCER_CC5P                     (1U << 17)
+#define WB32_TIM_CCER_CC6E                     (1U << 20)
+#define WB32_TIM_CCER_CC6P                     (1U << 21)
+/** @} */
+/**
+ * @name    TIM_CNT register
+ * @{
+ */
+#define WB32_TIM_CNT_UIFCPY                    (1U << 31)
+/** @} */
+/**
+ * @name    TIM_BDTR register
+ * @{
+ */
+#define WB32_TIM_BDTR_DTG_MASK                 (255U << 0)
+#define WB32_TIM_BDTR_DTG(n)                   ((n) << 0)
+#define WB32_TIM_BDTR_LOCK_MASK                (3U << 8)
+#define WB32_TIM_BDTR_LOCK(n)                  ((n) << 8)
+#define WB32_TIM_BDTR_OSSI                     (1U << 10)
+#define WB32_TIM_BDTR_OSSR                     (1U << 11)
+#define WB32_TIM_BDTR_BKE                      (1U << 12)
+#define WB32_TIM_BDTR_BKP                      (1U << 13)
+#define WB32_TIM_BDTR_AOE                      (1U << 14)
+#define WB32_TIM_BDTR_MOE                      (1U << 15)
+#define WB32_TIM_BDTR_BKF_MASK                 (15U << 16)
+#define WB32_TIM_BDTR_BKF(n)                   ((n) << 16)
+#define WB32_TIM_BDTR_BK2F_MASK                (15U << 20)
+#define WB32_TIM_BDTR_BK2F(n)                  ((n) << 20)
+#define WB32_TIM_BDTR_BK2E                     (1U << 24)
+#define WB32_TIM_BDTR_BK2P                     (1U << 25)
+/** @} */
+/**
+ * @name    TIM_DCR register
+ * @{
+ */
+#define WB32_TIM_DCR_DBA_MASK                  (31U << 0)
+#define WB32_TIM_DCR_DBA(n)                    ((n) << 0)
+#define WB32_TIM_DCR_DBL_MASK                  (31U << 8)
+#define WB32_TIM_DCR_DBL(n)                    ((n) << 8)
+/** @} */
+/**
+ * @name    TIM16_OR register
+ * @{
+ */
+#define WB32_TIM16_OR_TI1_RMP_MASK             (3U << 6)
+#define WB32_TIM16_OR_TI1_RMP(n)               ((n) << 6)
+/** @} */
+/**
+ * @name    TIM_OR register
+ * @{
+ */
+#define WB32_TIM_OR_ETR_RMP_MASK               (15U << 0)
+#define WB32_TIM_OR_ETR_RMP(n)                 ((n) << 0)
+/** @} */
+/**
+ * @name    TIM_CCMR3 register
+ * @{
+ */
+#define WB32_TIM_CCMR3_OC5FE                   (1U << 2)
+#define WB32_TIM_CCMR3_OC5PE                   (1U << 3)
+#define WB32_TIM_CCMR3_OC5M_MASK               ((7U << 4) | (1U << 16))
+#define WB32_TIM_CCMR3_OC5M(n)                 ((((n) & 7) << 4) |          \
+                                                (((n) >> 2) << 16))
+#define WB32_TIM_CCMR3_OC5CE                   (1U << 7)
+#define WB32_TIM_CCMR3_OC6FE                   (1U << 10)
+#define WB32_TIM_CCMR3_OC6PE                   (1U << 11)
+#define WB32_TIM_CCMR3_OC6M_MASK               ((7U << 12) | (1U << 24))
+#define WB32_TIM_CCMR3_OC6M(n)                 ((((n) & 7) << 12) |         \
+                                                (((n) >> 2) << 24))
+#define WB32_TIM_CCMR3_OC6CE                   (1U << 15)
+/** @} */
+/**
+ * @name    LPTIM_ISR register
+ * @{
+ */
+#define WB32_LPTIM_ISR_CMPM                    (1U << 0)
+#define WB32_LPTIM_ISR_ARRM                    (1U << 1)
+#define WB32_LPTIM_ISR_EXTTRIG                 (1U << 2)
+#define WB32_LPTIM_ISR_CMPOK                   (1U << 3)
+#define WB32_LPTIM_ISR_ARROK                   (1U << 4)
+#define WB32_LPTIM_ISR_UP                      (1U << 5)
+#define WB32_LPTIM_ISR_DOWN                    (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_ICR register
+ * @{
+ */
+#define WB32_LPTIM_ICR_CMPMCF                  (1U << 0)
+#define WB32_LPTIM_ICR_ARRMCF                  (1U << 1)
+#define WB32_LPTIM_ICR_EXTTRIGCF               (1U << 2)
+#define WB32_LPTIM_ICR_CMPOKCF                 (1U << 3)
+#define WB32_LPTIM_ICR_ARROKCF                 (1U << 4)
+#define WB32_LPTIM_ICR_UPCF                    (1U << 5)
+#define WB32_LPTIM_ICR_DOWNCF                  (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_IER register
+ * @{
+ */
+#define WB32_LPTIM_IER_CMPMIE                  (1U << 0)
+#define WB32_LPTIM_IER_ARRMIE                  (1U << 1)
+#define WB32_LPTIM_IER_EXTTRIGIE               (1U << 2)
+#define WB32_LPTIM_IER_CMPOKIE                 (1U << 3)
+#define WB32_LPTIM_IER_ARROKIE                 (1U << 4)
+#define WB32_LPTIM_IER_UPIE                    (1U << 5)
+#define WB32_LPTIM_IER_DOWNIE                  (1U << 6)
+/** @} */
+/**
+ * @name    LPTIM_CFGR register
+ * @{
+ */
+#define WB32_LPTIM_CFGR_CKSEL                  (1U << 0)
+#define WB32_LPTIM_CFGR_CKPOL_MASK             (3U << 1)
+#define WB32_LPTIM_CFGR_CKPOL(n)               ((n) << 1)
+#define WB32_LPTIM_CFGR_CKFLT_MASK             (3U << 3)
+#define WB32_LPTIM_CFGR_CKFLT(n)               ((n) << 3)
+#define WB32_LPTIM_CFGR_TRGFLT_MASK            (3U << 6)
+#define WB32_LPTIM_CFGR_TRGFLT(n)              ((n) << 6)
+#define WB32_LPTIM_CFGR_PRESC_MASK             (7U << 9)
+#define WB32_LPTIM_CFGR_PRESC(n)               ((n) << 9)
+#define WB32_LPTIM_CFGR_TRIGSEL_MASK           (7U << 13)
+#define WB32_LPTIM_CFGR_TRIGSEL(n)             ((n) << 13)
+#define WB32_LPTIM_CFGR_TRIGEN_MASK            (3U << 17)
+#define WB32_LPTIM_CFGR_TRIGEN(n)              ((n) << 17)
+#define WB32_LPTIM_CFGR_TIMOUT                 (1U << 19)
+#define WB32_LPTIM_CFGR_WAVE                   (1U << 20)
+#define WB32_LPTIM_CFGR_WAVPOL                 (1U << 21)
+#define WB32_LPTIM_CFGR_PRELOAD                (1U << 22)
+#define WB32_LPTIM_CFGR_COUNTMODE              (1U << 23)
+#define WB32_LPTIM_CFGR_ENC                    (1U << 24)
+/** @} */
+/**
+ * @name    LPTIM_CR register
+ * @{
+ */
+#define WB32_LPTIM_CR_ENABLE                   (1U << 0)
+#define WB32_LPTIM_CR_SNGSTRT                  (1U << 1)
+#define WB32_LPTIM_CR_CNTSTRT                  (1U << 2)
+/** @} */
+/**
+ * @name    LPTIM_OR register
+ * @{
+ */
+#define WB32_LPTIM_OR_0                        (1U << 0)
+#define WB32_LPTIM_OR_1                        (1U << 1)
+/** @} */
+/**
+ * @name    TIM units references
+ * @{
+ */
+#define WB32_TIM1                              ((wb32_tim_t *)TIM1_BASE)
+#define WB32_TIM2                              ((wb32_tim_t *)TIM2_BASE)
+#define WB32_TIM3                              ((wb32_tim_t *)TIM3_BASE)
+#define WB32_TIM4                              ((wb32_tim_t *)TIM4_BASE)
+#define WB32_LPTIM1                            ((wb32_lptim_t *)LPTIM1_BASE)
+#define WB32_LPTIM2                            ((wb32_lptim_t *)LPTIM2_BASE)
+/** @} */
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   WB32 TIM registers block.
+ * @note    This is the most general known form, not all timers have
+ *          necessarily all registers and bits.
+ */
+typedef struct {
+  volatile uint32_t     CR1;
+  volatile uint32_t     CR2;
+  volatile uint32_t     SMCR;
+  volatile uint32_t     DIER;
+  volatile uint32_t     SR;
+  volatile uint32_t     EGR;
+  volatile uint32_t     CCMR1;
+  volatile uint32_t     CCMR2;
+  volatile uint32_t     CCER;
+  volatile uint32_t     CNT;
+  volatile uint32_t     PSC;
+  volatile uint32_t     ARR;
+  volatile uint32_t     RCR;
+  volatile uint32_t     CCR[4];
+  volatile uint32_t     BDTR;
+  volatile uint32_t     DCR;
+  volatile uint32_t     DMAR;
+  volatile uint32_t     OR;
+  volatile uint32_t     CCMR3;
+  volatile uint32_t     CCXR[2];
+} wb32_tim_t;
+/**
+ * @brief   WB32 LPTIM registers block.
+ * @note    This is the most general known form, not all timers have
+ *          necessarily all registers and bits.
+ */
+typedef struct {
+  volatile uint32_t     ISR;
+  volatile uint32_t     ICR;
+  volatile uint32_t     IER;
+  volatile uint32_t     CFGR;
+  volatile uint32_t     CR;
+  volatile uint32_t     CMP;
+  volatile uint32_t     ARR;
+  volatile uint32_t     CNT;
+  volatile uint32_t     OR;
+} wb32_lptim_t;
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+#endif /* WB32_TIM_H */
+/** @} */

diff --git a/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h b/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h new file mode 100644 index 000000000..116f5cb5b --- /dev/null +++ b/lib/chibios-contrib/os/hal/ports/WB32/LLD/TIMv1/wb32_tim.h
@@ -0,0 +1,534 @@
	1	/*
	2	Copyright (C) 2021 Westberry Technology (ChangZhou) Corp., Ltd
	3
	4	Licensed under the Apache License, Version 2.0 (the "License");
	5	you may not use this file except in compliance with the License.
	6	You may obtain a copy of the License at
	7
	8	http://www.apache.org/licenses/LICENSE-2.0
	9
	10	Unless required by applicable law or agreed to in writing, software
	11	distributed under the License is distributed on an "AS IS" BASIS,
	12	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
	13	See the License for the specific language governing permissions and
	14	limitations under the License.
	15	*/
	16
	17	/**
	18	* @file TIMv1/wb32_tim.h
	19	* @brief WB32 TIM units common header.
	20	* @note This file requires definitions from the ST WB32 header file.
	21	*
	22	* @addtogroup WB32_TIMv1
	23	* @{
	24	*/
	25
	26	#ifndef WB32_TIM_H
	27	#define WB32_TIM_H
	28
	29	/===========================================================================/
	30	/* Driver constants. */
	31	/===========================================================================/
	32
	33	/**
	34	* @name TIM_CR1 register
	35	* @{
	36	*/
	37	#define WB32_TIM_CR1_CEN (1U << 0)
	38	#define WB32_TIM_CR1_UDIS (1U << 1)
	39	#define WB32_TIM_CR1_URS (1U << 2)
	40	#define WB32_TIM_CR1_OPM (1U << 3)
	41	#define WB32_TIM_CR1_DIR (1U << 4)
	42
	43	#define WB32_TIM_CR1_CMS_MASK (3U << 5)
	44	#define WB32_TIM_CR1_CMS(n) ((n) << 5)
	45
	46	#define WB32_TIM_CR1_ARPE (1U << 7)
	47
	48	#define WB32_TIM_CR1_CKD_MASK (3U << 8)
	49	#define WB32_TIM_CR1_CKD(n) ((n) << 8)
	50
	51	#define WB32_TIM_CR1_UIFREMAP (1U << 11)
	52	/** @} */
	53
	54	/**
	55	* @name TIM_CR2 register
	56	* @{
	57	*/
	58	#define WB32_TIM_CR2_CCPC (1U << 0)
	59	#define WB32_TIM_CR2_CCUS (1U << 2)
	60	#define WB32_TIM_CR2_CCDS (1U << 3)
	61
	62	#define WB32_TIM_CR2_MMS_MASK (7U << 4)
	63	#define WB32_TIM_CR2_MMS(n) ((n) << 4)
	64
	65	#define WB32_TIM_CR2_TI1S (1U << 7)
	66	#define WB32_TIM_CR2_OIS1 (1U << 8)
	67	#define WB32_TIM_CR2_OIS1N (1U << 9)
	68	#define WB32_TIM_CR2_OIS2 (1U << 10)
	69	#define WB32_TIM_CR2_OIS2N (1U << 11)
	70	#define WB32_TIM_CR2_OIS3 (1U << 12)
	71	#define WB32_TIM_CR2_OIS3N (1U << 13)
	72	#define WB32_TIM_CR2_OIS4 (1U << 14)
	73	#define WB32_TIM_CR2_OIS5 (1U << 16)
	74	#define WB32_TIM_CR2_OIS6 (1U << 18)
	75
	76	#define WB32_TIM_CR2_MMS2_MASK (15U << 20)
	77	#define WB32_TIM_CR2_MMS2(n) ((n) << 20)
	78	/** @} */
	79
	80	/**
	81	* @name TIM_SMCR register
	82	* @{
	83	*/
	84	#define WB32_TIM_SMCR_SMS_MASK ((7U << 0) \| (1U << 16))
	85	#define WB32_TIM_SMCR_SMS(n) ((((n) & 7) << 0) \| \
	86	(((n) >> 3) << 16))
	87
	88	#define WB32_TIM_SMCR_OCCS (1U << 3)
	89
	90	#define WB32_TIM_SMCR_TS_MASK (7U << 4)
	91	#define WB32_TIM_SMCR_TS(n) ((n) << 4)
	92
	93	#define WB32_TIM_SMCR_MSM (1U << 7)
	94
	95	#define WB32_TIM_SMCR_ETF_MASK (15U << 8)
	96	#define WB32_TIM_SMCR_ETF(n) ((n) << 8)
	97
	98	#define WB32_TIM_SMCR_ETPS_MASK (3U << 12)
	99	#define WB32_TIM_SMCR_ETPS(n) ((n) << 12)
	100
	101	#define WB32_TIM_SMCR_ECE (1U << 14)
	102	#define WB32_TIM_SMCR_ETP (1U << 15)
	103	/** @} */
	104
	105	/**
	106	* @name TIM_DIER register
	107	* @{
	108	*/
	109	#define WB32_TIM_DIER_UIE (1U << 0)
	110	#define WB32_TIM_DIER_CC1IE (1U << 1)
	111	#define WB32_TIM_DIER_CC2IE (1U << 2)
	112	#define WB32_TIM_DIER_CC3IE (1U << 3)
	113	#define WB32_TIM_DIER_CC4IE (1U << 4)
	114	#define WB32_TIM_DIER_COMIE (1U << 5)
	115	#define WB32_TIM_DIER_TIE (1U << 6)
	116	#define WB32_TIM_DIER_BIE (1U << 7)
	117	#define WB32_TIM_DIER_UDE (1U << 8)
	118	#define WB32_TIM_DIER_CC1DE (1U << 9)
	119	#define WB32_TIM_DIER_CC2DE (1U << 10)
	120	#define WB32_TIM_DIER_CC3DE (1U << 11)
	121	#define WB32_TIM_DIER_CC4DE (1U << 12)
	122	#define WB32_TIM_DIER_COMDE (1U << 13)
	123	#define WB32_TIM_DIER_TDE (1U << 14)
	124
	125	#define WB32_TIM_DIER_IRQ_MASK (WB32_TIM_DIER_UIE \| \
	126	WB32_TIM_DIER_CC1IE \| \
	127	WB32_TIM_DIER_CC2IE \| \
	128	WB32_TIM_DIER_CC3IE \| \
	129	WB32_TIM_DIER_CC4IE \| \
	130	WB32_TIM_DIER_COMIE \| \
	131	WB32_TIM_DIER_TIE \| \
	132	WB32_TIM_DIER_BIE)
	133
	134	/** @} */
	135
	136	/**
	137	* @name TIM_SR register
	138	* @{
	139	*/
	140	#define WB32_TIM_SR_UIF (1U << 0)
	141	#define WB32_TIM_SR_CC1IF (1U << 1)
	142	#define WB32_TIM_SR_CC2IF (1U << 2)
	143	#define WB32_TIM_SR_CC3IF (1U << 3)
	144	#define WB32_TIM_SR_CC4IF (1U << 4)
	145	#define WB32_TIM_SR_COMIF (1U << 5)
	146	#define WB32_TIM_SR_TIF (1U << 6)
	147	#define WB32_TIM_SR_BIF (1U << 7)
	148	#define WB32_TIM_SR_B2IF (1U << 8)
	149	#define WB32_TIM_SR_CC1OF (1U << 9)
	150	#define WB32_TIM_SR_CC2OF (1U << 10)
	151	#define WB32_TIM_SR_CC3OF (1U << 11)
	152	#define WB32_TIM_SR_CC4OF (1U << 12)
	153	#define WB32_TIM_SR_CC5IF (1U << 16)
	154	#define WB32_TIM_SR_CC6IF (1U << 17)
	155	/** @} */
	156
	157	/**
	158	* @name TIM_EGR register
	159	* @{
	160	*/
	161	#define WB32_TIM_EGR_UG (1U << 0)
	162	#define WB32_TIM_EGR_CC1G (1U << 1)
	163	#define WB32_TIM_EGR_CC2G (1U << 2)
	164	#define WB32_TIM_EGR_CC3G (1U << 3)
	165	#define WB32_TIM_EGR_CC4G (1U << 4)
	166	#define WB32_TIM_EGR_COMG (1U << 5)
	167	#define WB32_TIM_EGR_TG (1U << 6)
	168	#define WB32_TIM_EGR_BG (1U << 7)
	169	#define WB32_TIM_EGR_B2G (1U << 8)
	170	/** @} */
	171
	172	/**
	173	* @name TIM_CCMR1 register (output)
	174	* @{
	175	*/
	176	#define WB32_TIM_CCMR1_CC1S_MASK (3U << 0)
	177	#define WB32_TIM_CCMR1_CC1S(n) ((n) << 0)
	178
	179	#define WB32_TIM_CCMR1_OC1FE (1U << 2)
	180	#define WB32_TIM_CCMR1_OC1PE (1U << 3)
	181
	182	#define WB32_TIM_CCMR1_OC1M_MASK ((7U << 4) \| (1U << 16))
	183	#define WB32_TIM_CCMR1_OC1M(n) ((((n) & 7) << 4) \| \
	184	(((n) >> 3) << 16))
	185
	186	#define WB32_TIM_CCMR1_OC1CE (1U << 7)
	187
	188	#define WB32_TIM_CCMR1_CC2S_MASK (3U << 8)
	189	#define WB32_TIM_CCMR1_CC2S(n) ((n) << 8)
	190
	191	#define WB32_TIM_CCMR1_OC2FE (1U << 10)
	192	#define WB32_TIM_CCMR1_OC2PE (1U << 11)
	193
	194	#define WB32_TIM_CCMR1_OC2M_MASK ((7U << 12) \| (1U << 24))
	195	#define WB32_TIM_CCMR1_OC2M(n) ((((n) & 7) << 12) \| \
	196	(((n) >> 3) << 24))
	197
	198	#define WB32_TIM_CCMR1_OC2CE (1U << 15)
	199	/** @} */
	200
	201	/**
	202	* @name CCMR1 register (input)
	203	* @{
	204	*/
	205	#define WB32_TIM_CCMR1_IC1PSC_MASK (3U << 2)
	206	#define WB32_TIM_CCMR1_IC1PSC(n) ((n) << 2)
	207
	208	#define WB32_TIM_CCMR1_IC1F_MASK (15U << 4)
	209	#define WB32_TIM_CCMR1_IC1F(n) ((n) << 4)
	210
	211	#define WB32_TIM_CCMR1_IC2PSC_MASK (3U << 10)
	212	#define WB32_TIM_CCMR1_IC2PSC(n) ((n) << 10)
	213
	214	#define WB32_TIM_CCMR1_IC2F_MASK (15U << 12)
	215	#define WB32_TIM_CCMR1_IC2F(n) ((n) << 12)
	216	/** @} */
	217
	218	/**
	219	* @name TIM_CCMR2 register (output)
	220	* @{
	221	*/
	222	#define WB32_TIM_CCMR2_CC3S_MASK (3U << 0)
	223	#define WB32_TIM_CCMR2_CC3S(n) ((n) << 0)
	224
	225	#define WB32_TIM_CCMR2_OC3FE (1U << 2)
	226	#define WB32_TIM_CCMR2_OC3PE (1U << 3)
	227
	228	#define WB32_TIM_CCMR2_OC3M_MASK ((7U << 4) \| (1U << 16))
	229	#define WB32_TIM_CCMR2_OC3M(n) ((((n) & 7) << 4) \| \
	230	(((n) >> 3) << 16))
	231
	232	#define WB32_TIM_CCMR2_OC3CE (1U << 7)
	233
	234	#define WB32_TIM_CCMR2_CC4S_MASK (3U << 8)
	235	#define WB32_TIM_CCMR2_CC4S(n) ((n) << 8)
	236
	237	#define WB32_TIM_CCMR2_OC4FE (1U << 10)
	238	#define WB32_TIM_CCMR2_OC4PE (1U << 11)
	239
	240	#define WB32_TIM_CCMR2_OC4M_MASK ((7U << 12) \| (1U << 24))
	241	#define WB32_TIM_CCMR2_OC4M(n) ((((n) & 7) << 12) \| \
	242	(((n) >> 3) << 24))
	243
	244	#define WB32_TIM_CCMR2_OC4CE (1U << 15)
	245	/** @} */
	246
	247	/**
	248	* @name TIM_CCMR2 register (input)
	249	* @{
	250	*/
	251	#define WB32_TIM_CCMR2_IC3PSC_MASK (3U << 2)
	252	#define WB32_TIM_CCMR2_IC3PSC(n) ((n) << 2)
	253
	254	#define WB32_TIM_CCMR2_IC3F_MASK (15U << 4)
	255	#define WB32_TIM_CCMR2_IC3F(n) ((n) << 4)
	256
	257	#define WB32_TIM_CCMR2_IC4PSC_MASK (3U << 10)
	258	#define WB32_TIM_CCMR2_IC4PSC(n) ((n) << 10)
	259
	260	#define WB32_TIM_CCMR2_IC4F_MASK (15U << 12)
	261	#define WB32_TIM_CCMR2_IC4F(n) ((n) << 12)
	262	/** @} */
	263
	264	/**
	265	* @name TIM_CCER register
	266	* @{
	267	*/
	268	#define WB32_TIM_CCER_CC1E (1U << 0)
	269	#define WB32_TIM_CCER_CC1P (1U << 1)
	270	#define WB32_TIM_CCER_CC1NE (1U << 2)
	271	#define WB32_TIM_CCER_CC1NP (1U << 3)
	272	#define WB32_TIM_CCER_CC2E (1U << 4)
	273	#define WB32_TIM_CCER_CC2P (1U << 5)
	274	#define WB32_TIM_CCER_CC2NE (1U << 6)
	275	#define WB32_TIM_CCER_CC2NP (1U << 7)
	276	#define WB32_TIM_CCER_CC3E (1U << 8)
	277	#define WB32_TIM_CCER_CC3P (1U << 9)
	278	#define WB32_TIM_CCER_CC3NE (1U << 10)
	279	#define WB32_TIM_CCER_CC3NP (1U << 11)
	280	#define WB32_TIM_CCER_CC4E (1U << 12)
	281	#define WB32_TIM_CCER_CC4P (1U << 13)
	282	#define WB32_TIM_CCER_CC4NE (1U << 14)
	283	#define WB32_TIM_CCER_CC4NP (1U << 15)
	284	#define WB32_TIM_CCER_CC5E (1U << 16)
	285	#define WB32_TIM_CCER_CC5P (1U << 17)
	286	#define WB32_TIM_CCER_CC6E (1U << 20)
	287	#define WB32_TIM_CCER_CC6P (1U << 21)
	288	/** @} */
	289
	290	/**
	291	* @name TIM_CNT register
	292	* @{
	293	*/
	294	#define WB32_TIM_CNT_UIFCPY (1U << 31)
	295	/** @} */
	296
	297	/**
	298	* @name TIM_BDTR register
	299	* @{
	300	*/
	301	#define WB32_TIM_BDTR_DTG_MASK (255U << 0)
	302	#define WB32_TIM_BDTR_DTG(n) ((n) << 0)
	303
	304	#define WB32_TIM_BDTR_LOCK_MASK (3U << 8)
	305	#define WB32_TIM_BDTR_LOCK(n) ((n) << 8)
	306
	307	#define WB32_TIM_BDTR_OSSI (1U << 10)
	308	#define WB32_TIM_BDTR_OSSR (1U << 11)
	309	#define WB32_TIM_BDTR_BKE (1U << 12)
	310	#define WB32_TIM_BDTR_BKP (1U << 13)
	311	#define WB32_TIM_BDTR_AOE (1U << 14)
	312	#define WB32_TIM_BDTR_MOE (1U << 15)
	313
	314	#define WB32_TIM_BDTR_BKF_MASK (15U << 16)
	315	#define WB32_TIM_BDTR_BKF(n) ((n) << 16)
	316	#define WB32_TIM_BDTR_BK2F_MASK (15U << 20)
	317	#define WB32_TIM_BDTR_BK2F(n) ((n) << 20)
	318
	319	#define WB32_TIM_BDTR_BK2E (1U << 24)
	320	#define WB32_TIM_BDTR_BK2P (1U << 25)
	321	/** @} */
	322
	323	/**
	324	* @name TIM_DCR register
	325	* @{
	326	*/
	327	#define WB32_TIM_DCR_DBA_MASK (31U << 0)
	328	#define WB32_TIM_DCR_DBA(n) ((n) << 0)
	329
	330	#define WB32_TIM_DCR_DBL_MASK (31U << 8)
	331	#define WB32_TIM_DCR_DBL(n) ((n) << 8)
	332	/** @} */
	333
	334	/**
	335	* @name TIM16_OR register
	336	* @{
	337	*/
	338	#define WB32_TIM16_OR_TI1_RMP_MASK (3U << 6)
	339	#define WB32_TIM16_OR_TI1_RMP(n) ((n) << 6)
	340	/** @} */
	341
	342	/**
	343	* @name TIM_OR register
	344	* @{
	345	*/
	346	#define WB32_TIM_OR_ETR_RMP_MASK (15U << 0)
	347	#define WB32_TIM_OR_ETR_RMP(n) ((n) << 0)
	348	/** @} */
	349
	350	/**
	351	* @name TIM_CCMR3 register
	352	* @{
	353	*/
	354	#define WB32_TIM_CCMR3_OC5FE (1U << 2)
	355	#define WB32_TIM_CCMR3_OC5PE (1U << 3)
	356
	357	#define WB32_TIM_CCMR3_OC5M_MASK ((7U << 4) \| (1U << 16))
	358	#define WB32_TIM_CCMR3_OC5M(n) ((((n) & 7) << 4) \| \
	359	(((n) >> 2) << 16))
	360
	361	#define WB32_TIM_CCMR3_OC5CE (1U << 7)
	362
	363	#define WB32_TIM_CCMR3_OC6FE (1U << 10)
	364	#define WB32_TIM_CCMR3_OC6PE (1U << 11)
	365
	366	#define WB32_TIM_CCMR3_OC6M_MASK ((7U << 12) \| (1U << 24))
	367	#define WB32_TIM_CCMR3_OC6M(n) ((((n) & 7) << 12) \| \
	368	(((n) >> 2) << 24))
	369
	370	#define WB32_TIM_CCMR3_OC6CE (1U << 15)
	371	/** @} */
	372
	373	/**
	374	* @name LPTIM_ISR register
	375	* @{
	376	*/
	377	#define WB32_LPTIM_ISR_CMPM (1U << 0)
	378	#define WB32_LPTIM_ISR_ARRM (1U << 1)
	379	#define WB32_LPTIM_ISR_EXTTRIG (1U << 2)
	380	#define WB32_LPTIM_ISR_CMPOK (1U << 3)
	381	#define WB32_LPTIM_ISR_ARROK (1U << 4)
	382	#define WB32_LPTIM_ISR_UP (1U << 5)
	383	#define WB32_LPTIM_ISR_DOWN (1U << 6)
	384	/** @} */
	385
	386	/**
	387	* @name LPTIM_ICR register
	388	* @{
	389	*/
	390	#define WB32_LPTIM_ICR_CMPMCF (1U << 0)
	391	#define WB32_LPTIM_ICR_ARRMCF (1U << 1)
	392	#define WB32_LPTIM_ICR_EXTTRIGCF (1U << 2)
	393	#define WB32_LPTIM_ICR_CMPOKCF (1U << 3)
	394	#define WB32_LPTIM_ICR_ARROKCF (1U << 4)
	395	#define WB32_LPTIM_ICR_UPCF (1U << 5)
	396	#define WB32_LPTIM_ICR_DOWNCF (1U << 6)
	397	/** @} */
	398
	399	/**
	400	* @name LPTIM_IER register
	401	* @{
	402	*/
	403	#define WB32_LPTIM_IER_CMPMIE (1U << 0)
	404	#define WB32_LPTIM_IER_ARRMIE (1U << 1)
	405	#define WB32_LPTIM_IER_EXTTRIGIE (1U << 2)
	406	#define WB32_LPTIM_IER_CMPOKIE (1U << 3)
	407	#define WB32_LPTIM_IER_ARROKIE (1U << 4)
	408	#define WB32_LPTIM_IER_UPIE (1U << 5)
	409	#define WB32_LPTIM_IER_DOWNIE (1U << 6)
	410	/** @} */
	411
	412	/**
	413	* @name LPTIM_CFGR register
	414	* @{
	415	*/
	416	#define WB32_LPTIM_CFGR_CKSEL (1U << 0)
	417	#define WB32_LPTIM_CFGR_CKPOL_MASK (3U << 1)
	418	#define WB32_LPTIM_CFGR_CKPOL(n) ((n) << 1)
	419	#define WB32_LPTIM_CFGR_CKFLT_MASK (3U << 3)
	420	#define WB32_LPTIM_CFGR_CKFLT(n) ((n) << 3)
	421	#define WB32_LPTIM_CFGR_TRGFLT_MASK (3U << 6)
	422	#define WB32_LPTIM_CFGR_TRGFLT(n) ((n) << 6)
	423	#define WB32_LPTIM_CFGR_PRESC_MASK (7U << 9)
	424	#define WB32_LPTIM_CFGR_PRESC(n) ((n) << 9)
	425	#define WB32_LPTIM_CFGR_TRIGSEL_MASK (7U << 13)
	426	#define WB32_LPTIM_CFGR_TRIGSEL(n) ((n) << 13)
	427	#define WB32_LPTIM_CFGR_TRIGEN_MASK (3U << 17)
	428	#define WB32_LPTIM_CFGR_TRIGEN(n) ((n) << 17)
	429	#define WB32_LPTIM_CFGR_TIMOUT (1U << 19)
	430	#define WB32_LPTIM_CFGR_WAVE (1U << 20)
	431	#define WB32_LPTIM_CFGR_WAVPOL (1U << 21)
	432	#define WB32_LPTIM_CFGR_PRELOAD (1U << 22)
	433	#define WB32_LPTIM_CFGR_COUNTMODE (1U << 23)
	434	#define WB32_LPTIM_CFGR_ENC (1U << 24)
	435	/** @} */
	436
	437	/**
	438	* @name LPTIM_CR register
	439	* @{
	440	*/
	441	#define WB32_LPTIM_CR_ENABLE (1U << 0)
	442	#define WB32_LPTIM_CR_SNGSTRT (1U << 1)
	443	#define WB32_LPTIM_CR_CNTSTRT (1U << 2)
	444	/** @} */
	445
	446	/**
	447	* @name LPTIM_OR register
	448	* @{
	449	*/
	450	#define WB32_LPTIM_OR_0 (1U << 0)
	451	#define WB32_LPTIM_OR_1 (1U << 1)
	452	/** @} */
	453
	454	/**
	455	* @name TIM units references
	456	* @{
	457	*/
	458	#define WB32_TIM1 ((wb32_tim_t *)TIM1_BASE)
	459	#define WB32_TIM2 ((wb32_tim_t *)TIM2_BASE)
	460	#define WB32_TIM3 ((wb32_tim_t *)TIM3_BASE)
	461	#define WB32_TIM4 ((wb32_tim_t *)TIM4_BASE)
	462
	463	#define WB32_LPTIM1 ((wb32_lptim_t *)LPTIM1_BASE)
	464	#define WB32_LPTIM2 ((wb32_lptim_t *)LPTIM2_BASE)
	465	/** @} */
	466
	467	/===========================================================================/
	468	/* Driver pre-compile time settings. */
	469	/===========================================================================/
	470
	471	/===========================================================================/
	472	/* Derived constants and error checks. */
	473	/===========================================================================/
	474
	475	/===========================================================================/
	476	/* Driver data structures and types. */
	477	/===========================================================================/
	478
	479	/**
	480	* @brief WB32 TIM registers block.
	481	* @note This is the most general known form, not all timers have
	482	* necessarily all registers and bits.
	483	*/
	484	typedef struct {
	485	volatile uint32_t CR1;
	486	volatile uint32_t CR2;
	487	volatile uint32_t SMCR;
	488	volatile uint32_t DIER;
	489	volatile uint32_t SR;
	490	volatile uint32_t EGR;
	491	volatile uint32_t CCMR1;
	492	volatile uint32_t CCMR2;
	493	volatile uint32_t CCER;
	494	volatile uint32_t CNT;
	495	volatile uint32_t PSC;
	496	volatile uint32_t ARR;
	497	volatile uint32_t RCR;
	498	volatile uint32_t CCR[4];
	499	volatile uint32_t BDTR;
	500	volatile uint32_t DCR;
	501	volatile uint32_t DMAR;
	502	volatile uint32_t OR;
	503	volatile uint32_t CCMR3;
	504	volatile uint32_t CCXR[2];
	505	} wb32_tim_t;
	506
	507	/**
	508	* @brief WB32 LPTIM registers block.
	509	* @note This is the most general known form, not all timers have
	510	* necessarily all registers and bits.
	511	*/
	512	typedef struct {
	513	volatile uint32_t ISR;
	514	volatile uint32_t ICR;
	515	volatile uint32_t IER;
	516	volatile uint32_t CFGR;
	517	volatile uint32_t CR;
	518	volatile uint32_t CMP;
	519	volatile uint32_t ARR;
	520	volatile uint32_t CNT;
	521	volatile uint32_t OR;
	522	} wb32_lptim_t;
	523
	524	/===========================================================================/
	525	/* Driver macros. */
	526	/===========================================================================/
	527
	528	/===========================================================================/
	529	/* External declarations. */
	530	/===========================================================================/
	531
	532	#endif /* WB32_TIM_H */
	533
	534	/** @} */