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1/****************************************************************************************************//**
2 * @file LPC11Uxx.h
3 *
4 *
5 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File for
6 * default LPC11Uxx Device Series
7 *
8 * @version V0.1
9 * @date 21. March 2011
10 *
11 * @note Generated with SFDGen V2.6 Build 3j (beta) on Thursday, 17.03.2011 13:19:45
12 *
13 * from CMSIS SVD File 'LPC11U1x_svd.xml' Version 0.1,
14 * created on Wednesday, 16.03.2011 20:30:42, last modified on Thursday, 17.03.2011 20:19:40
15 *
16 *******************************************************************************************************/
17
18/** @addtogroup NXP
19 * @{
20 */
21
22/** @addtogroup LPC11Uxx
23 * @{
24 */
25
26#ifndef __LPC11UXX_H__
27#define __LPC11UXX_H__
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33
34#if defined ( __CC_ARM )
35 #pragma anon_unions
36#endif
37
38 /* Interrupt Number Definition */
39
40typedef enum {
41// ------------------------- Cortex-M0 Processor Exceptions Numbers -----------------------------
42 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
43 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
44 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
45 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
46 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
47 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
48 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
49// --------------------------- LPC11Uxx Specific Interrupt Numbers ------------------------------
50 FLEX_INT0_IRQn = 0, /*!< All I/O pins can be routed to below 8 interrupts. */
51 FLEX_INT1_IRQn = 1,
52 FLEX_INT2_IRQn = 2,
53 FLEX_INT3_IRQn = 3,
54 FLEX_INT4_IRQn = 4,
55 FLEX_INT5_IRQn = 5,
56 FLEX_INT6_IRQn = 6,
57 FLEX_INT7_IRQn = 7,
58 GINT0_IRQn = 8, /*!< Grouped Interrupt 0 */
59 GINT1_IRQn = 9, /*!< Grouped Interrupt 1 */
60 Reserved0_IRQn = 10, /*!< Reserved Interrupt */
61 Reserved1_IRQn = 11,
62 Reserved2_IRQn = 12,
63 Reserved3_IRQn = 13,
64 SSP1_IRQn = 14, /*!< SSP1 Interrupt */
65 I2C_IRQn = 15, /*!< I2C Interrupt */
66 TIMER_16_0_IRQn = 16, /*!< 16-bit Timer0 Interrupt */
67 TIMER_16_1_IRQn = 17, /*!< 16-bit Timer1 Interrupt */
68 TIMER_32_0_IRQn = 18, /*!< 32-bit Timer0 Interrupt */
69 TIMER_32_1_IRQn = 19, /*!< 32-bit Timer1 Interrupt */
70 SSP0_IRQn = 20, /*!< SSP0 Interrupt */
71 UART_IRQn = 21, /*!< UART Interrupt */
72 USB_IRQn = 22, /*!< USB IRQ Interrupt */
73 USB_FIQn = 23, /*!< USB FIQ Interrupt */
74 ADC_IRQn = 24, /*!< A/D Converter Interrupt */
75 WDT_IRQn = 25, /*!< Watchdog timer Interrupt */
76 BOD_IRQn = 26, /*!< Brown Out Detect(BOD) Interrupt */
77 FMC_IRQn = 27, /*!< Flash Memory Controller Interrupt */
78 Reserved4_IRQn = 28, /*!< Reserved Interrupt */
79 Reserved5_IRQn = 29, /*!< Reserved Interrupt */
80 USBWakeup_IRQn = 30, /*!< USB wakeup Interrupt */
81 Reserved6_IRQn = 31, /*!< Reserved Interrupt */
82} IRQn_Type;
83
84
85/** @addtogroup Configuration_of_CMSIS
86 * @{
87 */
88
89/* Processor and Core Peripheral Section */ /* Configuration of the Cortex-M0 Processor and Core Peripherals */
90
91#define __MPU_PRESENT 0 /*!< MPU present or not */
92#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
93#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
94/** @} */ /* End of group Configuration_of_CMSIS */
95
96#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
97
98/** @addtogroup Device_Peripheral_Registers
99 * @{
100 */
101
102
103// ------------------------------------------------------------------------------------------------
104// ----- I2C -----
105// ------------------------------------------------------------------------------------------------
106
107
108/**
109 * @brief Product name title=UM10462 Chapter title=LPC11U1x I2C-bus controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (I2C)
110 */
111
112typedef struct { /*!< (@ 0x40000000) I2C Structure */
113 __IO uint32_t CONSET; /*!< (@ 0x40000000) I2C Control Set Register */
114 __I uint32_t STAT; /*!< (@ 0x40000004) I2C Status Register */
115 __IO uint32_t DAT; /*!< (@ 0x40000008) I2C Data Register. */
116 __IO uint32_t ADR0; /*!< (@ 0x4000000C) I2C Slave Address Register 0 */
117 __IO uint32_t SCLH; /*!< (@ 0x40000010) SCH Duty Cycle Register High Half Word */
118 __IO uint32_t SCLL; /*!< (@ 0x40000014) SCL Duty Cycle Register Low Half Word */
119 __IO uint32_t CONCLR; /*!< (@ 0x40000018) I2C Control Clear Register*/
120 __IO uint32_t MMCTRL; /*!< (@ 0x4000001C) Monitor mode control register*/
121 __IO uint32_t ADR1; /*!< (@ 0x40000020) I2C Slave Address Register 1*/
122 __IO uint32_t ADR2; /*!< (@ 0x40000024) I2C Slave Address Register 2*/
123 __IO uint32_t ADR3; /*!< (@ 0x40000028) I2C Slave Address Register 3*/
124 __I uint32_t DATA_BUFFER; /*!< (@ 0x4000002C) Data buffer register */
125union{
126 __IO uint32_t MASK[4]; /*!< (@ 0x40000030) I2C Slave address mask register */
127 struct{
128 __IO uint32_t MASK0;
129 __IO uint32_t MASK1;
130 __IO uint32_t MASK2;
131 __IO uint32_t MASK3;
132 };
133 };
134} LPC_I2C_Type;
135
136
137// ------------------------------------------------------------------------------------------------
138// ----- WWDT -----
139// ------------------------------------------------------------------------------------------------
140
141
142/**
143 * @brief Product name title=UM10462 Chapter title=LPC11U1x Windowed Watchdog Timer (WWDT) Modification date=3/16/2011 Major revision=0 Minor revision=3 (WWDT)
144 */
145
146typedef struct { /*!< (@ 0x40004000) WWDT Structure */
147 __IO uint32_t MOD; /*!< (@ 0x40004000) Watchdog mode register*/
148 __IO uint32_t TC; /*!< (@ 0x40004004) Watchdog timer constant register */
149 __IO uint32_t FEED; /*!< (@ 0x40004008) Watchdog feed sequence register */
150 __I uint32_t TV; /*!< (@ 0x4000400C) Watchdog timer value register */
151 __IO uint32_t CLKSEL; /*!< (@ 0x40004010) Watchdog clock select register. */
152 __IO uint32_t WARNINT; /*!< (@ 0x40004014) Watchdog Warning Interrupt compare value. */
153 __IO uint32_t WINDOW; /*!< (@ 0x40004018) Watchdog Window compare value. */
154} LPC_WWDT_Type;
155
156
157// ------------------------------------------------------------------------------------------------
158// ----- USART -----
159// ------------------------------------------------------------------------------------------------
160
161
162/**
163 * @brief Product name title=UM10462 Chapter title=LPC11U1x USART Modification date=3/16/2011 Major revision=0 Minor revision=3 (USART)
164 */
165
166typedef struct { /*!< (@ 0x40008000) USART Structure */
167
168 union {
169 __IO uint32_t DLL; /*!< (@ 0x40008000) Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
170 __O uint32_t THR; /*!< (@ 0x40008000) Transmit Holding Register. The next character to be transmitted is written here. (DLAB=0) */
171 __I uint32_t RBR; /*!< (@ 0x40008000) Receiver Buffer Register. Contains the next received character to be read. (DLAB=0) */
172 };
173
174 union {
175 __IO uint32_t IER; /*!< (@ 0x40008004) Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential USART interrupts. (DLAB=0) */
176 __IO uint32_t DLM; /*!< (@ 0x40008004) Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider. (DLAB=1) */
177 };
178
179 union {
180 __O uint32_t FCR; /*!< (@ 0x40008008) FIFO Control Register. Controls USART FIFO usage and modes. */
181 __I uint32_t IIR; /*!< (@ 0x40008008) Interrupt ID Register. Identifies which interrupt(s) are pending. */
182 };
183 __IO uint32_t LCR; /*!< (@ 0x4000800C) Line Control Register. Contains controls for frame formatting and break generation. */
184 __IO uint32_t MCR; /*!< (@ 0x40008010) Modem Control Register. */
185 __I uint32_t LSR; /*!< (@ 0x40008014) Line Status Register. Contains flags for transmit and receive status, including line errors. */
186 __I uint32_t MSR; /*!< (@ 0x40008018) Modem Status Register. */
187 __IO uint32_t SCR; /*!< (@ 0x4000801C) Scratch Pad Register. Eight-bit temporary storage for software. */
188 __IO uint32_t ACR; /*!< (@ 0x40008020) Auto-baud Control Register. Contains controls for the auto-baud feature. */
189 __IO uint32_t ICR; /*!< (@ 0x40008024) IrDA Control Register. Enables and configures the IrDA (remote control) mode. */
190 __IO uint32_t FDR; /*!< (@ 0x40008028) Fractional Divider Register. Generates a clock input for the baud rate divider. */
191 __IO uint32_t OSR; /*!< (@ 0x4000802C) Oversampling Register. Controls the degree of oversampling during each bit time. */
192 __IO uint32_t TER; /*!< (@ 0x40008030) Transmit Enable Register. Turns off USART transmitter for use with software flow control. */
193 __I uint32_t RESERVED0[3];
194 __IO uint32_t HDEN; /*!< (@ 0x40008040) Half duplex enable register. */
195 __I uint32_t RESERVED1;
196 __IO uint32_t SCICTRL; /*!< (@ 0x40008048) Smart Card Interface Control register. Enables and configures the Smart Card Interface feature. */
197 __IO uint32_t RS485CTRL; /*!< (@ 0x4000804C) RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes. */
198 __IO uint32_t RS485ADRMATCH; /*!< (@ 0x40008050) RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode. */
199 __IO uint32_t RS485DLY; /*!< (@ 0x40008054) RS-485/EIA-485 direction control delay. */
200 __IO uint32_t SYNCCTRL;
201} LPC_USART_Type;
202
203#define USART_FCR_FIFOEN (1U << 0U)
204#define USART_FCR_RX_RST (1U << 1U)
205#define USART_FCR_TX_RST (1U << 2U)
206#define USART_FCR_RXTL_POS (6U)
207#define USART_FCR_RXTL_1B (0x0 << USART_FCR_RXTL_POS)
208#define USART_FCR_RXTL_4B (0x1 << USART_FCR_RXTL_POS)
209#define USART_FCR_RXTL_8B (0x2 << USART_FCR_RXTL_POS)
210#define USART_FCR_RXTL_14B (0x3 << USART_FCR_RXTL_POS)
211#define USART_FCR_RXTL_MASK (0x3 << USART_FCR_RXTL_POS)
212
213#define USART_LCR_WLS_POS (0U)
214#define USART_LCR_WLS_5B (0x0U << USART_LCR_WLS_POS)
215#define USART_LCR_WLS_6B (0x1U << USART_LCR_WLS_POS)
216#define USART_LCR_WLS_7B (0x2U << USART_LCR_WLS_POS)
217#define USART_LCR_WLS_8B (0x3U << USART_LCR_WLS_POS)
218#define USART_LCR_WLS_MASK (0x3U << USART_LCR_WLS_POS)
219#define USART_LCR_SBS_POS (2U)
220#define USART_LCR_SBS_1B (0U << USART_LCR_SBS_POS)
221#define USART_LCR_SBS_2B (0U << USART_LCR_SBS_POS)
222#define USART_LCR_SBS_MASK (0x1 << USART_LCR_SBS_POS)
223#define USART_LCR_PE (1U << 3U)
224#define USART_LCR_PS_POS (4U)
225#define USART_LCR_PS_ODD (0x0U << USART_LCR_PS_POS)
226#define USART_LCR_PS_EVEN (0x1U << USART_LCR_PS_POS)
227#define USART_LCR_PS_F1 (0x2U << USART_LCR_PS_POS)
228#define USART_LCR_PS_F0 (0x3U << USART_LCR_PS_POS)
229#define USART_LCR_PS_MASK (0x3U << USART_LCR_PS_POS)
230#define USART_LCR_DLAB (1U << 7U)
231
232#define USART_LSR_RDR (1U << 0U)
233#define USART_LSR_THRE (1U << 5U)
234
235#define USART_TER_TXEN (1U << 7U)
236
237#define USART_IER_RBRINTEN (1U << 0U) // Rx Has Data
238#define USART_IER_THRINTEN (1U << 1U) // Tx Empty
239
240// ------------------------------------------------------------------------------------------------
241// ----- Timer -----
242// ------------------------------------------------------------------------------------------------
243
244
245/**
246 * @brief Product name title=UM10462 Chapter title=LPC11U1x 32-bitcounter/timers CT32B0/1 Modification date=3/16/2011 Major revision=0 Minor revision=3
247 */
248
249typedef struct { /*!< (@ 0x40014000) CT32B0 Structure */
250 __IO uint32_t IR; /*!< (@ 0x40014000) Interrupt Register */
251 __IO uint32_t TCR; /*!< (@ 0x40014004) Timer Control Register */
252 __IO uint32_t TC; /*!< (@ 0x40014008) Timer Counter */
253 __IO uint32_t PR; /*!< (@ 0x4001400C) Prescale Register */
254 __IO uint32_t PC; /*!< (@ 0x40014010) Prescale Counter */
255 __IO uint32_t MCR; /*!< (@ 0x40014014) Match Control Register */
256 union {
257 __IO uint32_t MR[4]; /*!< (@ 0x40014018) Match Register */
258 struct{
259 __IO uint32_t MR0; /*!< (@ 0x40018018) Match Register. MR0 */
260 __IO uint32_t MR1; /*!< (@ 0x4001801C) Match Register. MR1 */
261 __IO uint32_t MR2; /*!< (@ 0x40018020) Match Register. MR2 */
262 __IO uint32_t MR3; /*!< (@ 0x40018024) Match Register. MR3 */
263 };
264 };
265 __IO uint32_t CCR; /*!< (@ 0x40014028) Capture Control Register */
266 union{
267 __I uint32_t CR[4]; /*!< (@ 0x4001402C) Capture Register */
268 struct{
269 __I uint32_t CR0; /*!< (@ 0x4001802C) Capture Register. CR 0 */
270 __I uint32_t CR1; /*!< (@ 0x40018030) Capture Register. CR 1 */
271 __I uint32_t CR2; /*!< (@ 0x40018034) Capture Register. CR 2 */
272 __I uint32_t CR3; /*!< (@ 0x40018038) Capture Register. CR 3 */
273 };
274 };
275__IO uint32_t EMR; /*!< (@ 0x4001403C) External Match Register */
276 __I uint32_t RESERVED0[12];
277 __IO uint32_t CTCR; /*!< (@ 0x40014070) Count Control Register */
278 __IO uint32_t PWMC; /*!< (@ 0x40014074) PWM Control Register */
279} LPC_CTxxBx_Type;
280
281
282
283// ------------------------------------------------------------------------------------------------
284// ----- ADC -----
285// ------------------------------------------------------------------------------------------------
286
287
288/**
289 * @brief Product name title=UM10462 Chapter title=LPC11U1x ADC Modification date=3/16/2011 Major revision=0 Minor revision=3 (ADC)
290 */
291
292typedef struct { /*!< (@ 0x4001C000) ADC Structure */
293 __IO uint32_t CR; /*!< (@ 0x4001C000) A/D Control Register */
294 __IO uint32_t GDR; /*!< (@ 0x4001C004) A/D Global Data Register */
295 __I uint32_t RESERVED0[1];
296 __IO uint32_t INTEN; /*!< (@ 0x4001C00C) A/D Interrupt Enable Register */
297 union{
298 __I uint32_t DR[8]; /*!< (@ 0x4001C010) A/D Channel Data Register*/
299 struct{
300 __IO uint32_t DR0; /*!< (@ 0x40020010) A/D Channel Data Register 0*/
301 __IO uint32_t DR1; /*!< (@ 0x40020014) A/D Channel Data Register 1*/
302 __IO uint32_t DR2; /*!< (@ 0x40020018) A/D Channel Data Register 2*/
303 __IO uint32_t DR3; /*!< (@ 0x4002001C) A/D Channel Data Register 3*/
304 __IO uint32_t DR4; /*!< (@ 0x40020020) A/D Channel Data Register 4*/
305 __IO uint32_t DR5; /*!< (@ 0x40020024) A/D Channel Data Register 5*/
306 __IO uint32_t DR6; /*!< (@ 0x40020028) A/D Channel Data Register 6*/
307 __IO uint32_t DR7; /*!< (@ 0x4002002C) A/D Channel Data Register 7*/
308 };
309 };
310 __I uint32_t STAT; /*!< (@ 0x4001C030) A/D Status Register. */
311} LPC_ADC_Type;
312
313
314// ------------------------------------------------------------------------------------------------
315// ----- PMU -----
316// ------------------------------------------------------------------------------------------------
317
318
319/**
320 * @brief Product name title=UM10462 Chapter title=LPC11U1x Power Management Unit (PMU) Modification date=3/16/2011 Major revision=0 Minor revision=3 (PMU)
321 */
322
323typedef struct { /*!< (@ 0x40038000) PMU Structure */
324 __IO uint32_t PCON; /*!< (@ 0x40038000) Power control register */
325 union{
326 __IO uint32_t GPREG[4]; /*!< (@ 0x40038004) General purpose register 0 */
327 struct{
328 __IO uint32_t GPREG0; /*!< (@ 0x40038004) General purpose register 0 */
329 __IO uint32_t GPREG1; /*!< (@ 0x40038008) General purpose register 1 */
330 __IO uint32_t GPREG2; /*!< (@ 0x4003800C) General purpose register 2 */
331 __IO uint32_t GPREG3; /*!< (@ 0x40038010) General purpose register 3 */
332 };
333 };
334} LPC_PMU_Type;
335
336
337// ------------------------------------------------------------------------------------------------
338// ----- FLASHCTRL -----
339// ------------------------------------------------------------------------------------------------
340
341
342/**
343 * @brief Product name title=UM10462 Chapter title=LPC11U1x Flash programming firmware Modification date=3/17/2011 Major revision=0 Minor revision=3 (FLASHCTRL)
344 */
345
346typedef struct { /*!< (@ 0x4003C000) FLASHCTRL Structure */
347 __I uint32_t RESERVED0[4];
348 __IO uint32_t FLASHCFG; /*!< (@ 0x4003C010) Flash memory access time configuration register */
349 __I uint32_t RESERVED1[3];
350 __IO uint32_t FMSSTART; /*!< (@ 0x4003C020) Signature start address register */
351 __IO uint32_t FMSSTOP; /*!< (@ 0x4003C024) Signature stop-address register */
352 __I uint32_t RESERVED2[1];
353 __I uint32_t FMSW0; /*!< (@ 0x4003C02C) Word 0 [31:0] */
354 __I uint32_t FMSW1; /*!< (@ 0x4003C030) Word 1 [63:32] */
355 __I uint32_t FMSW2; /*!< (@ 0x4003C034) Word 2 [95:64] */
356 __I uint32_t FMSW3; /*!< (@ 0x4003C038) Word 3 [127:96] */
357 __I uint32_t RESERVED3[1001];
358 __I uint32_t FMSTAT; /*!< (@ 0x4003CFE0) Signature generation status register */
359 __I uint32_t RESERVED4[1];
360 __IO uint32_t FMSTATCLR; /*!< (@ 0x4003CFE8) Signature generation status clear register */
361} LPC_FLASHCTRL_Type;
362
363
364// ------------------------------------------------------------------------------------------------
365// ----- SSP0/1 -----
366// ------------------------------------------------------------------------------------------------
367
368
369/**
370 * @brief Product name title=UM10462 Chapter title=LPC11U1x SSP/SPI Modification date=3/16/2011 Major revision=0 Minor revision=3 (SSP0)
371 */
372
373typedef struct { /*!< (@ 0x40040000) SSP0 Structure */
374 __IO uint32_t CR0; /*!< (@ 0x40040000) Control Register 0. Selects the serial clock rate, bus type, and data size. */
375 __IO uint32_t CR1; /*!< (@ 0x40040004) Control Register 1. Selects master/slave and other modes. */
376 __IO uint32_t DR; /*!< (@ 0x40040008) Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO. */
377 __I uint32_t SR; /*!< (@ 0x4004000C) Status Register */
378 __IO uint32_t CPSR; /*!< (@ 0x40040010) Clock Prescale Register */
379 __IO uint32_t IMSC; /*!< (@ 0x40040014) Interrupt Mask Set and Clear Register */
380 __I uint32_t RIS; /*!< (@ 0x40040018) Raw Interrupt Status Register */
381 __I uint32_t MIS; /*!< (@ 0x4004001C) Masked Interrupt Status Register */
382 __IO uint32_t ICR; /*!< (@ 0x40040020) SSPICR Interrupt Clear Register */
383} LPC_SSPx_Type;
384
385
386#define SSP_CR0_DSS_POS (0U)
387#define SSP_CR0_DSS_MASK (0xF << SSP_CR0_DSS_POS)
388#define SSP_CR0_DSS(X) (((X) << SSP_CR0_DSS_POS) & SSP_CR0_DSS_MASK)
389#define SSP_CR0_FRF_POS (4U)
390#define SSP_CR0_FRF_MASK (0x3 << SSP_CR0_FRF_POS)
391#define SSP_CR0_SCR_POS (8U)
392#define SSP_CR0_SCR_MASK (0xFF << SSP_CR0_SCR_POS)
393#define SSP_CR0_SCR(X) (((X) << SSP_CR0_SCR_POS) & SSP_CR0_SCR_MASK)
394#define SSP_CR0_CPOL (1U << 6U)
395#define SSP_CR0_CPHA (1U << 7U)
396
397#define SSP_CR1_SPI_EN (1U << 1U)
398#define SSP_CR1_SLAVE (1U << 2U)
399#define SSP_CR1_SLAVE_OUTPUT_DISABLE (1U << 3U)
400
401#define SSP_SR_TxEmpty (1U << 0U) // Tx Empty
402#define SSP_SR_TxNotFull (1U << 1U)
403#define SSP_SR_RxNotEmpty (1U << 2U)
404#define SSP_SR_RxFull (1U << 3U)
405#define SSP_SR_BUSY (1U << 4U)
406
407#define SSP_INT_ROR (1U << 0U) // RxOverrun
408#define SSP_INT_RTMIS (1U << 1U) // Rx FIFO not Empty Timeout
409#define SSP_INT_RXMIS (1U << 2U) // Rx Half Full
410#define SSP_INT_TXMIS (1U << 3U) // Tx Half Empty
411// ------------------------------------------------------------------------------------------------
412// ----- IOCONFIG -----
413// ------------------------------------------------------------------------------------------------
414
415
416/**
417 * @brief Product name title=UM10462 Chapter title=LPC11U1x I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
418 */
419
420typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
421 __IO uint32_t RESET_PIO0_0; /*!< (@ 0x40044000) I/O configuration for pin RESET/PIO0_0 */
422 __IO uint32_t PIO0_1; /*!< (@ 0x40044004) I/O configuration for pin PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE */
423 __IO uint32_t PIO0_2; /*!< (@ 0x40044008) I/O configuration for pin PIO0_2/SSEL0/CT16B0_CAP0 */
424 __IO uint32_t PIO0_3; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_3/USB_VBUS */
425 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4/SCL */
426 __IO uint32_t PIO0_5; /*!< (@ 0x40044014) I/O configuration for pin PIO0_5/SDA */
427 __IO uint32_t PIO0_6; /*!< (@ 0x40044018) I/O configuration for pin PIO0_6/USB_CONNECT/SCK0 */
428 __IO uint32_t PIO0_7; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_7/CTS */
429 __IO uint32_t PIO0_8; /*!< (@ 0x40044020) I/O configuration for pin PIO0_8/MISO0/CT16B0_MAT0 */
430 __IO uint32_t PIO0_9; /*!< (@ 0x40044024) I/O configuration for pin PIO0_9/MOSI0/CT16B0_MAT1 */
431 __IO uint32_t SWCLK_PIO0_10; /*!< (@ 0x40044028) I/O configuration for pin SWCLK/PIO0_10/ SCK0/CT16B0_MAT2 */
432 __IO uint32_t TDI_PIO0_11; /*!< (@ 0x4004402C) I/O configuration for pin TDI/PIO0_11/AD0/CT32B0_MAT3 */
433 __IO uint32_t TMS_PIO0_12; /*!< (@ 0x40044030) I/O configuration for pin TMS/PIO0_12/AD1/CT32B1_CAP0 */
434 __IO uint32_t TDO_PIO0_13; /*!< (@ 0x40044034) I/O configuration for pin TDO/PIO0_13/AD2/CT32B1_MAT0 */
435 __IO uint32_t TRST_PIO0_14; /*!< (@ 0x40044038) I/O configuration for pin TRST/PIO0_14/AD3/CT32B1_MAT1 */
436 __IO uint32_t SWDIO_PIO0_15; /*!< (@ 0x4004403C) I/O configuration for pin SWDIO/PIO0_15/AD4/CT32B1_MAT2 */
437 __IO uint32_t PIO0_16; /*!< (@ 0x40044040) I/O configuration for pin PIO0_16/AD5/CT32B1_MAT3/ WAKEUP */
438 __IO uint32_t PIO0_17; /*!< (@ 0x40044044) I/O configuration for pin PIO0_17/RTS/CT32B0_CAP0/SCLK */
439 __IO uint32_t PIO0_18; /*!< (@ 0x40044048) I/O configuration for pin PIO0_18/RXD/CT32B0_MAT0 */
440 __IO uint32_t PIO0_19; /*!< (@ 0x4004404C) I/O configuration for pin PIO0_19/TXD/CT32B0_MAT1 */
441 __IO uint32_t PIO0_20; /*!< (@ 0x40044050) I/O configuration for pin PIO0_20/CT16B1_CAP0 */
442 __IO uint32_t PIO0_21; /*!< (@ 0x40044054) I/O configuration for pin PIO0_21/CT16B1_MAT0/MOSI1 */
443 __IO uint32_t PIO0_22; /*!< (@ 0x40044058) I/O configuration for pin PIO0_22/AD6/CT16B1_MAT1/MISO1 */
444 __IO uint32_t PIO0_23; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_23/AD7 */
445 __IO uint32_t PIO1_0; /*!< Offset: 0x060 */
446 __IO uint32_t PIO1_1;
447 __IO uint32_t PIO1_2;
448 __IO uint32_t PIO1_3;
449 __IO uint32_t PIO1_4; /*!< Offset: 0x070 */
450 __IO uint32_t PIO1_5; /*!< (@ 0x40044074) I/O configuration for pin PIO1_5/CT32B1_CAP1 */
451 __IO uint32_t PIO1_6;
452 __IO uint32_t PIO1_7;
453 __IO uint32_t PIO1_8; /*!< Offset: 0x080 */
454 __IO uint32_t PIO1_9;
455 __IO uint32_t PIO1_10;
456 __IO uint32_t PIO1_11;
457 __IO uint32_t PIO1_12; /*!< Offset: 0x090 */
458 __IO uint32_t PIO1_13; /*!< (@ 0x40044094) I/O configuration for pin PIO1_13/DTR/CT16B0_MAT0/TXD */
459 __IO uint32_t PIO1_14; /*!< (@ 0x40044098) I/O configuration for pin PIO1_14/DSR/CT16B0_MAT1/RXD */
460 __IO uint32_t PIO1_15; /*!< (@ 0x4004409C) I/O configuration for pin PIO1_15/DCD/ CT16B0_MAT2/SCK1 */
461 __IO uint32_t PIO1_16; /*!< (@ 0x400440A0) I/O configuration for pin PIO1_16/RI/CT16B0_CAP0 */
462 __IO uint32_t PIO1_17;
463 __IO uint32_t PIO1_18;
464 __IO uint32_t PIO1_19; /*!< (@ 0x400440AC) I/O configuration for pin PIO1_19/DTR/SSEL1 */
465 __IO uint32_t PIO1_20; /*!< (@ 0x400440B0) I/O configuration for pin PIO1_20/DSR/SCK1 */
466 __IO uint32_t PIO1_21; /*!< (@ 0x400440B4) I/O configuration for pin PIO1_21/DCD/MISO1 */
467 __IO uint32_t PIO1_22; /*!< (@ 0x400440B8) I/O configuration for pin PIO1_22/RI/MOSI1 */
468 __IO uint32_t PIO1_23; /*!< (@ 0x400440BC) I/O configuration for pin PIO1_23/CT16B1_MAT1/SSEL1 */
469 __IO uint32_t PIO1_24; /*!< (@ 0x400440C0) I/O configuration for pin PIO1_24/ CT32B0_MAT0 */
470 __IO uint32_t PIO1_25; /*!< (@ 0x400440C4) I/O configuration for pin PIO1_25/CT32B0_MAT1 */
471 __IO uint32_t PIO1_26; /*!< (@ 0x400440C8) I/O configuration for pin PIO1_26/CT32B0_MAT2/ RXD */
472 __IO uint32_t PIO1_27; /*!< (@ 0x400440CC) I/O configuration for pin PIO1_27/CT32B0_MAT3/ TXD */
473 __IO uint32_t PIO1_28; /*!< (@ 0x400440D0) I/O configuration for pin PIO1_28/CT32B0_CAP0/ SCLK */
474 __IO uint32_t PIO1_29; /*!< (@ 0x400440D4) I/O configuration for pin PIO1_29/SCK0/ CT32B0_CAP1 */
475 __IO uint32_t PIO1_30;
476 __IO uint32_t PIO1_31; /*!< (@ 0x400440DC) I/O configuration for pin PIO1_31 */
477} LPC_IOCON_Type;
478
479
480// ------------------------------------------------------------------------------------------------
481// ----- SYSCON -----
482// ------------------------------------------------------------------------------------------------
483
484
485/**
486 * @brief Product name title=UM10462 Chapter title=LPC11U1x System control block Modification date=3/16/2011 Major revision=0 Minor revision=3 (SYSCON)
487 */
488
489typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
490 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
491 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
492 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
493 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
494 __IO uint32_t USBPLLCTRL; /*!< (@ 0x40048010) USB PLL control */
495 __I uint32_t USBPLLSTAT; /*!< (@ 0x40048014) USB PLL status */
496 __I uint32_t RESERVED0[2];
497 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
498 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
499 __I uint32_t RESERVED1[2];
500 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
501 __I uint32_t RESERVED2[3];
502 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
503 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
504 __IO uint32_t USBPLLCLKSEL; /*!< (@ 0x40048048) USB PLL clock source select */
505 __IO uint32_t USBPLLCLKUEN; /*!< (@ 0x4004804C) USB PLL clock source update enable */
506 __I uint32_t RESERVED3[8];
507 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
508 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
509 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
510 __I uint32_t RESERVED4[1];
511 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
512 __I uint32_t RESERVED5[4];
513 __IO uint32_t SSP0CLKDIV; /*!< (@ 0x40048094) SSP0 clock divider */
514 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048098) UART clock divider */
515 __IO uint32_t SSP1CLKDIV; /*!< (@ 0x4004809C) SSP1 clock divider */
516 __I uint32_t RESERVED6[8];
517 __IO uint32_t USBCLKSEL; /*!< (@ 0x400480C0) USB clock source select */
518 __IO uint32_t USBCLKUEN; /*!< (@ 0x400480C4) USB clock source update enable */
519 __IO uint32_t USBCLKDIV; /*!< (@ 0x400480C8) USB clock source divider */
520 __I uint32_t RESERVED7[5];
521 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
522 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
523 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
524 __I uint32_t RESERVED8[5];
525 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
526 __I uint32_t PIOPORCAP1; /*!< (@ 0x40048104) POR captured PIO status 1 */
527 __I uint32_t RESERVED9[18];
528 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
529 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
530 __I uint32_t RESERVED10[6];
531 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay */
532 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
533 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
534 __IO uint32_t USBCLKCTRL; /*!< (@ 0x40048198) USB clock control */
535 __I uint32_t USBCLKST; /*!< (@ 0x4004819C) USB clock status */
536 __I uint32_t RESERVED11[25];
537 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 interrupt wake-up enable register 0 */
538 __I uint32_t RESERVED12[3];
539 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register 1 */
540 __I uint32_t RESERVED13[6];
541 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
542 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
543 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
544 __I uint32_t RESERVED14[110];
545 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F4) Device ID */
546} LPC_SYSCON_Type;
547
548#define SYSCON_PRESETCTRL_SSP0_RSTn (1U << 0U)
549#define SYSCON_PRESETCTRL_I2C_RSTn (1U << 1U)
550#define SYSCON_PRESETCTRL_SSP1_RSTn (1U << 2U)
551// SYSCON_SYSPLLCTRL
552#define SYSCON_SYSPLLCTRL_MSEL_POS (0U)
553#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1FU << SYSPLLCTRL_MSEL_POS)
554#define SYSCON_SYSPLLCTRL_PSEL_POS (5U)
555#define SYSCON_SYSPLLCTRL_PSEL_MASK (0x03U << SYSPLLCTRL_PSEL_POS)
556// SYSCON_SYSPLLSTAT
557#define SYSCON_SYSPLLSTAT_LOCK 0x1U
558// SYSCON_SYSPLLCLKSEL
559#define SYSCON_SYSPLLCLKSEL_IRC (0x00U << 0)
560#define SYSCON_SYSPLLCLKSEL_SYSOSC (0x01U << 0)
561
562#define SYSCON_SYSPLLCLKUEN_ENA 0x01U
563
564#define SYSCON_USBPLLCLKSEL_IRC (0U << 0U)
565#define SYSCON_USBPLLCLKSEL_SYSOSC (1U << 0U)
566
567#define SYSCON_USBPLLCLKUEN_ENA 0x01U
568
569#define SYSCON_MAINCLKSEL_IRC (0x00U << 0)
570#define SYSCON_MAINCLKSEL_PLLIN (0x01U << 0)
571#define SYSCON_MAINCLKSEL_WATCHDOG (0x02U << 0)
572#define SYSCON_MAINCLKSEL_PLLOUT (0x03U << 0)
573
574#define SYSCON_MAINCLKUEN_ENA 0x01U
575
576#define SYSCON_SYSAHBCLKCTRL_SYS (1U << 0)
577#define SYSCON_SYSAHBCLKCTRL_ROM (1U << 1)
578#define SYSCON_SYSAHBCLKCTRL_RAM0 (1U << 2)
579#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1U << 3)
580#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1U << 4)
581#define SYSCON_SYSAHBCLKCTRL_I2C (1U << 5)
582#define SYSCON_SYSAHBCLKCTRL_GPIO (1U << 6)
583#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1U << 7)
584#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1U << 8)
585#define SYSCON_SYSAHBCLKCTRL_CT32B0 (1U << 9)
586#define SYSCON_SYSAHBCLKCTRL_CT32B1 (1U << 10)
587#define SYSCON_SYSAHBCLKCTRL_SSP0 (1U << 11)
588#define SYSCON_SYSAHBCLKCTRL_USART (1U << 12)
589#define SYSCON_SYSAHBCLKCTRL_ADC (1U << 13)
590#define SYSCON_SYSAHBCLKCTRL_USB (1U << 14)
591#define SYSCON_SYSAHBCLKCTRL_WWDT (1U << 15)
592#define SYSCON_SYSAHBCLKCTRL_IOCON (1U << 16)
593#define SYSCON_SYSAHBCLKCTRL_SSP1 (1U << 18)
594#define SYSCON_SYSAHBCLKCTRL_PINT (1U << 19)
595#define SYSCON_SYSAHBCLKCTRL_GROUP0INT (1U << 23)
596#define SYSCON_SYSAHBCLKCTRL_GROUP1INT (1U << 24)
597#define SYSCON_SYSAHBCLKCTRL_RAM1 (1U << 26)
598#define SYSCON_SYSAHBCLKCTRL_USBRAM (1U << 27)
599
600#define SYSCON_USBCLKSEL_USBPLLOUT (0U << 0U)
601#define SYSCON_USBCLKSEL_MAINCLK (1U << 0U)
602
603#define SYSCON_USBCLKUEN_ENA 0x01U
604
605#define SYSCON_USBCLKDIV_MASK
606
607#define SYSCON_PDRUNCFG_IRCOUT_PD (1U << 0U)
608#define SYSCON_PDRUNCFG_IRC_PD (1U << 1U)
609#define SYSCON_PDRUNCFG_FLASH_PD (1U << 2U)
610#define SYSCON_PDRUNCFG_BOD_PD (1U << 3U)
611#define SYSCON_PDRUNCFG_ADC_PD (1U << 4U)
612#define SYSCON_PDRUNCFG_SYSSOC_PD (1U << 5U)
613#define SYSCON_PDRUNCFG_WDTOSC_PD (1U << 6U)
614#define SYSCON_PDRUNCFG_SYSPLL_PD (1U << 7U)
615#define SYSCON_PDRUNCFG_USBPLL_PD (1U << 8U)
616#define SYSCON_PDRUNCFG_USBPAD_PD (1U << 10U)
617// ------------------------------------------------------------------------------------------------
618// ----- GPIO_PIN_INT -----
619// ------------------------------------------------------------------------------------------------
620
621
622/**
623 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PIN_INT)
624 */
625
626typedef struct { /*!< (@ 0x4004C000) GPIO_PIN_INT Structure */
627 __IO uint32_t ISEL; /*!< (@ 0x4004C000) Pin Interrupt Mode register */
628 __IO uint32_t IENR; /*!< (@ 0x4004C004) Pin Interrupt Enable (Rising) register */
629 __IO uint32_t SIENR; /*!< (@ 0x4004C008) Set Pin Interrupt Enable (Rising) register */
630 __IO uint32_t CIENR; /*!< (@ 0x4004C00C) Clear Pin Interrupt Enable (Rising) register */
631 __IO uint32_t IENF; /*!< (@ 0x4004C010) Pin Interrupt Enable Falling Edge / Active Level register */
632 __IO uint32_t SIENF; /*!< (@ 0x4004C014) Set Pin Interrupt Enable Falling Edge / Active Level register */
633 __IO uint32_t CIENF; /*!< (@ 0x4004C018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
634 __IO uint32_t RISE; /*!< (@ 0x4004C01C) Pin Interrupt Rising Edge register */
635 __IO uint32_t FALL; /*!< (@ 0x4004C020) Pin Interrupt Falling Edge register */
636 __IO uint32_t IST; /*!< (@ 0x4004C024) Pin Interrupt Status register */
637} LPC_GPIO_PIN_INT_Type;
638
639
640// ------------------------------------------------------------------------------------------------
641// ----- GPIO_GROUP_INT0/1 -----
642// ------------------------------------------------------------------------------------------------
643
644
645/**
646 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_GROUP_INT0)
647 */
648
649typedef struct { /*!< (@ 0x4005C000) GPIO_GROUP_INT0 Structure */
650 __IO uint32_t CTRL; /*!< (@ 0x4005C000) GPIO grouped interrupt control register */
651 __I uint32_t RESERVED0[7];
652 __IO uint32_t PORT_POL[2]; /*!< (@ 0x4005C020) GPIO grouped interrupt port 0 polarity register */
653 __I uint32_t RESERVED1[6];
654 __IO uint32_t PORT_ENA[2]; /*!< (@ 0x4005C040) GPIO grouped interrupt port 0/1 enable register */
655} LPC_GPIO_GROUP_INTx_Type;
656
657
658
659// ------------------------------------------------------------------------------------------------
660// ----- USB -----
661// ------------------------------------------------------------------------------------------------
662
663
664/**
665 * @brief Product name title=UM10462 Chapter title=LPC11U1x USB2.0device controller Modification date=3/16/2011 Major revision=0 Minor revision=3 (USB)
666 */
667
668typedef struct { /*!< (@ 0x40080000) USB Structure */
669 __IO uint32_t DEVCMDSTAT; /*!< (@ 0x40080000) USB Device Command/Status register */
670 __IO uint32_t INFO; /*!< (@ 0x40080004) USB Info register */
671 __IO uint32_t EPLISTSTART; /*!< (@ 0x40080008) USB EP Command/Status List start address */
672 __IO uint32_t DATABUFSTART; /*!< (@ 0x4008000C) USB Data buffer start address */
673 __IO uint32_t LPM; /*!< (@ 0x40080010) Link Power Management register */
674 __IO uint32_t EPSKIP; /*!< (@ 0x40080014) USB Endpoint skip */
675 __IO uint32_t EPINUSE; /*!< (@ 0x40080018) USB Endpoint Buffer in use */
676 __IO uint32_t EPBUFCFG; /*!< (@ 0x4008001C) USB Endpoint Buffer Configuration register */
677 __IO uint32_t INTSTAT; /*!< (@ 0x40080020) USB interrupt status register */
678 __IO uint32_t INTEN; /*!< (@ 0x40080024) USB interrupt enable register */
679 __IO uint32_t INTSETSTAT; /*!< (@ 0x40080028) USB set interrupt status register */
680 __IO uint32_t INTROUTING; /*!< (@ 0x4008002C) USB interrupt routing register */
681 __I uint32_t RESERVED0[1];
682 __I uint32_t EPTOGGLE; /*!< (@ 0x40080034) USB Endpoint toggle register */
683} LPC_USB_Type;
684
685#define USB_DEVCMDSTAT_DEVADDR_POS 0U
686#define USB_DEVCMDSTAT_DEVADDR_MASK (0x7FU << USB_DEVCMDSTAT_DEVADDR_POS)
687#define USB_DEVCMDSTAT_DEV_EN (1U << 7U)
688#define USB_DEVCMDSTAT_SETUP (1U << 8U)
689#define USB_DEVCMDSTAT_PLL_ON (1U << 9U)
690#define USB_DEVCMDSTAT_LPM_SUP (1U << 11U)
691#define USB_DEVCMDSTAT_INTONNAK_AO (1U << 12U)
692#define USB_DEVCMDSTAT_INTONNAK_AI (1U << 13U)
693#define USB_DEVCMDSTAT_INTONNAK_CO (1U << 14U)
694#define USB_DEVCMDSTAT_INTONNAK_CI (1U << 15U)
695#define USB_DEVCMDSTAT_DCON (1U << 16U)
696#define USB_DEVCMDSTAT_DSUP (1U << 17U)
697#define USB_DEVCMDSTAT_LPM_SUS (1U << 19U)
698#define USB_DEVCMDSTAT_LPM_REWP (1U << 20U)
699#define USB_DEVCMDSTAT_DCON_C (1U << 24U)
700#define USB_DEVCMDSTAT_DSUS_C (1U << 25U)
701#define USB_DEVCMDSTAT_DRES_C (1U << 26U)
702
703#define USB_INFO_FRAME_NR_POS 0U
704#define USB_INFO_FRAME_NR_MASK (0x7FFU << USB_INFO_FRAME_NR_POS)
705
706#define USB_EPLISTSTART_POS (8U)
707#define USB_EPLISTSTART_MASK (0xFFFFFF << USB_EPLISTSTART_POS)
708
709#define USB_DATABUFSTART_POS (22U)
710#define USB_DATABUFSTART_MASK (0x3FF << USB_DATABUFSTART_POS)
711
712#define USB_INT_EPn_INT (1U)
713#define USB_INT_EP(ep) (1U << (ep))
714#define USB_INT_EP_ALL_INT (0x3FF)
715#define USB_INT_FRAME_INT (1U << 30U)
716#define USB_INT_DEV_INT (1U << 31U)
717
718// ------------------------------------------------------------------------------------------------
719// ----- GPIO_PORT -----
720// ------------------------------------------------------------------------------------------------
721
722
723/**
724 * @brief Product name title=UM10462 Chapter title=LPC11U1x GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
725 */
726
727typedef struct {
728 union {
729 struct {
730 __IO uint8_t B0[32]; /*!< (@ 0x50000000) Byte pin registers port 0; pins PIO0_0 to PIO0_31 */
731 __IO uint8_t B1[32]; /*!< (@ 0x50000020) Byte pin registers port 1 */
732 };
733 __IO uint8_t B[64]; /*!< (@ 0x50000000) Byte pin registers port 0/1 */
734 };
735 __I uint32_t RESERVED0[1008];
736 union {
737 struct {
738 __IO uint32_t W0[32]; /*!< (@ 0x50001000) Word pin registers port 0 */
739 __IO uint32_t W1[32]; /*!< (@ 0x50001080) Word pin registers port 1 */
740 };
741 __IO uint32_t W[64]; /*!< (@ 0x50001000) Word pin registers port 0/1 */
742 };
743 uint32_t RESERVED1[960];
744 __IO uint32_t DIR[2]; /* 0x2000 */
745 uint32_t RESERVED2[30];
746 __IO uint32_t MASK[2]; /* 0x2080 */
747 uint32_t RESERVED3[30];
748 __IO uint32_t PIN[2]; /* 0x2100 */
749 uint32_t RESERVED4[30];
750 __IO uint32_t MPIN[2]; /* 0x2180 */
751 uint32_t RESERVED5[30];
752 __IO uint32_t SET[2]; /* 0x2200 */
753 uint32_t RESERVED6[30];
754 __O uint32_t CLR[2]; /* 0x2280 */
755 uint32_t RESERVED7[30];
756 __O uint32_t NOT[2]; /* 0x2300 */
757} LPC_GPIO_Type;
758
759
760#if defined ( __CC_ARM )
761 #pragma no_anon_unions
762#endif
763
764
765// ------------------------------------------------------------------------------------------------
766// ----- Peripheral memory map -----
767// ------------------------------------------------------------------------------------------------
768
769#define LPC_I2C_BASE (0x40000000)
770#define LPC_WWDT_BASE (0x40004000)
771#define LPC_USART_BASE (0x40008000)
772#define LPC_CT16B0_BASE (0x4000C000)
773#define LPC_CT16B1_BASE (0x40010000)
774#define LPC_CT32B0_BASE (0x40014000)
775#define LPC_CT32B1_BASE (0x40018000)
776#define LPC_ADC_BASE (0x4001C000)
777#define LPC_PMU_BASE (0x40038000)
778#define LPC_FLASHCTRL_BASE (0x4003C000)
779#define LPC_SSP0_BASE (0x40040000)
780#define LPC_SSP1_BASE (0x40058000)
781#define LPC_IOCON_BASE (0x40044000)
782#define LPC_SYSCON_BASE (0x40048000)
783#define LPC_GPIO_PIN_INT_BASE (0x4004C000)
784#define LPC_GPIO_GROUP_INT0_BASE (0x4005C000)
785#define LPC_GPIO_GROUP_INT1_BASE (0x40060000)
786#define LPC_USB_BASE (0x40080000)
787#define LPC_GPIO_BASE (0x50000000)
788
789
790// ------------------------------------------------------------------------------------------------
791// ----- Peripheral declaration -----
792// ------------------------------------------------------------------------------------------------
793
794#define LPC_I2C ((LPC_I2C_Type *) LPC_I2C_BASE)
795#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
796#define LPC_USART ((LPC_USART_Type *) LPC_USART_BASE)
797#define LPC_CT16B0 ((LPC_CTxxBx_Type *) LPC_CT16B0_BASE)
798#define LPC_CT16B1 ((LPC_CTxxBx_Type *) LPC_CT16B1_BASE)
799#define LPC_CT32B0 ((LPC_CTxxBx_Type *) LPC_CT32B0_BASE)
800#define LPC_CT32B1 ((LPC_CTxxBx_Type *) LPC_CT32B1_BASE)
801#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
802#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
803#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
804#define LPC_SSP0 ((LPC_SSPx_Type *) LPC_SSP0_BASE)
805#define LPC_SSP1 ((LPC_SSPx_Type *) LPC_SSP1_BASE)
806#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
807#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
808#define LPC_GPIO_PIN_INT ((LPC_GPIO_PIN_INT_Type *) LPC_GPIO_PIN_INT_BASE)
809#define LPC_GPIO_GROUP_INT0 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT0_BASE)
810#define LPC_GPIO_GROUP_INT1 ((LPC_GPIO_GROUP_INTx_Type*) LPC_GPIO_GROUP_INT1_BASE)
811#define LPC_USB ((LPC_USB_Type *) LPC_USB_BASE)
812#define LPC_GPIO ((LPC_GPIO_Type *) LPC_GPIO_BASE)
813
814
815/** @} */ /* End of group Device_Peripheral_Registers */
816/** @} */ /* End of group (null) */
817/** @} */ /* End of group LPC11Uxx */
818
819#ifdef __cplusplus
820}
821#endif
822
823
824#endif // __LPC11UXX_H__
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