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1/**************************************************************************//**
2 * @file NUC123.h
3 * @version V3.0
4 * $Revision: 85 $
5 * $Date: 17/05/26 10:49a $
6 * @brief NUC123 Series Peripheral Access Layer Header File
7 *
8 * @note
9 * SPDX-License-Identifier: Apache-2.0
10 * Copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved.
11 *
12 ******************************************************************************/
13
14/**
15 \mainpage Introduction
16 *
17 *
18 * This user manual describes the usage of NUC123 Series MCU device driver
19 *
20 * <b>Disclaimer</b>
21 *
22 * The Software is furnished "AS IS", without warranty as to performance or results, and
23 * the entire risk as to performance or results is assumed by YOU. Nuvoton disclaims all
24 * warranties, express, implied or otherwise, with regard to the Software, its use, or
25 * operation, including without limitation any and all warranties of merchantability, fitness
26 * for a particular purpose, and non-infringement of intellectual property rights.
27 *
28 * <b>Copyright Notice</b>
29 *
30 * Copyright (C) 2014~2016 Nuvoton Technology Corp. All rights reserved.
31 */
32
33
34#ifndef __NUC123_H__
35#define __NUC123_H__
36
37/*
38 * ==========================================================================
39 * ---------- Interrupt Number Definition -----------------------------------
40 * ==========================================================================
41*/
42
43/** @addtogroup MCU_CMSIS Device Definitions for CMSIS
44 Interrupt Number Definition and Configurations for CMSIS
45 @{
46*/
47
48/**
49 * @details Interrupt Number Definition. The maximum of 32 Specific Interrupts are possible.
50 */
51
52typedef enum IRQn
53{
54 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
55 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
56 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
58 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
59 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
60
61 /****** ARMIKMCU Swift specific Interrupt Numbers ************************************************/
62 BOD_IRQn = 0, /*!< Brown-Out Low Voltage Detected Interrupt */
63 WDT_IRQn = 1, /*!< Watch Dog Timer Interrupt */
64 EINT0_IRQn = 2, /*!< EINT0 Interrupt */
65 EINT1_IRQn = 3, /*!< EINT1 Interrupt */
66 GPAB_IRQn = 4, /*!< GPIO_PA/PB Interrupt */
67 GPCDF_IRQn = 5, /*!< GPIO_PC/PD/PF Interrupt */
68 PWMA_IRQn = 6, /*!< PWMA Interrupt */
69 TMR0_IRQn = 8, /*!< TIMER0 Interrupt */
70 TMR1_IRQn = 9, /*!< TIMER1 Interrupt */
71 TMR2_IRQn = 10, /*!< TIMER2 Interrupt */
72 TMR3_IRQn = 11, /*!< TIMER3 Interrupt */
73 UART0_IRQn = 12, /*!< UART0 Interrupt */
74 UART1_IRQn = 13, /*!< UART1 Interrupt */
75 SPI0_IRQn = 14, /*!< SPI0 Interrupt */
76 SPI1_IRQn = 15, /*!< SPI1 Interrupt */
77 SPI2_IRQn = 16, /*!< SPI2 Interrupt */
78 I2C0_IRQn = 18, /*!< I2C0 Interrupt */
79 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
80 CAN0_IRQn = 20, /*!< CAN0 Interrupt */
81 CAN1_IRQn = 21, /*!< CAN1 Interrupt */
82 USBD_IRQn = 23, /*!< USB device Interrupt */
83 PS2_IRQn = 24, /*!< PS/2 device Interrupt */
84 PDMA_IRQn = 26, /*!< PDMA Interrupt */
85 I2S_IRQn = 27, /*!< I2S Interrupt */
86 PWRWU_IRQn = 28, /*!< Power Down Wake Up Interrupt */
87 ADC_IRQn = 29, /*!< ADC Interrupt */
88 IRC_IRQn = 30, /*!< IRC TRIM Interrupt */
89} IRQn_Type;
90
91
92/*
93 * ==========================================================================
94 * ----------- Processor and Core Peripheral Section ------------------------
95 * ==========================================================================
96 */
97
98/* Configuration of the Cortex-M0 Processor and Core Peripherals */
99#define __MPU_PRESENT 0 /*!< armikcmu does not provide a MPU present or not */
100#define __NVIC_PRIO_BITS 2 /*!< armikcmu Supports 2 Bits for the Priority Levels */
101#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
102
103
104/*@}*/ /* end of group MCU_CMSIS */
105
106
107#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
108#include "system_NUC123.h" /* NUC123 System */
109
110#if defined ( __CC_ARM )
111#pragma anon_unions
112#endif
113
114
115/*-------------------------------- Device Specific Peripheral registers structures ---------------------*/
116/** @addtogroup REGISTER Control Register
117 Peripheral Control Registers
118 @{
119 */
120
121/*----------------------------- ADC Controller -------------------------------*/
122/** @addtogroup REG_ADC Analog to Digital Converter (ADC)
123 Memory Mapped Structure for ADC Controller
124 @{
125 */
126
127typedef struct
128{
129
130
131
132/**
133 * @var ADC_T::ADDR
134 * Offset: 0x00-0x1C ADC Data Register x
135 * ---------------------------------------------------------------------------------------------------
136 * |Bits |Field |Descriptions
137 * | :----: | :----: | :---- |
138 * |[9:0] |RSLT |A/D Conversion Result
139 * | | |This field contains conversion result of ADC.
140 * |[16] |OVERRUN |Overrun Flag (Read Only)
141 * | | |If converted data in RSLT has not been read before new conversion result is loaded to this register, OVERRUN is set to 1 and previous conversion result is gone.
142 * | | |It is cleared by hardware after ADDR register is read.
143 * | | |0 = Data in RSLT (ADDRx[9:0], x=0~7) is recent conversion result.
144 * | | |1 = Data in RSLT (ADDRx[9:0], x=0~7) is overwritten.
145 * |[17] |VALID |Valid Flag (Read Only)
146 * | | |This bit is set to 1 when corresponding channel analog input conversion is completed and cleared by hardware after ADDR register is read.
147 * | | |0 = Data in RSLT bits (ADDRx[9:0], x=0~7) is not valid.
148 * | | |1 = Data in RSLT bits (ADDRx[9:0], x=0~7) is valid.
149 * @var ADC_T::ADCR
150 * Offset: 0x20 ADC Control Register
151 * ---------------------------------------------------------------------------------------------------
152 * |Bits |Field |Descriptions
153 * | :----: | :----: | :---- |
154 * |[0] |ADEN |A/D Converter Enable Bit
155 * | | |Before starting A/D conversion function, this bit should be set to 1.
156 * | | |Clear it to 0 to disable A/D converter analog circuit for saving power consumption.
157 * | | |0 = A/D converter Disabled.
158 * | | |1 = A/D converter Enabled.
159 * |[1] |ADIE |A/D Interrupt Enable Bit
160 * | | |A/D conversion end interrupt request is generated if ADIE bit is set to 1.
161 * | | |0 = A/D interrupt function Disabled.
162 * | | |1 = A/D interrupt function Enabled.
163 * |[3:2] |ADMD |A/D Converter Operation Mode
164 * | | |00 = Single conversion.
165 * | | |01 = Reserved.
166 * | | |10 = Single-cycle scan.
167 * | | |11 = Continuous scan.
168 * | | |When changing the operation mode, software should disable ADST bit (ADCR[11]) firstly.
169 * |[5:4] |TRGS |Hardware Trigger Source
170 * | | |00 = A/D conversion is started by external STADC pin.
171 * | | |11 = A/D conversion is started by PWM Center-aligned trigger.
172 * | | |Others = Reserved.
173 * | | |Note: TRGEN (ADCR[8]) and ADST (ADCR[11]) shall be cleared to 0 before changing TRGS.
174 * |[7:6] |TRGCOND |External Trigger Condition
175 * | | |These two bits decide external pin STADC trigger event is level or edge.
176 * | | |The signal must be kept at stable state at least 8 PCLKs for level trigger and 4 PCLKs at high and low state for edge trigger.
177 * | | |00 = Low level.
178 * | | |01 = High level.
179 * | | |10 = Falling edge.
180 * | | |11 = Rising edge.
181 * |[8] |TRGEN |Hardware Trigger Enable Bit
182 * | | |Enable or disable triggering of A/D conversion by external STADC pin or by PWM trigger.
183 * | | |0 = External trigger Disabled.
184 * | | |1 = External trigger Enabled.
185 * | | |Note: ADC hardware trigger function is only supported in single-cycle scan mode.
186 * | | |If hardware trigger is enabled, the ADST bit can be set to 1 by the selected hardware trigger source.
187 * |[9] |PTEN |PDMA Transfer Enable Bit
188 * | | |When A/D conversion is completed, the converted data is loaded into ADDR 0~7, software can enable this bit to generate a PDMA data transfer request.
189 * | | |When PTEN=1, software must set ADIE=0 (ADCR[1]) to disable interrupt.
190 * | | |0 = PDMA data transfer Disabled.
191 * | | |1 = PDMA data transfer in ADDR 0~7 Enabled.
192 * |[11] |ADST |A/D Conversion Start
193 * | | |ADST bit can be set to 1 from three sources: software, STADC pin and PWM output.
194 * | | |ADST will be cleared to 0 by hardware automatically at the ends of single mode and single-cycle scan mode.
195 * | | |In continuous scan mode, A/D conversion is continuously performed until software writes 0 to this bit or chip reset.
196 * | | |0 = Conversion stopped and A/D converter entering idle state.
197 * | | |1 = Conversion started.
198 * | | |Note: when ADST is clear to 0 by hardware automatically in single mode, user need to wait one ADC_CLK cycle for next A/D conversion.
199 * @var ADC_T::ADCHER
200 * Offset: 0x24 ADC Channel Enable Register
201 * ---------------------------------------------------------------------------------------------------
202 * |Bits |Field |Descriptions
203 * | :----: | :----: | :---- |
204 * |[7:0] |CHEN |Analog Input Channel Enable Bit
205 * | | |Set CHEN[7:0] to enable the corresponding analog input channel 7 ~ 0.
206 * | | |0 = Channel Disabled.
207 * | | |1 = Channel Enabled.
208 * |[8] |PRESEL |Analog Input Channel 7 Select
209 * | | |0 = External analog input.
210 * | | |1 = Internal band-gap voltage.
211 * | | |Note:
212 * | | |When software selects the band-gap voltage as the analog input source of ADC channel 7, ADC clock rate needs to be limited to slower than 300 kHz.
213 * @var ADC_T::ADCMPR
214 * Offset: 0x28-0x2C ADC Compare Register x
215 * ---------------------------------------------------------------------------------------------------
216 * |Bits |Field |Descriptions
217 * | :----: | :----: | :---- |
218 * |[0] |CMPEN |Compare Enable Bit
219 * | | |Set this bit to 1 to enable ADC controller to compare CMPD (ADCMPRx[25:16]) with specified channel conversion result when converted data is loaded into ADDRx register.
220 * | | |0 = Compare function Disabled.
221 * | | |1 = Compare function Enabled.
222 * |[1] |CMPIE |Compare Interrupt Enable Bit
223 * | | |If the compare function is enabled and the compare condition matches the setting of
224 * | | |CMPCOND (ADCMPRx[2]) and CMPMATCNT (ADCMPRx[11:8]), CMPFx bit (ADSR[2:1])
225 * | | |will be set, in the meanwhile, if CMPIE (ADCMPRx[1]) is set to 1, a compare interrupt
226 * | | |request is generated.
227 * | | |0 = Compare function interrupt Disabled.
228 * | | |1 = Compare function interrupt Enabled.
229 * |[2] |CMPCOND |Compare Condition
230 * | | |0 = Set the compare condition as that when a 10-bit A/D conversion result is less than the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one.
231 * | | |1 = Set the compare condition as that when a 10-bit A/D conversion result is greater or equal to the 10-bit CMPD (ADCMPRx[25:16]), the internal match counter will increase one.
232 * | | |Note: When the internal counter reaches the value to (CMPMATCNT+1), the CMPFx bit will be set.
233 * |[5:3] |CMPCH |Compare Channel Selection
234 * | | |000 = Channel 0 conversion result is selected to be compared.
235 * | | |001 = Channel 1 conversion result is selected to be compared.
236 * | | |010 = Channel 2 conversion result is selected to be compared.
237 * | | |011 = Channel 3 conversion result is selected to be compared.
238 * | | |100 = Channel 4 conversion result is selected to be compared.
239 * | | |101 = Channel 5 conversion result is selected to be compared.
240 * | | |110 = Channel 6 conversion result is selected to be compared.
241 * | | |111 = Channel 7 conversion result is selected to be compared.
242 * |[11:8] |CMPMATCNT |Compare Match Count
243 * | | |When the specified A/D channel analog conversion result matches the compare condition defined by CMPCOND (ADCMPRx[2]), the internal match counter will increase 1,
244 * | | |otherwise, the compare match counter will be cleared to 0.
245 * | | |When the internal counter reaches the value to (CMPMATCNT+1), CMPFx bit (ADSR[2:1]) will be set.
246 * |[25:16] |CMPD |Comparison Data
247 * | | |The 10-bit data is used to compare with conversion result of specified channel.
248 * @var ADC_T::ADSR
249 * Offset: 0x30 ADC Status Register
250 * ---------------------------------------------------------------------------------------------------
251 * |Bits |Field |Descriptions
252 * | :----: | :----: | :---- |
253 * |[0] |ADF |A/D Conversion End Flag
254 * | | |A status flag that indicates the end of A/D conversion.
255 * | | |ADF is set to 1 at these two conditions:
256 * | | |1. When A/D conversion ends in Single mode.
257 * | | |2. When A/D conversion ends on all specified channels in Scan mode.
258 * | | |This flag can be cleared by writing 1 to itself.
259 * |[1] |CMPF0 |Compare Flag
260 * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR0 then this bit is set to 1.
261 * | | |And it is cleared by writing 1 to self.
262 * | | |0 = Conversion result in ADDR does not meet ADCMPR0 setting.
263 * | | |1 = Conversion result in ADDR meets ADCMPR0 setting.
264 * |[2] |CMPF1 |Compare Flag
265 * | | |When the selected channel A/D conversion result meets setting condition in ADCMPR1 then this bit is set to 1.
266 * | | |And it is cleared by writing 1 to self.
267 * | | |0 = Conversion result in ADDR does not meet ADCMPR1 setting.
268 * | | |1 = Conversion result in ADDR meets ADCMPR1 setting.
269 * |[3] |BUSY |BUSY/IDLE (Read Only)
270 * | | |0 = A/D converter is in idle state.
271 * | | |1 = A/D converter is busy at conversion.
272 * | | |This bit is a mirror of ADST bit in ADCR.
273 * |[6:4] |CHANNEL |Current Conversion Channel (Read Only)
274 * | | |This field reflects the current conversion channel when BUSY = 1 (ADSR[3]).
275 * | | |When BUSY(ADSR[3]) = 0, it shows the number of the next converted channel.
276 * |[15:8] |VALID |Data Valid Flag (Read Only)
277 * | | |VALID[7:0] is a mirror of the VALID bits in ADDR7[17] ~ ADDR0[17].
278 * | | |It is read only.
279 * |[23:16] |OVERRUN |Overrun Flag (Read Only)
280 * | | |OVERRUN[7:0] is a mirror of the OVERRUN bits in ADDR7[16] ~ ADDR0[16].
281 * @var ADC_T::ADPDMA
282 * Offset: 0x40 ADC PDMA Current Transfer Data Register
283 * ---------------------------------------------------------------------------------------------------
284 * |Bits |Field |Descriptions
285 * | :----: | :----: | :---- |
286 * |[9:0] |AD_PDMA |ADC PDMA Current Transfer Data Register (Read Only)
287 * | | |When transferring A/D conversion result with PDMA, software can read this register to monitor current PDMA transfer data.
288 */
289
290 __I uint32_t ADDR[8]; /* Offset: 0x00-0x1C ADC Data Register x */
291 __IO uint32_t ADCR; /* Offset: 0x20 ADC Control Register */
292 __IO uint32_t ADCHER; /* Offset: 0x24 ADC Channel Enable Register */
293 __IO uint32_t ADCMPR[2]; /* Offset: 0x28-0x2C ADC Compare Register x */
294 __IO uint32_t ADSR; /* Offset: 0x30 ADC Status Register */
295 __I uint32_t RESERVE0[3];
296 __I uint32_t ADPDMA; /* Offset: 0x40 ADC PDMA Current Transfer Data Register */
297
298} ADC_T;
299
300
301
302/** @addtogroup REG_ADC_BITMASK ADC Bit Mask
303 @{
304 */
305
306/* ADDR Bit Field Definitions */
307#define ADC_ADDR_VALID_Pos 17 /*!< ADC_T::ADDR: VALID Position */
308#define ADC_ADDR_VALID_Msk (1ul << ADC_ADDR_VALID_Pos) /*!< ADC_T::ADDR: VALID Mask */
309
310#define ADC_ADDR_OVERRUN_Pos 16 /*!< ADC_T::ADDR: OVERRUN Position */
311#define ADC_ADDR_OVERRUN_Msk (1ul << ADC_ADDR_OVERRUN_Pos) /*!< ADC_T::ADDR: OVERRUN Mask */
312
313#define ADC_ADDR_RSLT_Pos 0 /*!< ADC_T::ADDR: RSLT Position */
314#define ADC_ADDR_RSLT_Msk (0x3FFul << ADC_ADDR_RSLT_Pos) /*!< ADC_T::ADDR: RSLT Mask */
315
316/* ADCR Bit Field Definitions */
317#define ADC_ADCR_ADST_Pos 11 /*!< ADC_T::ADCR: ADST Position */
318#define ADC_ADCR_ADST_Msk (1ul << ADC_ADCR_ADST_Pos) /*!< ADC_T::ADCR: ADST Mask */
319
320#define ADC_ADCR_PTEN_Pos 9 /*!< ADC_T::ADCR: PTEN Position */
321#define ADC_ADCR_PTEN_Msk (1ul << ADC_ADCR_PTEN_Pos) /*!< ADC_T::ADCR: PTEN Mask */
322
323#define ADC_ADCR_TRGEN_Pos 8 /*!< ADC_T::ADCR: TRGEN Position */
324#define ADC_ADCR_TRGEN_Msk (1ul << ADC_ADCR_TRGEN_Pos) /*!< ADC_T::ADCR: TRGEN Mask */
325
326#define ADC_ADCR_TRGCOND_Pos 6 /*!< ADC_T::ADCR: TRGCOND Position */
327#define ADC_ADCR_TRGCOND_Msk (3ul << ADC_ADCR_TRGCOND_Pos) /*!< ADC_T::ADCR: TRGCOND Mask */
328
329#define ADC_ADCR_TRGS_Pos 4 /*!< ADC_T::ADCR: TRGS Position */
330#define ADC_ADCR_TRGS_Msk (3ul << ADC_ADCR_TRGS_Pos) /*!< ADC_T::ADCR: TRGS Mask */
331
332#define ADC_ADCR_ADMD_Pos 2 /*!< ADC_T::ADCR: ADMD Position */
333#define ADC_ADCR_ADMD_Msk (3ul << ADC_ADCR_ADMD_Pos) /*!< ADC_T::ADCR: ADMD Mask */
334
335#define ADC_ADCR_ADIE_Pos 1 /*!< ADC_T::ADCR: ADIE Position */
336#define ADC_ADCR_ADIE_Msk (1ul << ADC_ADCR_ADIE_Pos) /*!< ADC_T::ADCR: ADIE Mask */
337
338#define ADC_ADCR_ADEN_Pos 0 /*!< ADC_T::ADCR: ADEN Position */
339#define ADC_ADCR_ADEN_Msk (1ul << ADC_ADCR_ADEN_Pos) /*!< ADC_T::ADCR: ADEN Mask */
340
341/* ADCHER Bit Field Definitions */
342#define ADC_ADCHER_PRESEL_Pos 8 /*!< ADC_T::ADCHER: PRESEL Position */
343#define ADC_ADCHER_PRESEL_Msk (1ul << ADC_ADCHER_PRESEL_Pos) /*!< ADC_T::ADCHER: PRESEL Mask */
344
345#define ADC_ADCHER_CHEN_Pos 0 /*!< ADC_T::ADCHER: CHEN Position */
346#define ADC_ADCHER_CHEN_Msk (0xFFul << ADC_ADCHER_CHEN_Pos) /*!< ADC_T::ADCHER: CHEN Mask */
347
348/* ADCMPR Bit Field Definitions */
349#define ADC_ADCMPR_CMPD_Pos 16 /*!< ADC_T::ADCMPR: CMPD Position */
350#define ADC_ADCMPR_CMPD_Msk (0x3FFul << ADC_ADCMPR_CMPD_Pos) /*!< ADC_T::ADCMPR: CMPD Mask */
351
352#define ADC_ADCMPR_CMPMATCNT_Pos 8 /*!< ADC_T::ADCMPR: CMPMATCNT Position */
353#define ADC_ADCMPR_CMPMATCNT_Msk (0xFul << ADC_ADCMPR_CMPMATCNT_Pos) /*!< ADC_T::ADCMPR: CMPMATCNT Mask */
354
355#define ADC_ADCMPR_CMPCH_Pos 3 /*!< ADC_T::ADCMPR: CMPCH Position */
356#define ADC_ADCMPR_CMPCH_Msk (7ul << ADC_ADCMPR_CMPCH_Pos) /*!< ADC_T::ADCMPR: CMPCH Mask */
357
358#define ADC_ADCMPR_CMPCOND_Pos 2 /*!< ADC_T::ADCMPR: CMPCOND Position */
359#define ADC_ADCMPR_CMPCOND_Msk (1ul << ADC_ADCMPR_CMPCOND_Pos) /*!< ADC_T::ADCMPR: CMPCOND Mask */
360
361#define ADC_ADCMPR_CMPIE_Pos 1 /*!< ADC_T::ADCMPR: CMPIE Position */
362#define ADC_ADCMPR_CMPIE_Msk (1ul << ADC_ADCMPR_CMPIE_Pos) /*!< ADC_T::ADCMPR: CMPIE Mask */
363
364#define ADC_ADCMPR_CMPEN_Pos 0 /*!< ADC_T::ADCMPR: CMPEN Position */
365#define ADC_ADCMPR_CMPEN_Msk (1ul << ADC_ADCMPR_CMPEN_Pos) /*!< ADC_T::ADCMPR: CMPEN Mask */
366
367/* ADSR Bit Field Definitions */
368#define ADC_ADSR_OVERRUN_Pos 16 /*!< ADC_T::ADSR: OVERRUN Position */
369#define ADC_ADSR_OVERRUN_Msk (0xFFul << ADC_ADSR_OVERRUN_Pos) /*!< ADC_T::ADSR: OVERRUN Mask */
370
371#define ADC_ADSR_VALID_Pos 8 /*!< ADC_T::ADSR: VALID Position */
372#define ADC_ADSR_VALID_Msk (0xFFul << ADC_ADSR_VALID_Pos) /*!< ADC_T::ADSR: VALID Mask */
373
374#define ADC_ADSR_CHANNEL_Pos 4 /*!< ADC_T::ADSR: CHANNEL Position */
375#define ADC_ADSR_CHANNEL_Msk (7ul << ADC_ADSR_CHANNEL_Pos) /*!< ADC_T::ADSR: CHANNEL Mask */
376
377#define ADC_ADSR_BUSY_Pos 3 /*!< ADC_T::ADSR: BUSY Position */
378#define ADC_ADSR_BUSY_Msk (1ul << ADC_ADSR_BUSY_Pos) /*!< ADC_T::ADSR: BUSY Mask */
379
380#define ADC_ADSR_CMPF1_Pos 2 /*!< ADC_T::ADSR: CMPF1 Position */
381#define ADC_ADSR_CMPF1_Msk (1ul << ADC_ADSR_CMPF1_Pos) /*!< ADC_T::ADSR: CMPF1 Mask */
382
383#define ADC_ADSR_CMPF0_Pos 1 /*!< ADC_T::ADSR: CMPF0 Position */
384#define ADC_ADSR_CMPF0_Msk (1ul << ADC_ADSR_CMPF0_Pos) /*!< ADC_T::ADSR: CMPF0 Mask */
385
386#define ADC_ADSR_ADF_Pos 0 /*!< ADC_T::ADSR: ADF Position */
387#define ADC_ADSR_ADF_Msk (1ul << ADC_ADSR_ADF_Pos) /*!< ADC_T::ADSR: ADF Mask */
388
389/* ADPDMA Bit Field Definitions */
390#define ADC_ADPDMA_AD_PDMA_Pos 0 /*!< ADC_T::ADPDMA: AD_PDMA Position */
391#define ADC_ADPDMA_AD_PDMA_Msk (0x3FFul << ADC_ADPDMA_AD_PDMA_Pos) /*!< ADC_T::ADPDMA: AD_PDMA Mask */
392/*@}*/ /* end of group REG_ADC_BITMASK */
393/*@}*/ /* end of group REG_ADC */
394
395
396/*---------------------------- Clock Controller ------------------------------*/
397/** @addtogroup REG_CLK System Clock Controller (CLK)
398 Memory Mapped Structure for System Clock Controller
399 @{
400 */
401
402typedef struct
403{
404
405
406
407/**
408 * @var CLK_T::PWRCON
409 * Offset: 0x00 System Power-down Control Register
410 * ---------------------------------------------------------------------------------------------------
411 * |Bits |Field |Descriptions
412 * | :----: | :----: | :---- |
413 * |[0] |XTL12M_EN |External 4~24 MHz High Speed Crystal Enable (HXT) Control (Write Protect)
414 * | | |The bit default value is set by flash controller user configuration register CFOSC (Config0[26:24]).
415 * | | |When the default clock source is from external 4~24 MHz high speed crystal, this bit is set to 1 automatically.
416 * | | |0 = External 4~24 MHz high speed crystal oscillator (HXT) Disabled.
417 * | | |1 = External 4~24 MHz high speed crystal oscillator (HXT) Enabled.
418 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
419 * |[2] |OSC22M_EN |Internal 22.1184 MHz High Speed Oscillator (HIRC) Enable Control (Write Protect)
420 * | | |0 = Internal 22.1184 MHz high speed oscillator (HIRC) Disabled.
421 * | | |1 = Internal 22.1184 MHz high speed oscillator (HIRC) Enabled.
422 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
423 * |[3] |OSC10K_EN |Internal 10 KHz Low Speed Oscillator (LIRC) Enable Control (Write Protect)
424 * | | |0 = Internal 10 kHz low speed oscillator (LIRC) Disabled.
425 * | | |1 = Internal 10 kHz low speed oscillator (LIRC) Enabled.
426 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
427 * |[4] |PD_WU_DLY |Wake-up Delay Counter Enable Control (Write Protect)
428 * | | |When the chip wakes up from Power-down mode, the clock control will delay certain clock cycles to wait system clock stable.
429 * | | |The delayed clock cycle is 4096 clock cycles when chip work at external 4~24 MHz high speed crystal, and 256 clock cycles when chip work at internal 22.1184 MHz high speed oscillator.
430 * | | |0 = Clock cycles delay Disabled.
431 * | | |1 = Clock cycles delay Enabled.
432 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
433 * |[5] |PD_WU_INT_EN|Power-Down Mode Wake-Up Interrupt Enable Control (Write Protect)
434 * | | |0 = Power-down mode wake-up interrupt Disabled.
435 * | | |1 = Power-down mode wake-up interrupt Enabled.
436 * | | |Note1: The interrupt will occur when both PD_WU_STS and PD_WU_INT_EN are high.
437 * | | |Note2: This bit is write protected bit. Refer to the REGWRPROT register.
438 * |[6] |PD_WU_STS |Power-down Mode Wake-Up Interrupt Status
439 * | | |Set by "Power-down wake-up event", it indicates that resume from Power-down mode.
440 * | | |The flag is set if the GPIO, USB, UART, WDT, TIMER, I2C or BOD wake-up occurred.
441 * | | |This bit can be cleared to 0 by software writing "1".
442 * | | |Note: This bit is working only if PD_WU_INT_EN (PWRCON[5]) set to 1.
443 * |[7] |PWR_DOWN_EN|System Power-down Enable Bit (Write Protect)
444 * | | |When this bit is set to 1, Power-down mode is enabled and chip Power-down behavior will depends on the PD_WAIT_CPU bit
445 * | | |(a) If the PD_WAIT_CPU is 0, then the chip enters Power-down mode immediately after the PWR_DOWN_EN bit set.
446 * | | |(b) if the PD_WAIT_CPU is 1, then the chip keeps active till the CPU sleep mode is also active and then the chip enters Power-down mode (recommend)
447 * | | |When chip wakes up from Power-down mode, this bit is cleared by hardware.
448 * | | |User needs to set this bit again for next Power-down.
449 * | | |In Power-down mode, 4~24 MHz external high speed crystal oscillator (HXT) and the 22.1184 MHz internal high speed RC oscillator (HIRC) will be disabled in this mode, but the 10 kHz internal low speed RC oscillator (LIRC) is not controlled by Power-down mode.
450 * | | |In Power- down mode, the PLL and system clock are disabled, and ignored the clock source selection. The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the 10 kHz internal low speed RC oscillator (LIRC).
451 * | | |The clocks of peripheral are not controlled by Power-down mode, if the peripheral clock source is from the internal 10 kHz low speed oscillator.
452 * | | |0 = Chip operating normally or chip in Idle mode because of WFI command.
453 * | | |1 = Chip enters Power-down mode instantly or waits CPU sleep command WFI.
454 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
455 * |[8] |PD_WAIT_CPU|This Bit Control The Power-Down Entry Condition (Write Protect)
456 * | | |0 = Chip enters Power-down mode when the PWR_DOWN_EN bit is set to 1.
457 * | | |1 = Chip enters Power-down mode when the both PD_WAIT_CPU and PWR_DOWN_EN bits are set to 1 and CPU run WFI instruction.
458 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
459 * @var CLK_T::AHBCLK
460 * Offset: 0x04 AHB Devices Clock Enable Control Register
461 * ---------------------------------------------------------------------------------------------------
462 * |Bits |Field |Descriptions
463 * | :----: | :----: | :---- |
464 * |[1] |PDMA_EN |PDMA Controller Clock Enable Control
465 * | | |0 = PDMA peripheral clock Disabled.
466 * | | |1 = PDMA peripheral clock Enabled.
467 * |[2] |ISP_EN |Flash ISP Controller Clock Enable Control
468 * | | |0 = Flash ISP peripheral clock Disabled.
469 * | | |1 = Flash ISP peripheral clock Enabled.
470 * @var CLK_T::APBCLK
471 * Offset: 0x08 APB Devices Clock Enable Control Register
472 * ---------------------------------------------------------------------------------------------------
473 * |Bits |Field |Descriptions
474 * | :----: | :----: | :---- |
475 * |[0] |WDT_EN |Watchdog Timer Clock Enable Control (Write Protect)
476 * | | |0 = Watchdog Timer clock Disabled.
477 * | | |1 = Watchdog Timer clock Enabled.
478 * | | |Note: This bit is write protected bit. Refer to the REGWRPROT register.
479 * |[2] |TMR0_EN |Timer0 Clock Enable Control
480 * | | |0 = Timer0 clock Disabled.
481 * | | |1 = Timer0 clock Enabled.
482 * |[3] |TMR1_EN |Timer1 Clock Enable Control
483 * | | |0 = Timer1 clock Disabled.
484 * | | |1 = Timer1 clock Enabled.
485 * |[4] |TMR2_EN |Timer2 Clock Enable Control
486 * | | |0 = Timer2 clock Disabled.
487 * | | |1 = Timer2 clock Enabled.
488 * |[5] |TMR3_EN |Timer3 Clock Enable Control
489 * | | |0 = Timer3 clock Disabled.
490 * | | |1 = Timer3 clock Enabled.
491 * |[6] |FDIV_EN |Frequency Divider Output Clock Enable Control
492 * | | |0 = FDIV clock Disabled.
493 * | | |1 = FDIV clock Enabled.
494 * |[8] |I2C0_EN |I2C0 Clock Enable Control
495 * | | |0 = I2C0 clock Disabled.
496 * | | |1 = I2C0 clock Enabled.
497 * |[9] |I2C1_EN |I2C1 Clock Enable Control
498 * | | |0 = I2C1 clock Disabled.
499 * | | |1 = I2C1 clock Enabled.
500 * |[12] |SPI0_EN |SPI0 Clock Enable Control
501 * | | |0 = SPI0 clock Disabled.
502 * | | |1 = SPI0 clock Enabled.
503 * |[13] |SPI1_EN |SPI1 Clock Enable Control
504 * | | |0 = SPI1 clock Disabled.
505 * | | |1 = SPI1 clock Enabled.
506 * |[14] |SPI2_EN |SPI2 Clock Enable Control
507 * | | |0 = SPI2 clock Disabled.
508 * | | |1 = SPI2 clock Enabled.
509 * |[16] |UART0_EN |UART0 Clock Enable Control
510 * | | |0 = UART0 clock Disabled.
511 * | | |1 = UART0 clock Enabled.
512 * |[17] |UART1_EN |UART1 Clock Enable Control
513 * | | |0 = UART1 clock Disabled.
514 * | | |1 = UART1 clock Enabled.
515 * |[20] |PWM01_EN |PWM_01 Clock Enable Control
516 * | | |0 = PWM01 clock Disabled.
517 * | | |1 = PWM01 clock Enabled.
518 * |[21] |PWM23_EN |PWM_23 Clock Enable Control
519 * | | |0 = PWM23 clock Disabled.
520 * | | |1 = PWM23 clock Enabled.
521 * |[27] |USBD_EN |USB 2.0 FS Device Controller Clock Enable Control
522 * | | |0 = USB clock Disabled.
523 * | | |1 = USB clock Enabled.
524 * |[28] |ADC_EN |Analog-Digital-Converter (ADC) Clock Enable Control
525 * | | |0 = ADC clock Disabled.
526 * | | |1 = ADC clock Enabled.
527 * |[29] |I2S_EN |I2S Clock Enable Control
528 * | | |0 = I2S clock Disabled.
529 * | | |1 = I2S clock Enabled.
530 * |[31] |PS2_EN |PS/2 Clock Enable Control
531 * | | |0 = PS/2 clock Disabled.
532 * | | |1 = PS/2 clock Enabled.
533 * @var CLK_T::CLKSTATUS
534 * Offset: 0x0C Clock status monitor Register
535 * ---------------------------------------------------------------------------------------------------
536 * |Bits |Field |Descriptions
537 * | :----: | :----: | :---- |
538 * |[0] |XTL12M_STB|External 4~24 MHz High Speed Crystal (HXT) Clock Source Stable Flag (Read Only)
539 * | | |0 = External 4~24 MHz high speed crystal clock (HXT) is not stable or disabled.
540 * | | |1 = External 4~24 MHz high speed crystal clock (HXT) is stable and enabled.
541 * |[2] |PLL_STB |Internal PLL Clock Source Stable Flag (Read Only)
542 * | | |0 = Internal PLL clock is not stable or disabled.
543 * | | |1 = Internal PLL clock is stable in normal mode.
544 * |[3] |OSC10K_STB|Internal 10 KHz Low Speed Oscillator (LIRC) Clock Source Stable Flag (Read Only)
545 * | | |0 = Internal 10 kHz low speed oscillator clock (LIRC) is not stable or disabled.
546 * | | |1 = Internal 10 kHz low speed oscillator clock (LIRC) is stable and enabled.
547 * |[4] |OSC22M_STB|Internal 22.1184 MHz High Speed Oscillator (HIRC) Clock Source Stable Flag (Read Only)
548 * | | |0 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is not stable or disabled.
549 * | | |1 = Internal 22.1184 MHz high speed oscillator (HIRC) clock is stable and enabled.
550 * |[7] |CLK_SW_FAIL|Clock Switching Fail Flag
551 * | | |This bit is updated when software switches system clock source.
552 * | | |If switch target clock is stable, this bit will be set to 0.
553 * | | |If switch target clock is not stable, this bit will be set to 1.
554 * | | |0 = Clock switching success.
555 * | | |1 = Clock switching failure.
556 * | | |Note1: On NUC123xxxANx, this bit can be cleared to 0 by software writing "1".
557 * | | |Note2: On NUC123xxxAEx, this bit is read only. After selected clock source is stable, hardware will switch system clock to selected clock automatically, and CLK_SW_FAIL will be cleared automatically by hardware.
558 * @var CLK_T::CLKSEL0
559 * Offset: 0x10 Clock Source Select Control Register 0
560 * ---------------------------------------------------------------------------------------------------
561 * |Bits |Field |Descriptions
562 * | :----: | :----: | :---- |
563 * |[2:0] |HCLK_S |HCLK Clock Source Select (Write Protect)
564 * | | |The 3-bit default value is reloaded from the value of CFOSC (CONFIG0[26:24]) in user configuration register of Flash controller by any reset.
565 * | | |Therefore the default value is either 000b or 111b.
566 * | | |000 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
567 * | | |001 = Clock source from PLL/2 clock.
568 * | | |010 = Clock source from PLL clock.
569 * | | |011 = Clock source from internal 10 kHz low speed oscillator clock.
570 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
571 * | | |Note1: Before clock switching, the related clock sources (both pre-select and new-select) must be turn on.
572 * | | |Note2: These bits are write protected bit. Refer to the REGWRPROT register.
573 * |[5:3] |STCLK_S |Cortex-M0 SysTick Clock Source Select (Write Protect)
574 * | | |If SYST_CSR[2] = 1, SysTick clock source is from HCLK.
575 * | | |If SYST_CSR[2] = 0, SysTick clock source is defined by STCLK_S(CLKSEL0[5:3]).
576 * | | |000 = Clock source from external 4~24 MHz high speed crystal clock.
577 * | | |010 = Clock source from external 4~24 MHz high speed crystal clock/2.
578 * | | |011 = Clock source from HCLK/2.
579 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock/2.
580 * | | |Note1: If SysTick clock source is not from HCLK (i.e. SYST_CSR[2] = 0), SysTick clock source must less than or equal to HCLK/2.
581 * | | |Note2: These bits are write protected bit. Refer to the REGWRPROT register.
582 * @var CLK_T::CLKSEL1
583 * Offset: 0x14 Clock Source Select Control Register 1
584 * ---------------------------------------------------------------------------------------------------
585 * |Bits |Field |Descriptions
586 * | :----: | :----: | :---- |
587 * |[1:0] |WDT_S |Watchdog Timer Clock Source Select (Write Protect)
588 * | | |10 = Clock source from HCLK/2048 clock.
589 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
590 * | | |Note: These bits are write protected bit. Refer to the REGWRPROT register.
591 * |[3:2] |ADC_S |ADC Clock Source Select
592 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
593 * | | |01 = Clock source from PLL clock.
594 * | | |10 = Clock source from HCLK.
595 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
596 * |[4] |SPI0_S |SPI0 Clock Source Selection
597 * | | |0 = Clock source from PLL clock.
598 * | | |1 = Clock source from HCLK.
599 * |[5] |SPI1_S |SPI1 Clock Source Selection
600 * | | |0 = Clock source from PLL clock.
601 * | | |1 = Clock source from HCLK.
602 * |[6] |SPI2_S |SPI2 Clock Source Selection
603 * | | |0 = Clock source from PLL clock.
604 * | | |1 = Clock source from HCLK.
605 * |[10:8] |TMR0_S |TIMER0 Clock Source Selection
606 * | | |000 = Clock source from external 4~24 MHz high speed crystal clock.
607 * | | |010 = Clock source from HCLK.
608 * | | |011 = Clock source from external trigger.
609 * | | |101 = Clock source from internal 10 kHz low speed oscillator clock.
610 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
611 * | | |Others = Reserved.
612 * |[14:12] |TMR1_S |TIMER1 Clock Source Selection
613 * | | |000 = Clock source from external 4~24 MHz high speed crystal clock.
614 * | | |010 = Clock source from HCLK.
615 * | | |011 = Clock source from external trigger.
616 * | | |101 = Clock source from internal 10 kHz low speed oscillator clock.
617 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
618 * | | |Others = Reserved.
619 * |[18:16] |TMR2_S |TIMER2 Clock Source Selection
620 * | | |000 = Clock source from external 4~24 MHz high speed crystal clock.
621 * | | |010 = Clock source from HCLK.
622 * | | |011 = Clock source from external trigger.
623 * | | |101 = Clock source from internal 10 kHz low speed oscillator clock.
624 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
625 * | | |Others = Reserved.
626 * |[22:20] |TMR3_S |TIMER3 Clock Source Selection
627 * | | |000 = Clock source from external 4~24 MHz high speed crystal clock.
628 * | | |010 = Clock source from HCLK.
629 * | | |011 = Reserved.
630 * | | |101 = Clock source from internal 10 kHz low speed oscillator clock.
631 * | | |111 = Clock source from internal 22.1184 MHz high speed oscillator clock.
632 * | | |Others = Reserved.
633 * |[25:24] |UART_S |UART Clock Source Selection
634 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
635 * | | |01 = Clock source from PLL clock.
636 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
637 * |[29:28] |PWM01_S |PWM0 and PWM1 Clock Source Selection
638 * | | |PWM0 and PWM1 used the same clock source; both of them used the same prescaler.
639 * | | |The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
640 * | | |If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
641 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
642 * | | |10 = Clock source from HCLK.
643 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
644 * | | |If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
645 * | | |00 = Reserved.
646 * | | |01 = Reserved.
647 * | | |10 = Reserved.
648 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
649 * |[31:30] |PWM23_S |PWM2 and PWM3 Clock Source Selection
650 * | | |PWM2 and PWM3 used the same clock source; both of them used the same prescaler.
651 * | | |The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
652 * | | |If PWM23_S_E = 0, theclock source of PWM2 and PWM3 defined by PWM23_S list below:
653 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
654 * | | |10 = Clock source from HCLK.
655 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
656 * | | |If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
657 * | | |00 = Reserved.
658 * | | |01 = Reserved.
659 * | | |10 = Reserved.
660 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
661 * @var CLK_T::CLKDIV
662 * Offset: 0x18 Clock Divider Number Register
663 * ---------------------------------------------------------------------------------------------------
664 * |Bits |Field |Descriptions
665 * | :----: | :----: | :---- |
666 * |[3:0] |HCLK_N |HCLK Clock Divide Number From HCLK Clock Source
667 * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLK_N + 1).
668 * |[7:4] |USB_N |USB Clock Divide Number From PLL Clock
669 * | | |USB clock frequency = (PLL frequency) / (USB_N + 1).
670 * |[11:8] |UART_N |UART Clock Divide Number From UART Clock Source
671 * | | |UART clock frequency = (UART clock source frequency) / (UART_N + 1).
672 * |[23:16] |ADC_N |ADC Clock Divide Number From ADC Clock Source
673 * | | |ADC clock frequency = (ADC clock source frequency) / (ADC_N + 1).
674 * @var CLK_T::CLKSEL2
675 * Offset: 0x1C Clock Source Select Control Register 2
676 * ---------------------------------------------------------------------------------------------------
677 * |Bits |Field |Descriptions
678 * | :----: | :----: | :---- |
679 * |[1:0] |I2S_S |I2S Clock Source Selection
680 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
681 * | | |01 = Clock source from PLL clock.
682 * | | |10 = Clock source from HCLK.
683 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
684 * |[3:2] |FRQDIV_S |Clock Divider Clock Source Selection
685 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
686 * | | |10 = Clock source from HCLK.
687 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
688 * |[8] |PWM01_S_E |PWM0 and PWM1 Clock Source Selection Extend
689 * | | |PWM0 and PWM1 used the same clock source; both of them used the same prescaler.
690 * | | |The clock source of PWM0 and PWM1 is defined by PWM01_S (CLKSEL1[29:28]) and PWM01_S_E (CLKSEL2[8]).
691 * | | |If PWM01_S_E = 0, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
692 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
693 * | | |10 = Clock source from HCLK.
694 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
695 * | | |If PWM01_S_E = 1, the clock source of PWM0 and PWM1 defined by PWM01_S list below:
696 * | | |00 = Reserved.
697 * | | |01 = Reserved.
698 * | | |10 = Reserved.
699 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
700 * |[9] |PWM23_S_E |PWM2 and PWM3 Clock Source Selection Extend
701 * | | |PWM2 and PWM3 used the same clock source; both of them used the same prescaler.
702 * | | |The clock source of PWM2 and PWM3 is defined by PWM23_S (CLKSEL1[31:30]) and PWM23_S_E (CLKSEL2[9]).
703 * | | |If PWM23_S_E = 0, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
704 * | | |00 = Clock source from external 4~24 MHz high speed crystal oscillator clock.
705 * | | |10 = Clock source from HCLK.
706 * | | |11 = Clock source from internal 22.1184 MHz high speed oscillator clock.
707 * | | |If PWM23_S_E = 1, the clock source of PWM2 and PWM3 defined by PWM23_S list below:
708 * | | |00 = Reserved.
709 * | | |01 = Reserved.
710 * | | |10 = Reserved.
711 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
712 * |[17:16] |WWDT_S |Window Watchdog Timer Clock Source Selection
713 * | | |10 = Clock source from HCLK/2048 clock.
714 * | | |11 = Clock source from internal 10 kHz low speed oscillator clock.
715 * @var CLK_T::PLLCON
716 * Offset: 0x20 PLL Control Register
717 * ---------------------------------------------------------------------------------------------------
718 * |Bits |Field |Descriptions
719 * | :----: | :----: | :---- |
720 * |[8:0] |FB_DV |PLL Feedback Divider Control Bits
721 * | | |Refer to the PLL formulas.
722 * |[13:9] |IN_DV |PLL Input Divider Control Bits
723 * | | |Refer to the PLL formulas.
724 * |[15:14] |OUT_DV |PLL Output Divider Control Bits
725 * | | |Refer to the PLL formulas.
726 * |[16] |PD |Power-down Mode
727 * | | |If the PWR_DOWN_EN bit is set to 1 in PWRCON register, the PLL will enter Power-down mode too.
728 * | | |0 = PLL is in Normal mode.
729 * | | |1 = PLL is in Power-down mode (default).
730 * |[17] |BP |PLL Bypass Control
731 * | | |0 = PLL is in Normal mode (default).
732 * | | |1 = PLL clock output is same as PLL source clock input.
733 * |[18] |OE |PLL OE (FOUT Enable) Control
734 * | | |0 = PLL FOUT Enabled.
735 * | | |1 = PLL FOUT is fixed low.
736 * |[19] |PLL_SRC |PLL Source Clock Selection
737 * | | |0 = PLL source clock from external 4~24 MHz high speed crystal.
738 * | | |1 = PLL source clock from internal 22.1184 MHz high speed oscillator.
739 * @var CLK_T::FRQDIV
740 * Offset: 0x24 Frequency Divider Control Register
741 * ---------------------------------------------------------------------------------------------------
742 * |Bits |Field |Descriptions
743 * | :----: | :----: | :---- |
744 * |[3:0] |FSEL |Divider Output Frequency Selection Bits
745 * | | |The formula of output frequency is Fout = Fin/2(N+1).
746 * | | |Fin is the input clock frequency.
747 * | | |Fout is the frequency of divider output clock.
748 * | | |N is the 4-bit value of FSEL[3:0].
749 * |[4] |DIVIDER_EN|Frequency Divider Enable Bit
750 * | | |0 = Frequency Divider function Disabled.
751 * | | |1 = Frequency Divider function Enabled.
752 * @var CLK_T::APBDIV
753 * Offset: 0x2C APB Divider Control Register
754 * ---------------------------------------------------------------------------------------------------
755 * |Bits |Field |Descriptions
756 * | :----: | :----: | :---- |
757 * |[0] |APBDIV |APB Divider Enable Bit
758 * | | |0 = PCLK is HCLK.
759 * | | |1 = PCLK is HCLK/2.
760 */
761
762 __IO uint32_t PWRCON; /* Offset: 0x00 System Power-down Control Register */
763 __IO uint32_t AHBCLK; /* Offset: 0x04 AHB Devices Clock Enable Control Register */
764 __IO uint32_t APBCLK; /* Offset: 0x08 APB Devices Clock Enable Control Register */
765 __IO uint32_t CLKSTATUS; /* Offset: 0x0C Clock status monitor Register */
766 __IO uint32_t CLKSEL0; /* Offset: 0x10 Clock Source Select Control Register 0 */
767 __IO uint32_t CLKSEL1; /* Offset: 0x14 Clock Source Select Control Register 1 */
768 __IO uint32_t CLKDIV; /* Offset: 0x18 Clock Divider Number Register */
769 __IO uint32_t CLKSEL2; /* Offset: 0x1C Clock Source Select Control Register 2 */
770 __IO uint32_t PLLCON; /* Offset: 0x20 PLL Control Register */
771 __IO uint32_t FRQDIV; /* Offset: 0x24 Frequency Divider Control Register */
772 __I uint32_t RESERVE0;
773 __IO uint32_t APBDIV; /* Offset: 0x2C APB Divider Control Register */
774
775} CLK_T;
776
777
778
779/** @addtogroup REG_CLK_BITMASK CLK Bit Mask
780 @{
781 */
782
783/* CLK PWRCON Bit Field Definitions */
784#define CLK_PWRCON_PD_WAIT_CPU_Pos 8 /*!< CLK_T::PWRCON: PD_WAIT_CPU Position */
785#define CLK_PWRCON_PD_WAIT_CPU_Msk (1ul << CLK_PWRCON_PD_WAIT_CPU_Pos) /*!< CLK_T::PWRCON: PD_WAIT_CPU Mask */
786
787#define CLK_PWRCON_PWR_DOWN_EN_Pos 7 /*!< CLK_T::PWRCON: PWR_DOWN_EN Position */
788#define CLK_PWRCON_PWR_DOWN_EN_Msk (1ul << CLK_PWRCON_PWR_DOWN_EN_Pos) /*!< CLK_T::PWRCON: PWR_DOWN_EN Mask */
789
790#define CLK_PWRCON_PD_WU_STS_Pos 6 /*!< CLK_T::PWRCON: PD_WU_STS Position */
791#define CLK_PWRCON_PD_WU_STS_Msk (1ul << CLK_PWRCON_PD_WU_STS_Pos) /*!< CLK_T::PWRCON: PD_WU_STS Mask */
792
793#define CLK_PWRCON_PD_WU_INT_EN_Pos 5 /*!< CLK_T::PWRCON: PD_WU_INT_EN Position */
794#define CLK_PWRCON_PD_WU_INT_EN_Msk (1ul << CLK_PWRCON_PD_WU_INT_EN_Pos) /*!< CLK_T::PWRCON: PD_WU_INT_EN Mask */
795
796#define CLK_PWRCON_PD_WU_DLY_Pos 4 /*!< CLK_T::PWRCON: PD_WU_DLY Position */
797#define CLK_PWRCON_PD_WU_DLY_Msk (1ul << CLK_PWRCON_PD_WU_DLY_Pos) /*!< CLK_T::PWRCON: PD_WU_DLY Mask */
798
799#define CLK_PWRCON_OSC10K_EN_Pos 3 /*!< CLK_T::PWRCON: OSC10K_EN Position */
800#define CLK_PWRCON_OSC10K_EN_Msk (1ul << CLK_PWRCON_OSC10K_EN_Pos) /*!< CLK_T::PWRCON: OSC10K_EN Mask */
801#define CLK_PWRCON_IRC10K_EN_Pos 3 /*!< CLK_T::PWRCON: IRC10K_EN Position */
802#define CLK_PWRCON_IRC10K_EN_Msk (1ul << CLK_PWRCON_IRC10K_EN_Pos) /*!< CLK_T::PWRCON: IRC10K_EN Mask */
803
804#define CLK_PWRCON_OSC22M_EN_Pos 2 /*!< CLK_T::PWRCON: OSC22M_EN Position */
805#define CLK_PWRCON_OSC22M_EN_Msk (1ul << CLK_PWRCON_OSC22M_EN_Pos) /*!< CLK_T::PWRCON: OSC22M_EN Mask */
806#define CLK_PWRCON_IRC22M_EN_Pos 2 /*!< CLK_T::PWRCON: IRC22M_EN Position */
807#define CLK_PWRCON_IRC22M_EN_Msk (1ul << CLK_PWRCON_IRC22M_EN_Pos) /*!< CLK_T::PWRCON: IRC22M_EN Mask */
808
809#define CLK_PWRCON_XTL12M_EN_Pos 0 /*!< CLK_T::PWRCON: XTL12M_EN Position */
810#define CLK_PWRCON_XTL12M_EN_Msk (1ul << CLK_PWRCON_XTL12M_EN_Pos) /*!< CLK_T::PWRCON: XTL12M_EN Mask */
811
812/* CLK AHBCLK Bit Field Definitions */
813#define CLK_AHBCLK_ISP_EN_Pos 2 /*!< CLK_T::AHBCLK: ISP_EN Position */
814#define CLK_AHBCLK_ISP_EN_Msk (1ul << CLK_AHBCLK_ISP_EN_Pos) /*!< CLK_T::AHBCLK: ISP_EN Mask */
815
816#define CLK_AHBCLK_PDMA_EN_Pos 1 /*!< CLK_T::AHBCLK: PDMA_EN Position */
817#define CLK_AHBCLK_PDMA_EN_Msk (1ul << CLK_AHBCLK_PDMA_EN_Pos) /*!< CLK_T::AHBCLK: PDMA_EN Mask */
818
819
820/* CLK APBCLK Bit Field Definitions */
821#define CLK_APBCLK_PS2_EN_Pos 31 /*!< CLK_T::APBCLK: PS2_EN Position */
822#define CLK_APBCLK_PS2_EN_Msk (1ul << CLK_APBCLK_PS2_EN_Pos) /*!< CLK_T::APBCLK: PS2_EN Mask */
823
824#define CLK_APBCLK_I2S_EN_Pos 29 /*!< CLK_T::APBCLK: I2S_EN Position */
825#define CLK_APBCLK_I2S_EN_Msk (1ul << CLK_APBCLK_I2S_EN_Pos) /*!< CLK_T::APBCLK: I2S_EN Mask */
826
827#define CLK_APBCLK_ADC_EN_Pos 28 /*!< CLK_T::APBCLK: ADC_EN Position */
828#define CLK_APBCLK_ADC_EN_Msk (1ul << CLK_APBCLK_ADC_EN_Pos) /*!< CLK_T::APBCLK: ADC_EN Mask */
829
830#define CLK_APBCLK_USBD_EN_Pos 27 /*!< CLK_T::APBCLK: USBD_EN Position */
831#define CLK_APBCLK_USBD_EN_Msk (1ul << CLK_APBCLK_USBD_EN_Pos) /*!< CLK_T::APBCLK: USBD_EN Mask */
832
833#define CLK_APBCLK_PWM23_EN_Pos 21 /*!< CLK_T::APBCLK: PWM23_EN Position */
834#define CLK_APBCLK_PWM23_EN_Msk (1ul << CLK_APBCLK_PWM23_EN_Pos) /*!< CLK_T::APBCLK: PWM23_EN Mask */
835
836#define CLK_APBCLK_PWM01_EN_Pos 20 /*!< CLK_T::APBCLK: PWM01_EN Position */
837#define CLK_APBCLK_PWM01_EN_Msk (1ul << CLK_APBCLK_PWM01_EN_Pos) /*!< CLK_T::APBCLK: PWM01_EN Mask */
838
839#define CLK_APBCLK_UART1_EN_Pos 17 /*!< CLK_T::APBCLK: UART1_EN Position */
840#define CLK_APBCLK_UART1_EN_Msk (1ul << CLK_APBCLK_UART1_EN_Pos) /*!< CLK_T::APBCLK: UART1_EN Mask */
841
842#define CLK_APBCLK_UART0_EN_Pos 16 /*!< CLK_T::APBCLK: UART0_EN Position */
843#define CLK_APBCLK_UART0_EN_Msk (1ul << CLK_APBCLK_UART0_EN_Pos) /*!< CLK_T::APBCLK: UART0_EN Mask */
844
845#define CLK_APBCLK_SPI2_EN_Pos 14 /*!< CLK_T::APBCLK: SPI2_EN Position */
846#define CLK_APBCLK_SPI2_EN_Msk (1ul << CLK_APBCLK_SPI2_EN_Pos) /*!< CLK_T::APBCLK: SPI2_EN Mask */
847
848#define CLK_APBCLK_SPI1_EN_Pos 13 /*!< CLK_T::APBCLK: SPI1_EN Position */
849#define CLK_APBCLK_SPI1_EN_Msk (1ul << CLK_APBCLK_SPI1_EN_Pos) /*!< CLK_T::APBCLK: SPI1_EN Mask */
850
851#define CLK_APBCLK_SPI0_EN_Pos 12 /*!< CLK_T::APBCLK: SPI0_EN Position */
852#define CLK_APBCLK_SPI0_EN_Msk (1ul << CLK_APBCLK_SPI0_EN_Pos) /*!< CLK_T::APBCLK: SPI0_EN Mask */
853
854#define CLK_APBCLK_I2C1_EN_Pos 9 /*!< CLK_T::APBCLK: I2C1_EN Position */
855#define CLK_APBCLK_I2C1_EN_Msk (1ul << CLK_APBCLK_I2C1_EN_Pos) /*!< CLK_T::APBCLK: I2C1_EN Mask */
856
857#define CLK_APBCLK_I2C0_EN_Pos 8 /*!< CLK_T::APBCLK: I2C0_EN_ Position */
858#define CLK_APBCLK_I2C0_EN_Msk (1ul << CLK_APBCLK_I2C0_EN_Pos) /*!< CLK_T::APBCLK: I2C0_EN_ Mask */
859
860#define CLK_APBCLK_FDIV_EN_Pos 6 /*!< CLK_T::APBCLK: FDIV_EN Position */
861#define CLK_APBCLK_FDIV_EN_Msk (1ul << CLK_APBCLK_FDIV_EN_Pos) /*!< CLK_T::APBCLK: FDIV_EN Mask */
862
863#define CLK_APBCLK_TMR3_EN_Pos 5 /*!< CLK_T::APBCLK: TMR3_EN Position */
864#define CLK_APBCLK_TMR3_EN_Msk (1ul << CLK_APBCLK_TMR3_EN_Pos) /*!< CLK_T::APBCLK: TMR3_EN Mask */
865
866#define CLK_APBCLK_TMR2_EN_Pos 4 /*!< CLK_T::APBCLK: TMR2_EN Position */
867#define CLK_APBCLK_TMR2_EN_Msk (1ul << CLK_APBCLK_TMR2_EN_Pos) /*!< CLK_T::APBCLK: TMR2_EN Mask */
868
869#define CLK_APBCLK_TMR1_EN_Pos 3 /*!< CLK_T::APBCLK: TMR1_EN Position */
870#define CLK_APBCLK_TMR1_EN_Msk (1ul << CLK_APBCLK_TMR1_EN_Pos) /*!< CLK_T::APBCLK: TMR1_EN Mask */
871
872#define CLK_APBCLK_TMR0_EN_Pos 2 /*!< CLK_T::APBCLK: TMR0_EN Position */
873#define CLK_APBCLK_TMR0_EN_Msk (1ul << CLK_APBCLK_TMR0_EN_Pos) /*!< CLK_T::APBCLK: TMR0_EN Mask */
874
875#define CLK_APBCLK_WDT_EN_Pos 0 /*!< CLK_T::APBCLK: WDT_EN Position */
876#define CLK_APBCLK_WDT_EN_Msk (1ul << CLK_APBCLK_WDT_EN_Pos) /*!< CLK_T::APBCLK: WDT_EN Mask */
877
878
879/* CLK CLKSTATUS Bit Field Definitions */
880#define CLK_CLKSTATUS_CLK_SW_FAIL_Pos 7 /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Position */
881#define CLK_CLKSTATUS_CLK_SW_FAIL_Msk (1ul << CLK_CLKSTATUS_CLK_SW_FAIL_Pos) /*!< CLK_T::CLKSTATUS: CLK_SW_FAIL Mask */
882
883#define CLK_CLKSTATUS_OSC22M_STB_Pos 4 /*!< CLK_T::CLKSTATUS: OSC22M_STB Position */
884#define CLK_CLKSTATUS_OSC22M_STB_Msk (1ul << CLK_CLKSTATUS_OSC22M_STB_Pos) /*!< CLK_T::CLKSTATUS: OSC22M_STB Mask */
885#define CLK_CLKSTATUS_IRC22M_STB_Pos 4 /*!< CLK_T::CLKSTATUS: IRC22M_STB Position */
886#define CLK_CLKSTATUS_IRC22M_STB_Msk (1ul << CLK_CLKSTATUS_IRC22M_STB_Pos) /*!< CLK_T::CLKSTATUS: IRC22M_STB Mask */
887
888#define CLK_CLKSTATUS_OSC10K_STB_Pos 3 /*!< CLK_T::CLKSTATUS: OSC10K_STB Position */
889#define CLK_CLKSTATUS_OSC10K_STB_Msk (1ul << CLK_CLKSTATUS_OSC10K_STB_Pos) /*!< CLK_T::CLKSTATUS: OSC10K_STB Mask */
890#define CLK_CLKSTATUS_IRC10K_STB_Pos 3 /*!< CLK_T::CLKSTATUS: IRC10K_STB Position */
891#define CLK_CLKSTATUS_IRC10K_STB_Msk (1ul << CLK_CLKSTATUS_IRC10K_STB_Pos) /*!< CLK_T::CLKSTATUS: IRC10K_STB Mask */
892
893#define CLK_CLKSTATUS_PLL_STB_Pos 2 /*!< CLK_T::CLKSTATUS: PLL_STB Position */
894#define CLK_CLKSTATUS_PLL_STB_Msk (1ul << CLK_CLKSTATUS_PLL_STB_Pos) /*!< CLK_T::CLKSTATUS: PLL_STB Mask */
895
896#define CLK_CLKSTATUS_XTL12M_STB_Pos 0 /*!< CLK_T::CLKSTATUS: XTL12M_STB Position */
897#define CLK_CLKSTATUS_XTL12M_STB_Msk (1ul << CLK_CLKSTATUS_XTL12M_STB_Pos) /*!< CLK_T::CLKSTATUS: XTL12M_STB Mask */
898
899/* CLK CLKSEL0 Bit Field Definitions */
900#define CLK_CLKSEL0_STCLK_S_Pos 3 /*!< CLK_T::CLKSEL0: STCLK_S Position */
901#define CLK_CLKSEL0_STCLK_S_Msk (7ul << CLK_CLKSEL0_STCLK_S_Pos) /*!< CLK_T::CLKSEL0: STCLK_S Mask */
902
903#define CLK_CLKSEL0_HCLK_S_Pos 0 /*!< CLK_T::CLKSEL0: HCLK_S Position */
904#define CLK_CLKSEL0_HCLK_S_Msk (7ul << CLK_CLKSEL0_HCLK_S_Pos) /*!< CLK_T::CLKSEL0: HCLK_S Mask */
905
906/* CLK CLKSEL1 Bit Field Definitions */
907#define CLK_CLKSEL1_PWM23_S_Pos 30 /*!< CLK_T::CLKSEL1: PWM23_S Position */
908#define CLK_CLKSEL1_PWM23_S_Msk (3ul << CLK_CLKSEL1_PWM23_S_Pos) /*!< CLK_T::CLKSEL1: PWM23_S Mask */
909
910#define CLK_CLKSEL1_PWM01_S_Pos 28 /*!< CLK_T::CLKSEL1: PWM01_S Position */
911#define CLK_CLKSEL1_PWM01_S_Msk (3ul << CLK_CLKSEL1_PWM01_S_Pos) /*!< CLK_T::CLKSEL1: PWM01_S Mask */
912
913#define CLK_CLKSEL1_UART_S_Pos 24 /*!< CLK_T::CLKSEL1: UART_S Position */
914#define CLK_CLKSEL1_UART_S_Msk (3ul << CLK_CLKSEL1_UART_S_Pos) /*!< CLK_T::CLKSEL1: UART_S Mask */
915
916#define CLK_CLKSEL1_TMR3_S_Pos 20 /*!< CLK_T::CLKSEL1: TMR3_S Position */
917#define CLK_CLKSEL1_TMR3_S_Msk (7ul << CLK_CLKSEL1_TMR3_S_Pos) /*!< CLK_T::CLKSEL1: TMR3_S Mask */
918
919#define CLK_CLKSEL1_TMR2_S_Pos 16 /*!< CLK_T::CLKSEL1: TMR2_S Position */
920#define CLK_CLKSEL1_TMR2_S_Msk (7ul << CLK_CLKSEL1_TMR2_S_Pos) /*!< CLK_T::CLKSEL1: TMR2_S Mask */
921
922#define CLK_CLKSEL1_TMR1_S_Pos 12 /*!< CLK_T::CLKSEL1: TMR1_S Position */
923#define CLK_CLKSEL1_TMR1_S_Msk (7ul << CLK_CLKSEL1_TMR1_S_Pos) /*!< CLK_T::CLKSEL1: TMR1_S Mask */
924
925#define CLK_CLKSEL1_TMR0_S_Pos 8 /*!< CLK_T::CLKSEL1: TMR0_S Position */
926#define CLK_CLKSEL1_TMR0_S_Msk (7ul << CLK_CLKSEL1_TMR0_S_Pos) /*!< CLK_T::CLKSEL1: TMR0_S Mask */
927
928#define CLK_CLKSEL1_SPI2_S_Pos 6 /*!< CLK_T::CLKSEL1: SPI2_S Position */
929#define CLK_CLKSEL1_SPI2_S_Msk (1ul << CLK_CLKSEL1_SPI2_S_Pos) /*!< CLK_T::CLKSEL1: SPI2_S Mask */
930
931#define CLK_CLKSEL1_SPI1_S_Pos 5 /*!< CLK_T::CLKSEL1: SPI1_S Position */
932#define CLK_CLKSEL1_SPI1_S_Msk (1ul << CLK_CLKSEL1_SPI1_S_Pos) /*!< CLK_T::CLKSEL1: SPI1_S Mask */
933
934#define CLK_CLKSEL1_SPI0_S_Pos 4 /*!< CLK_T::CLKSEL1: SPI0_S Position */
935#define CLK_CLKSEL1_SPI0_S_Msk (1ul << CLK_CLKSEL1_SPI0_S_Pos) /*!< CLK_T::CLKSEL1: SPI0_S Mask */
936
937#define CLK_CLKSEL1_ADC_S_Pos 2 /*!< CLK_T::CLKSEL1: ADC_S Position */
938#define CLK_CLKSEL1_ADC_S_Msk (3ul << CLK_CLKSEL1_ADC_S_Pos) /*!< CLK_T::CLKSEL1: ADC_S Mask */
939
940#define CLK_CLKSEL1_WDT_S_Pos 0 /*!< CLK_T::CLKSEL1: WDT_S Position */
941#define CLK_CLKSEL1_WDT_S_Msk (3ul << CLK_CLKSEL1_WDT_S_Pos) /*!< CLK_T::CLKSEL1: WDT_S Mask */
942
943/* CLK CLKSEL2 Bit Field Definitions */
944#define CLK_CLKSEL2_WWDT_S_Pos 16 /*!< CLK_T::CLKSEL2: WWDT_S Position */
945#define CLK_CLKSEL2_WWDT_S_Msk (3ul << CLK_CLKSEL2_WWDT_S_Pos) /*!< CLK_T::CLKSEL2: WWDT_S Mask */
946
947#define CLK_CLKSEL2_PWM23_S_E_Pos 9 /*!< CLK_T::CLKSEL2: PWM23_S_E Position */
948#define CLK_CLKSEL2_PWM23_S_E_Msk (1ul << CLK_CLKSEL2_PWM23_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM23_S_E Mask */
949#define CLK_CLKSEL2_PWM23_S_EXT_Pos 9 /*!< CLK_T::CLKSEL2: PWM23_S_EXT Position */
950#define CLK_CLKSEL2_PWM23_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM23_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM23_S_EXT Mask */
951
952#define CLK_CLKSEL2_PWM01_S_E_Pos 8 /*!< CLK_T::CLKSEL2: PWM01_S_E Position */
953#define CLK_CLKSEL2_PWM01_S_E_Msk (1ul << CLK_CLKSEL2_PWM01_S_E_Pos) /*!< CLK_T::CLKSEL2: PWM01_S_E Mask */
954#define CLK_CLKSEL2_PWM01_S_EXT_Pos 8 /*!< CLK_T::CLKSEL2: PWM01_S_EXT Position */
955#define CLK_CLKSEL2_PWM01_S_EXT_Msk (1ul << CLK_CLKSEL2_PWM01_S_EXT_Pos) /*!< CLK_T::CLKSEL2: PWM01_S_EXT Mask */
956
957#define CLK_CLKSEL2_FRQDIV_S_Pos 2 /*!< CLK_T::CLKSEL2: FRQDIV_S Position */
958#define CLK_CLKSEL2_FRQDIV_S_Msk (3ul << CLK_CLKSEL2_FRQDIV_S_Pos) /*!< CLK_T::CLKSEL2: FRQDIV_S Mask */
959
960#define CLK_CLKSEL2_I2S_S_Pos 0 /*!< CLK_T::CLKSEL2: I2S_S Position */
961#define CLK_CLKSEL2_I2S_S_Msk (3ul << CLK_CLKSEL2_I2S_S_Pos) /*!< CLK_T::CLKSEL2: I2S_S Mask */
962
963/* CLK CLKDIV Bit Field Definitions */
964#define CLK_CLKDIV_ADC_N_Pos 16 /*!< CLK_T::CLKDIV: ADC_N Position */
965#define CLK_CLKDIV_ADC_N_Msk (0xFFul << CLK_CLKDIV_ADC_N_Pos) /*!< CLK_T::CLKDIV: ADC_N Mask */
966
967#define CLK_CLKDIV_UART_N_Pos 8 /*!< CLK_T::CLKDIV: UART_N Position */
968#define CLK_CLKDIV_UART_N_Msk (0xFul << CLK_CLKDIV_UART_N_Pos) /*!< CLK_T::CLKDIV: UART_N Mask */
969
970#define CLK_CLKDIV_USB_N_Pos 4 /*!< CLK_T::CLKDIV: USB_N Position */
971#define CLK_CLKDIV_USB_N_Msk (0xFul << CLK_CLKDIV_USB_N_Pos) /*!< CLK_T::CLKDIV: USB_N Mask */
972
973#define CLK_CLKDIV_HCLK_N_Pos 0 /*!< CLK_T::CLKDIV: HCLK_N Position */
974#define CLK_CLKDIV_HCLK_N_Msk (0xFul << CLK_CLKDIV_HCLK_N_Pos) /*!< CLK_T::CLKDIV: HCLK_N Mask */
975
976/* CLK PLLCON Bit Field Definitions */
977#define CLK_PLLCON_PLL_SRC_Pos 19 /*!< CLK_T::PLLCON: PLL_SRC Position */
978#define CLK_PLLCON_PLL_SRC_Msk (1ul << CLK_PLLCON_PLL_SRC_Pos) /*!< CLK_T::PLLCON: PLL_SRC Mask */
979
980#define CLK_PLLCON_OE_Pos 18 /*!< CLK_T::PLLCON: PLL_SRC Position */
981#define CLK_PLLCON_OE_Msk (1ul << CLK_PLLCON_OE_Pos) /*!< CLK_T::PLLCON: PLL_SRC Mask */
982
983#define CLK_PLLCON_BP_Pos 17 /*!< CLK_T::PLLCON: OE Position */
984#define CLK_PLLCON_BP_Msk (1ul << CLK_PLLCON_BP_Pos) /*!< CLK_T::PLLCON: OE Mask */
985
986#define CLK_PLLCON_PD_Pos 16 /*!< CLK_T::PLLCON: PD Position */
987#define CLK_PLLCON_PD_Msk (1ul << CLK_PLLCON_PD_Pos) /*!< CLK_T::PLLCON: PD Mask */
988
989#define CLK_PLLCON_OUT_DV_Pos 14 /*!< CLK_T::PLLCON: OUT_DV Position */
990#define CLK_PLLCON_OUT_DV_Msk (3ul << CLK_PLLCON_OUT_DV_Pos) /*!< CLK_T::PLLCON: OUT_DV Mask */
991
992#define CLK_PLLCON_IN_DV_Pos 9 /*!< CLK_T::PLLCON: IN_DV Position */
993#define CLK_PLLCON_IN_DV_Msk (0x1Ful << CLK_PLLCON_IN_DV_Pos) /*!< CLK_T::PLLCON: IN_DV Mask */
994
995#define CLK_PLLCON_FB_DV_Pos 0 /*!< CLK_T::PLLCON: FB_DV Position */
996#define CLK_PLLCON_FB_DV_Msk (0x1FFul << CLK_PLLCON_FB_DV_Pos) /*!< CLK_T::PLLCON: FB_DV Mask */
997
998/* CLK FRQDIV Bit Field Definitions */
999#define CLK_FRQDIV_DIVIDER_EN_Pos 4 /*!< CLK_T::FRQDIV: DIVIDER_EN Position */
1000#define CLK_FRQDIV_DIVIDER_EN_Msk (1ul << CLK_FRQDIV_DIVIDER_EN_Pos) /*!< CLK_T::FRQDIV: DIVIDER_EN Mask */
1001
1002#define CLK_FRQDIV_FSEL_Pos 0 /*!< CLK_T::FRQDIV: FRQDIV_FSEL Position */
1003#define CLK_FRQDIV_FSEL_Msk (0xFul << CLK_FRQDIV_FSEL_Pos) /*!< CLK_T::FRQDIV: FRQDIV_FSEL Mask */
1004
1005/* CLK APBDIV Bit Field Definitions */
1006#define CLK_APBDIV_APBDIV_Pos 0 /*!< CLK_T::APBDIV: APBDIV Position */
1007#define CLK_APBDIV_APBDIV_Msk (1ul << CLK_APBDIV_APBDIV_Pos) /*!< CLK_T::APBDIV: APBDIV Mask */
1008/*@}*/ /* end of group REG_CLK_BITMASK */
1009/*@}*/ /* end of group REG_CLK */
1010
1011
1012/*----------------------------- Cyclic Redundancy Check (CRC) Controller -----------------------------*/
1013/** @addtogroup REG_CRC Cyclic Redundancy Check Controller (CRC)
1014 Memory Mapped Structure for Cyclic Redundancy Check
1015 @{
1016 */
1017
1018typedef struct
1019{
1020
1021
1022/**
1023 * @var CRC_T::CTL
1024 * Offset: 0x00 CRC Control Register
1025 * ---------------------------------------------------------------------------------------------------
1026 * |Bits |Field |Descriptions
1027 * | :----: | :----: | :---- |
1028 * |[0] |CRCCEN |CRC Channel Enable
1029 * | | |0 = No effect.
1030 * | | |1 = CRC operation Enabled.
1031 * | | |Note1: When operating in CRC DMA mode (TRIG_EN (CRC_CTL[23]) = 1), if user clears this bit, the DMA operation will be continuous until all CRC DMA operation is done, and the TRIG_EN (CRC_CTL[23]) bit will keep 1until all CRC DMA operation done.
1032 * | | |But in this case, the CRC_BLKD_IF (CRC_DMAISR[1])flag will inactive, user can read CRC checksum result only if TRIG_EN (CRC_CTL[23]) clears to 0.
1033 * | | |Note2: When operating in CRC DMA mode (TRIG_EN (CRC_CTL[23]) = 1), if user wants to stop the transfer immediately, user can write 1 to CRC_RST (CRC_CTL [1]) bit to stop the transmission.
1034 * |[1] |CRC_RST |CRC Engine Reset
1035 * | | |0 = No effect.
1036 * | | |1 = Reset the internal CRC state machine and internal buffer.
1037 * | | |The others contents of CRC_CTL register will not be cleared.
1038 * | | |This bit will be cleared automatically.
1039 * | | |Note: When operated in CPU PIO mode, setting this bit will reload the initial seed value (CRC_SEED register).
1040 * |[23] |TRIG_EN |Trigger Enable
1041 * | | |This bit is used to trigger the CRC DMA transfer.
1042 * | | |0 = No effect.
1043 * | | |1 = CRC DMA data read or write transfer Enabled.
1044 * | | |Note1: If this bit asserts which indicates the CRC engine operation in CRC DMA mode, do not fill in any data in CRC_WDATA register.
1045 * | | |Note2: When CRC DMA transfer completed, this bit will be cleared automatically.
1046 * | | |Note3: If the bus error occurs when CRC DMA transfer data, all CRC DMA transfer will be stopped.
1047 * | | |Software must reset all DMA channel before trigger DMA again.
1048 * |[24] |WDATA_RVS |Write Data Order Reverse
1049 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_WDATA register.
1050 * | | |0 = Bit order reverse for CRC write data in Disabled.
1051 * | | |1 = Bit order reverse for CRC write data in Enabled (per byre).
1052 * | | |Note: If the write data is 0xAABBCCDD, the bit order reverse for CRC write data in is 0x55DD33BB
1053 * |[25] |CHECKSUM_RVS|Checksum Reverse
1054 * | | |This bit is used to enable the bit order reverse function for write data value in CRC_CHECKSUM register.
1055 * | | |0 = Bit order reverse for CRC checksum Disabled.
1056 * | | |1 = Bit order reverse for CRC checksum Enabled.
1057 * | | |Note: If the checksum result is 0XDD7B0F2E, the bit order reverse for CRC checksum is 0x74F0DEBB
1058 * |[26] |WDATA_COM |Write Data 1's Complement
1059 * | | |This bit is used to enable the 1's complement function for write data value in CRC_WDATA register.
1060 * | | |0 = 1's complement for CRC write data in Disabled.
1061 * | | |1 = 1's complement for CRC write data in Enabled.
1062 * |[27] |CHECKSUM_COM|Checksum 1's Complement
1063 * | | |This bit is used to enable the 1's complement function for checksum result in CRC_CHECKSUM register.
1064 * | | |0 = 1's complement for CRC checksum Disabled.
1065 * | | |1 = 1's complement for CRC checksum Enabled.
1066 * |[29:28] |CPU_WDLEN |CPU Write Data Length
1067 * | | |This field indicates the CPU write data length only when operating in CPU PIO mode.
1068 * | | |00 = The write data length is 8-bit mode.
1069 * | | |01 = The write data length is 16-bit mode.
1070 * | | |10 = The write data length is 32-bit mode.
1071 * | | |11 = Reserved.
1072 * | | |Note1: This field is only valid when operating in CPU PIO mode.
1073 * | | |Note2: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
1074 * |[31:30] |CRC_MODE |CRC Polynomial Mode
1075 * | | |This field indicates the CRC operation polynomial mode.
1076 * | | |00 = CRC-CCITT Polynomial Mode.
1077 * | | |01 = CRC-8 Polynomial Mode.
1078 * | | |10 = CRC-16 Polynomial Mode.
1079 * | | |11 = CRC-32 Polynomial Mode.
1080 * @var CRC_T::DMASAR
1081 * Offset: 0x04 CRC DMA Source Address Register
1082 * ---------------------------------------------------------------------------------------------------
1083 * |Bits |Field |Descriptions
1084 * | :----: | :----: | :---- |
1085 * |[31:0] |CRC_DMASAR|CRC DMA Transfer Source Address Register
1086 * | | |This field indicates a 32-bit source address of CRC DMA.
1087 * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR).
1088 * | | |Note: The source address must be word alignment
1089 * @var CRC_T::DMABCR
1090 * Offset: 0x0C CRC DMA Transfer Byte Count Register
1091 * ---------------------------------------------------------------------------------------------------
1092 * |Bits |Field |Descriptions
1093 * | :----: | :----: | :---- |
1094 * |[15:0] |CRC_DMABCR|CRC DMA Transfer Byte Count Register
1095 * | | |This field indicates a 16-bit total transfer byte count number of CRC DMA
1096 * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR).
1097 * @var CRC_T::DMACSAR
1098 * Offset: 0x14 CRC DMA Current Source Address Register
1099 * ---------------------------------------------------------------------------------------------------
1100 * |Bits |Field |Descriptions
1101 * | :----: | :----: | :---- |
1102 * |[31:0] |CRC_DMACSAR|CRC DMA Current Source Address Register (Read Only)
1103 * | | |This field indicates the current source address where the CRC DMA transfer just occurs.
1104 * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR).
1105 * @var CRC_T::DMACBCR
1106 * Offset: 0x1C CRC DMA Current Transfer Byte Count Register
1107 * ---------------------------------------------------------------------------------------------------
1108 * |Bits |Field |Descriptions
1109 * | :----: | :----: | :---- |
1110 * |[15:0] |CRC_DMACBCR|CRC DMA Current Remained Byte Count Register (Read Only)
1111 * | | |This field indicates the current remained byte count of CRC DMA.
1112 * | | |(CRC_DMASAR + CRC_DMABCR) = (CRC_DMACSAR + CRC_DMACBCR).
1113 * | | |Note: Setting CRC_RST (CRC_CTL[1]) bit to 1 will clear this register value.
1114 * @var CRC_T::DMAIER
1115 * Offset: 0x20 CRC DMA Interrupt Enable Register
1116 * ---------------------------------------------------------------------------------------------------
1117 * |Bits |Field |Descriptions
1118 * | :----: | :----: | :---- |
1119 * |[0] |CRC_TABORT_IE|CRC DMA Read/Write Target Abort Interrupt Enable
1120 * | | |Enable this bit will generate the CRC DMA Target Abort interrupt signal while CRC_TARBOT_IF (CRC_DMAISR[0]) bit is set to 1.
1121 * | | |0 = Target abort interrupt generation Disabled during CRC DMA transfer.
1122 * | | |1 = Target abort interrupt generation Enabled during CRC DMA transfer.
1123 * |[1] |CRC_BLKD_IE|CRC DMA Block Transfer Done Interrupt Enable
1124 * | | |Enable this bit will generate the CRC DMA Transfer Done interrupt signal while CRC_BLKD_IF (CRC_DMAISR[1]) bit is set to 1.
1125 * | | |0 = Interrupt generator Disabled when CRC DMA transfer done.
1126 * | | |1 = Interrupt generator Enabled when CRC DMA transfer done.
1127 * @var CRC_T::DMAISR
1128 * Offset: 0x24 CRC DMA Interrupt Status Register
1129 * ---------------------------------------------------------------------------------------------------
1130 * |Bits |Field |Descriptions
1131 * | :----: | :----: | :---- |
1132 * |[0] |CRC_TABORT_IF|CRC DMA Read/Write Target Abort Interrupt Flag
1133 * | | |This bit indicates that CRC bus has error or not during CRC DMA transfer.
1134 * | | |0 = No bus error response received during CRC DMA transfer.
1135 * | | |1 = Bus error response received during CRC DMA transfer.
1136 * | | |It is cleared by writing 1 to it through software.
1137 * | | |Note: The bit filed indicate bus master received error response or not.
1138 * | | |If bus master received error response, it means that CRC transfer target abort is happened.
1139 * | | |DMA will stop transfer and respond this event to software then CRC state machine goes to IDLE state.
1140 * | | |When target abort occurred, software must reset DMA before transfer those data again.
1141 * |[1] |CRC_BLKD_IF|CRC DMA Block Transfer Done Interrupt Flag
1142 * | | |This bit indicates that CRC DMA transfer has finished or not.
1143 * | | |0 = Not finished if TRIG_EN (CRC_CTL[23]) bit has enabled.
1144 * | | |1 = CRC transfer done if TRIG_EN (CRC_CTL[23]) bit has enabled.
1145 * | | |It is cleared by writing 1 to it through software.
1146 * | | |(When CRC DMA transfer done, TRIG_EN (CRC_CTL[23]) bit will be cleared automatically)
1147 * @var CRC_T::WDATA
1148 * Offset: 0x80 CRC Write Data Register
1149 * ---------------------------------------------------------------------------------------------------
1150 * |Bits |Field |Descriptions
1151 * | :----: | :----: | :---- |
1152 * |[31:0] |CRC_WDATA |CRC Write Data Register
1153 * | | |When operating in CPU PIO mode, software can write data to this field to perform CRC operation.
1154 * | | |When operating in DMA mode, this field indicates the DMA read data from memory and cannot be written.
1155 * | | |Note: When the write data length is 8-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [7:0] bits; if the write data length is 16-bit mode, the valid data in CRC_WDATA register is only CRC_WDATA [15:0].
1156 * @var CRC_T::SEED
1157 * Offset: 0x84 CRC Seed Register
1158 * ---------------------------------------------------------------------------------------------------
1159 * |Bits |Field |Descriptions
1160 * | :----: | :----: | :---- |
1161 * |[31:0] |CRC_SEED |CRC Seed Register
1162 * | | |This field indicates the CRC seed value.
1163 * @var CRC_T::CHECKSUM
1164 * Offset: 0x88 CRC Checksum Register
1165 * ---------------------------------------------------------------------------------------------------
1166 * |Bits |Field |Descriptions
1167 * | :----: | :----: | :---- |
1168 * |[31:0] |CRC_CHECKSUM|CRC Checksum Register
1169 * | | |This fields indicates the CRC checksum result
1170 */
1171
1172 __IO uint32_t CTL; /* Offset: 0x00 CRC Control Register */
1173 __IO uint32_t DMASAR; /* Offset: 0x04 CRC DMA Source Address Register */
1174 __I uint32_t RESERVED0;
1175 __IO uint32_t DMABCR; /* Offset: 0x0C CRC DMA Transfer Byte Count Register */
1176 __I uint32_t RESERVED1;
1177 __I uint32_t DMACSAR; /* Offset: 0x14 CRC DMA Current Source Address Register */
1178 __I uint32_t RESERVED2;
1179 __I uint32_t DMACBCR; /* Offset: 0x1C CRC DMA Current Transfer Byte Count Register */
1180 __IO uint32_t DMAIER; /* Offset: 0x20 CRC DMA Interrupt Enable Register */
1181 __IO uint32_t DMAISR; /* Offset: 0x24 CRC DMA Interrupt Status Register */
1182 __I uint32_t RESERVED3[22];
1183 __IO uint32_t WDATA; /* Offset: 0x80 CRC Write Data Register */
1184 __IO uint32_t SEED; /* Offset: 0x84 CRC Seed Register */
1185 __I uint32_t CHECKSUM; /* Offset: 0x88 CRC Checksum Register */
1186
1187} CRC_T;
1188
1189
1190
1191/** @addtogroup REG_CRC_BITMASK CRC Bit Mask
1192 @{
1193 */
1194
1195/* CRC CTL Bit Field Definitions */
1196#define CRC_CTL_CRC_MODE_Pos 30 /*!< CRC_T::CTL: CRC_MODE Position */
1197#define CRC_CTL_CRC_MODE_Msk (0x3ul << CRC_CTL_CRC_MODE_Pos) /*!< CRC_T::CTL: CRC_MODE Mask */
1198
1199#define CRC_CTL_CPU_WDLEN_Pos 28 /*!< CRC_T::CTL: CPU_WDLEN Position */
1200#define CRC_CTL_CPU_WDLEN_Msk (0x3ul << CRC_CTL_CPU_WDLEN_Pos) /*!< CRC_T::CTL: CPU_WDLEN Mask */
1201
1202#define CRC_CTL_CHECKSUM_COM_Pos 27 /*!< CRC_T::CTL: CHECKSUM_COM Position */
1203#define CRC_CTL_CHECKSUM_COM_Msk (1ul << CRC_CTL_CHECKSUM_COM_Pos) /*!< CRC_T::CTL: CHECKSUM_COM Mask */
1204
1205#define CRC_CTL_WDATA_COM_Pos 26 /*!< CRC_T::CTL: WDATA_COM Position */
1206#define CRC_CTL_WDATA_COM_Msk (1ul << CRC_CTL_WDATA_COM_Pos) /*!< CRC_T::CTL: WDATA_COM Mask */
1207
1208#define CRC_CTL_CHECKSUM_RVS_Pos 25 /*!< CRC_T::CTL: CHECKSUM_RVS Position */
1209#define CRC_CTL_CHECKSUM_RVS_Msk (1ul << CRC_CTL_CHECKSUM_RVS_Pos) /*!< CRC_T::CTL: CHECKSUM_RVS Mask */
1210
1211#define CRC_CTL_WDATA_RVS_Pos 24 /*!< CRC_T::CTL: WDATA_RVS Position */
1212#define CRC_CTL_WDATA_RVS_Msk (1ul << CRC_CTL_WDATA_RVS_Pos) /*!< CRC_T::CTL: WDATA_RVS Mask */
1213
1214#define CRC_CTL_TRIG_EN_Pos 23 /*!< CRC_T::CTL: TRIG_EN Position */
1215#define CRC_CTL_TRIG_EN_Msk (1ul << CRC_CTL_TRIG_EN_Pos) /*!< CRC_T::CTL: TRIG_EN Mask */
1216
1217#define CRC_CTL_CRC_RST_Pos 1 /*!< CRC_T::CTL: CRC_RST Position */
1218#define CRC_CTL_CRC_RST_Msk (1ul << CRC_CTL_CRC_RST_Pos) /*!< CRC_T::CTL: CRC_RST Mask */
1219
1220#define CRC_CTL_CRCCEN_Pos 0 /*!< CRC_T::CTL: CRCCEN Position */
1221#define CRC_CTL_CRCCEN_Msk (1ul << CRC_CTL_CRCCEN_Pos) /*!< CRC_T::CTL: CRCCEN Mask */
1222
1223/* CRC DMASAR Bit Field Definitions */
1224#define CRC_DMASAR_CRC_DMASAR_Pos 0 /*!< CRC_T::DMASAR: CRC_DMASAR Position */
1225#define CRC_DMASAR_CRC_DMASAR_Msk (0xFFFFFFFFul << CRC_DMASAR_CRC_DMASAR_Pos) /*!< CRC_T::DMASAR: CRC_DMASAR Mask */
1226
1227/* CRC DMABCR Bit Field Definitions */
1228#define CRC_DMABCR_CRC_DMABCR_Pos 0 /*!< CRC_T::DMABCR: CRC_DMABCR Position */
1229#define CRC_DMABCR_CRC_DMABCR_Msk (0xFFFFul << CRC_DMABCR_CRC_DMABCR_Pos) /*!< CRC_T::DMABCR: CRC_DMABCR Mask */
1230
1231/* CRC DMACSAR Bit Field Definitions */
1232#define CRC_DMACSAR_CRC_DMACSAR_Pos 0 /*!< CRC_T::DMACSAR: CRC_DMACSAR Position */
1233#define CRC_DMACSAR_CRC_DMACSAR_Msk (0xFFFFFFFFul << CRC_DMACSAR_CRC_DMACSAR_Pos) /*!< CRC_T::DMACSAR: CRC_DMACSAR Mask */
1234
1235/* CRC DMACBCR Bit Field Definitions */
1236#define CRC_DMACBCR_CRC_DMACBCR_Pos 0 /*!< CRC_T::DMACBCR: DMACBCR Position */
1237#define CRC_DMACBCR_CRC_DMACBCR_Msk (0xFFFFul << CRC_DMACBCR_CRC_DMACBCR_Pos) /*!< CRC_T::DMACBCR: DMACBCR Mask */
1238
1239/* CRC DMAIER Bit Field Definitions */
1240#define CRC_DMAIER_CRC_BLKD_IE_Pos 1 /*!< CRC_T::DMAIER: CRC_BLKD_IE Position */
1241#define CRC_DMAIER_CRC_BLKD_IE_Msk (1ul << CRC_DMAIER_CRC_BLKD_IE_Pos) /*!< CRC_T::DMAIER: CRC_BLKD_IE Mask */
1242
1243#define CRC_DMAIER_CRC_TABORT_IE_Pos 0 /*!< CRC_T::DMAIER: CRC_TABORT_IE Position */
1244#define CRC_DMAIER_CRC_TABORT_IE_Msk (1ul << CRC_DMAIER_CRC_TABORT_IE_Pos) /*!< CRC_T::DMAIER: CRC_TABORT_IE Mask */
1245
1246/* CRC DMAISR Bit Field Definitions */
1247#define CRC_DMAISR_CRC_BLKD_IF_Pos 1 /*!< CRC_T::DMAISR: CRC_BLKD_IF Position */
1248#define CRC_DMAISR_CRC_BLKD_IF_Msk (1ul << CRC_DMAISR_CRC_BLKD_IF_Pos) /*!< CRC_T::DMAISR: CRC_BLKD_IF Mask */
1249
1250#define CRC_DMAISR_CRC_TABORT_IF_Pos 0 /*!< CRC_T::DMAISR: CRC_TABORT_IF Position */
1251#define CRC_DMAISR_CRC_TABORT_IF_Msk (1ul << CRC_DMAISR_CRC_TABORT_IF_Pos) /*!< CRC_T::DMAISR: CRC_TABORT_IF Mask */
1252
1253/* CRC WDATA Bit Field Definitions */
1254#define CRC_WDATA_CRC_WDATA_Pos 0 /*!< CRC_T::WDATA: CRC_WDATA Position */
1255#define CRC_WDATA_CRC_WDATA_Msk (0xFFFFFFFFul << CRC_WDATA_CRC_WDATA_Pos) /*!< CRC_T::WDATA: CRC_WDATA Mask */
1256
1257/* CRC SEED Bit Field Definitions */
1258#define CRC_SEED_CRC_SEED_Pos 0 /*!< CRC_T::SEED: CRC_SEED Position */
1259#define CRC_SEED_CRC_SEED_Msk (0xFFFFFFFFul << CRC_SEED_CRC_SEED_Pos) /*!< CRC_T::SEED: CRC_SEED Mask */
1260
1261/* CRC CHECKSUM Bit Field Definitions */
1262#define CRC_CHECKSUM_CRC_CHECKSUM_Pos 0 /*!< CRC_T::CHECKSUM: CRC_CHECKSUM Position */
1263#define CRC_CHECKSUM_CRC_CHECKSUM_Msk (0xFFFFFFFFul << CRC_CHECKSUM_CRC_CHECKSUM_Pos) /*!< CRC_T::CHECKSUM: CRC_CHECKSUM Mask */
1264/*@}*/ /* end of group REG_CRC_BITMASK */
1265/*@}*/ /* end of group REG_CRC */
1266
1267/*-------------------------- FLASH Memory Controller -------------------------*/
1268/** @addtogroup REG_FMC Flash Memory Controller (FMC)
1269 Memory Mapped Structure for Flash Memory Controller
1270 @{
1271 */
1272
1273typedef struct
1274{
1275
1276
1277/**
1278 * @var FMC_T::ISPCON
1279 * Offset: 0x00 ISP Control Register
1280 * ---------------------------------------------------------------------------------------------------
1281 * |Bits |Field |Descriptions
1282 * | :----: | :----: | :---- |
1283 * |[0] |ISPEN |ISP Enable
1284 * | | |This bit is protected bit. ISP function enable bit. Set this bit to enable ISP function.
1285 * | | |1 = Enable ISP function
1286 * | | |0 = Disable ISP function
1287 * |[1] |BS |Boot Select
1288 * | | |This bit is protected bit. Set/clear this bit to select next booting from LDROM/APROM,
1289 * | | |respectively. This bit also functions as MCU booting status flag, which can be used to check where
1290 * | | |MCU booted from. This bit is initiated with the inverted value of CBS in Config0 after power-
1291 * | | |on reset; It keeps the same value at other reset.
1292 * | | |1 = boot from LDROM
1293 * | | |0 = boot from APROM
1294 * |[4] |CFGUEN |Config Update Enable
1295 * | | |Writing this bit to 1 enables s/w to update Config value by ISP procedure regardless of program
1296 * | | |code is running in APROM or LDROM.
1297 * | | |1 = Config update enable
1298 * | | |0 = Config update disable
1299 * |[5] |LDUEN |LDROM Update Enable
1300 * | | |LDROM update enable bit.
1301 * | | |1 = LDROM can be updated when the MCU runs in APROM.
1302 * | | |0 = LDROM cannot be updated
1303 * |[6] |ISPFF |ISP Fail Flag
1304 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
1305 * | | |(1) APROM writes to itself.
1306 * | | |(2) LDROM writes to itself.
1307 * | | |(3) Destination address is illegal, such as over an available range.
1308 * | | |Write 1 to clear.
1309 * |[7] |SWRST |Software Reset
1310 * | | |Writing 1 to this bit to start software reset.
1311 * | | |It is cleared by hardware after reset is finished.
1312 * @var FMC_T::ISPADR
1313 * Offset: 0x04 ISP Address Register
1314 * ---------------------------------------------------------------------------------------------------
1315 * |Bits |Field |Descriptions
1316 * | :----: | :----: | :---- |
1317 * |[31:0] |ISPADR |ISP Address
1318 * | | |it supports word program only. ISPARD[1:0] must be kept 2'b00 for ISP operation.
1319 * @var FMC_T::ISPDAT
1320 * Offset: 0x08 ISP Data Register
1321 * ---------------------------------------------------------------------------------------------------
1322 * |Bits |Field |Descriptions
1323 * | :----: | :----: | :---- |
1324 * |[31:0] |ISPDAT |ISP Data
1325 * | | |Write data to this register before ISP program operation
1326 * | | |Read data from this register after ISP read operation
1327 * @var FMC_T::ISPCMD
1328 * Offset: 0x0C ISP Command Register
1329 * ---------------------------------------------------------------------------------------------------
1330 * |Bits |Field |Descriptions
1331 * | :----: | :----: | :---- |
1332 * |[5:0] |ISPCMD |ISP Command
1333 * | | |ISP command table is shown below:
1334 * | | |0x00 = Read.
1335 * | | |0x21 = Program.
1336 * | | |0x22 = Page Erase.
1337 * @var FMC_T::ISPTRG
1338 * Offset: 0x10 ISP Trigger Control Register
1339 * ---------------------------------------------------------------------------------------------------
1340 * |Bits |Field |Descriptions
1341 * | :----: | :----: | :---- |
1342 * |[0] |ISPGO |ISP start trigger
1343 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware automatically when ISP
1344 * | | |operation is finish.
1345 * | | |1 = ISP is on going
1346 * | | |0 = ISP done
1347 * @var FMC_T::DFBADR
1348 * Offset: 0x14 Data Flash Base Address Register
1349 * ---------------------------------------------------------------------------------------------------
1350 * |Bits |Field |Descriptions
1351 * | :----: | :----: | :---- |
1352 * |[31:0] |DFBA |Data Flash Base Address
1353 * | | |This register indicates data flash start address.
1354 * | | |It is a read only register.
1355 * | | |For 8/16/32/64kB flash memory device, the data flash size is 4kB and it start address is fixed at
1356 * | | |0x01F000 by hardware internally.
1357 * @var FMC_T::FATCON
1358 * Offset: 0x18 Flash Access Time Control Register
1359 * ---------------------------------------------------------------------------------------------------
1360 * |Bits |Field |Descriptions
1361 * | :----: | :----: | :---- |
1362 * |[0] |FPSEN |Flash Power Save Enable
1363 * | | |If CPU clock is slower than 24 MHz, then s/w can enable flash power saving function.
1364 * | | |1 = Enable flash power saving
1365 * | | |0 = Disable flash power saving
1366 * |[4] |L_SPEED |Flash Low Speed Mode Enable
1367 * | | |1 = Flash access always no wait state (zero wait state)
1368 * | | |0 = Insert wait state while Flash access discontinued address.
1369 * | | |Note: Set this bit only when HCLK <= 25MHz. If HCLK > 25MHz, CPU will fetch wrong
1370 * | | |code and cause fail result.
1371 * @var FMC_T::ISPSTA
1372 * Offset: 0x40 ISP Status Register
1373 * ---------------------------------------------------------------------------------------------------
1374 * |Bits |Field |Descriptions
1375 * | :----: | :----: | :---- |
1376 * |[0] |ISPGO |ISP Start Trigger (Read Only)
1377 * | | |Write 1 to start ISP operation and this bit will be cleared to 0 by hardware
1378 * | | |automatically when ISP operation is finished.
1379 * | | |0 = ISP operation finished.
1380 * | | |1 = ISP operation progressed.
1381 * | | |Note: This bit is the same as ISPTRG bit0
1382 * |[2:1] |CBS |Chip Boot Selection (Read Only)
1383 * | | |This is a mirror of CBS in Config0.
1384 * |[6] |ISPFF |ISP Fail Flag (Write-protection Bit)
1385 * | | |This bit is set by hardware when a triggered ISP meets any of the following conditions:
1386 * | | |(1) APROM writes to itself.
1387 * | | |(2) LDROM writes to itself.
1388 * | | |(3) CONFIG is erased/programmed when CFGUEN is set to 0
1389 * | | |(4) Destination address is illegal, such as over an available range.
1390 * |[20:9] |VECMAP |Vector Page Mapping Address (Read Only)
1391 * | | |The current flash address space 0x0000_0000~0x0000_01FF is mapping to the address
1392 * | | |{VECMAP[11:0], 9'h000} ~ {VECMAP[11:0], 9'h1FF}
1393 */
1394
1395 __IO uint32_t ISPCON; /* Offset: 0x00 ISP Control Register */
1396 __IO uint32_t ISPADR; /* Offset: 0x04 ISP Address Register */
1397 __IO uint32_t ISPDAT; /* Offset: 0x08 ISP Data Register */
1398 __IO uint32_t ISPCMD; /* Offset: 0x0C ISP Command Register */
1399 __IO uint32_t ISPTRG; /* Offset: 0x10 ISP Trigger Control Register */
1400 __I uint32_t DFBADR; /* Offset: 0x14 Data Flash Base Address Register */
1401 __IO uint32_t FATCON; /* Offset: 0x18 Flash Access Time Control Register */
1402 __I uint32_t RESERVED[9];
1403 __IO uint32_t ISPSTA; /* Offset: 0x40 ISP Status Register */
1404
1405} FMC_T;
1406
1407
1408
1409/** @addtogroup REG_FMC_BITMASK FMC Bit Mask
1410 @{
1411 */
1412
1413/* FMC ISPCON Bit Field Definitions */
1414#define FMC_ISPCON_ET_Pos 12 /*!< FMC_T::ISPCON: ET Position */
1415#define FMC_ISPCON_ET_Msk (7ul << FMC_ISPCON_ET_Pos) /*!< FMC_T::ISPCON: ET Mask */
1416
1417#define FMC_ISPCON_PT_Pos 8 /*!< FMC_T::ISPCON: PT Position */
1418#define FMC_ISPCON_PT_Msk (7ul << FMC_ISPCON_PT_Pos) /*!< FMC_T::ISPCON: PT Mask */
1419
1420#define FMC_ISPCON_ISPFF_Pos 6 /*!< FMC_T::ISPCON: ISPFF Position */
1421#define FMC_ISPCON_ISPFF_Msk (1ul << FMC_ISPCON_ISPFF_Pos) /*!< FMC_T::ISPCON: ISPFF Mask */
1422
1423#define FMC_ISPCON_LDUEN_Pos 5 /*!< FMC_T::ISPCON: LDUEN Position */
1424#define FMC_ISPCON_LDUEN_Msk (1ul << FMC_ISPCON_LDUEN_Pos) /*!< FMC_T::ISPCON: LDUEN Mask */
1425
1426#define FMC_ISPCON_CFGUEN_Pos 4 /*!< FMC_T::ISPCON: CFGUEN Position */
1427#define FMC_ISPCON_CFGUEN_Msk (1ul << FMC_ISPCON_CFGUEN_Pos) /*!< FMC_T::ISPCON: CFGUEN Mask */
1428
1429#define FMC_ISPCON_APUEN_Pos 3 /*!< FMC_T::ISPCON: APUEN Position */
1430#define FMC_ISPCON_APUEN_Msk (1ul << FMC_ISPCON_APUEN_Pos) /*!< FMC_T::ISPCON: APUEN Mask */
1431
1432#define FMC_ISPCON_BS_Pos 1 /*!< FMC_T::ISPCON: BS Position */
1433#define FMC_ISPCON_BS_Msk (0x1ul << FMC_ISPCON_BS_Pos) /*!< FMC_T::ISPCON: BS Mask */
1434
1435#define FMC_ISPCON_ISPEN_Pos 0 /*!< FMC_T::ISPCON: ISPEN Position */
1436#define FMC_ISPCON_ISPEN_Msk (1ul << FMC_ISPCON_ISPEN_Pos) /*!< FMC_T::ISPCON: ISPEN Mask */
1437
1438/* FMC ISPADR Bit Field Definitions */
1439#define FMC_ISPADR_ISPADR_Pos 0 /*!< FMC_T::ISPADR: ISPADR Position */
1440#define FMC_ISPADR_ISPADR_Msk (0xFFFFFFFFul << FMC_ISPADR_ISPADR_Pos) /*!< FMC_T::ISPADR: ISPADR Mask */
1441
1442/* FMC ISPADR Bit Field Definitions */
1443#define FMC_ISPDAT_ISPDAT_Pos 0 /*!< FMC_T::ISPDAT: ISPDAT Position */
1444#define FMC_ISPDAT_ISPDAT_Msk (0xFFFFFFFFul << FMC_ISPDAT_ISPDAT_Pos) /*!< FMC_T::ISPDAT: ISPDAT Mask */
1445
1446/* FMC ISPCMD Bit Field Definitions */
1447#define FMC_ISPCMD_FOEN_Pos 5 /*!< FMC_T::ISPCMD: FOEN Position */
1448#define FMC_ISPCMD_FOEN_Msk (1ul << FMC_ISPCMD_FOEN_Pos) /*!< FMC_T::ISPCMD: FOEN Mask */
1449
1450#define FMC_ISPCMD_FCEN_Pos 4 /*!< FMC_T::ISPCMD: FCEN Position */
1451#define FMC_ISPCMD_FCEN_Msk (1ul << FMC_ISPCMD_FCEN_Pos) /*!< FMC_T::ISPCMD: FCEN Mask */
1452
1453#define FMC_ISPCMD_FCTRL_Pos 0 /*!< FMC_T::ISPCMD: FCTRL Position */
1454#define FMC_ISPCMD_FCTRL_Msk (0xFul << FMC_ISPCMD_FCTRL_Pos) /*!< FMC_T::ISPCMD: FCTRL Mask */
1455
1456/* FMC ISPTRG Bit Field Definitions */
1457#define FMC_ISPTRG_ISPGO_Pos 0 /*!< FMC_T::ISPTRG: ISPGO Position */
1458#define FMC_ISPTRG_ISPGO_Msk (1ul << FMC_ISPTRG_ISPGO_Pos) /*!< FMC_T::ISPTRG: ISPGO Mask */
1459
1460/* FMC DFBADR Bit Field Definitions */
1461#define FMC_DFBADR_DFBA_Pos 0 /*!< FMC_T::DFBADR: DFBA Position */
1462#define FMC_DFBADR_DFBA_Msk (0xFFFFFFFFul << FMC_DFBADR_DFBA_Pos) /*!< FMC_T::DFBADR: DFBA Mask */
1463
1464/* FMC FATCON Bit Field Definitions */
1465#define FMC_FATCON_FOMSEL1_Pos 6 /*!< FMC_T::FATCON: FOMSEL1 Position */
1466#define FMC_FATCON_FOMSEL1_Msk (1ul << FMC_FATCON_FOMSEL1_Pos) /*!< FMC_T::FATCON: FOMSEL1 Mask */
1467
1468#define FMC_FATCON_FOMSEL0_Pos 4 /*!< FMC_T::FATCON: FOMSEL0 Position */
1469#define FMC_FATCON_FOMSEL0_Msk (1ul << FMC_FATCON_FOMSEL0_Pos) /*!< FMC_T::FATCON: FOMSEL0 Mask */
1470
1471#define FMC_FATCON_FATS_Pos 1 /*!< FMC_T::FATCON: FATS Position */
1472#define FMC_FATCON_FATS_Msk (7ul << FMC_FATCON_FATS_Pos) /*!< FMC_T::FATCON: FATS Mask */
1473
1474#define FMC_FATCON_FPSEN_Pos 0 /*!< FMC_T::FATCON: FPSEN Position */
1475#define FMC_FATCON_FPSEN_Msk (1ul << FMC_FATCON_FPSEN_Pos) /*!< FMC_T::FATCON: FPSEN Mask */
1476
1477
1478#define FMC_ISPSTA_ISPGO_Pos 0 /*!< FMC_T::ISPSTA: ISPGO Position */
1479#define FMC_ISPSTA_ISPGO_Msk (1ul << FMC_ISPSTA_ISPGO_Pos) /*!< FMC_T::ISPSTA: ISPGO Mask */
1480
1481#define FMC_ISPSTA_CBS_Pos 1 /*!< FMC_T::ISPSTA: CBS Position */
1482#define FMC_ISPSTA_CBS_Msk (0x3ul << FMC_ISPSTA_CBS_Pos) /*!< FMC_T::ISPSTA: CBS Mask */
1483
1484#define FMC_ISPSTA_ISPFF_Pos 6 /*!< FMC_T::ISPSTA: ISPFF Position */
1485#define FMC_ISPSTA_ISPFF_Msk (0x3ul << FMC_ISPSTA_ISPFF_Pos) /*!< FMC_T::ISPSTA: ISPFF Mask */
1486
1487#define FMC_ISPSTA_VECMAP_Pos 9 /*!< FMC_T::ISPSTA: VECMAP Position */
1488#define FMC_ISPSTA_VECMAP_Msk (0xFFFul << FMC_ISPSTA_VECMAP_Pos) /*!< FMC_T::ISPSTA: VECMAP Mask */
1489
1490/*@}*/ /* end of group REG_FMC_BITMASK */
1491/*@}*/ /* end of group REG_FMC */
1492
1493
1494
1495/*--------------------- General Purpose I/O (GPIO) ---------------------*/
1496/** @addtogroup REG_GPIO General Purpose Input/Output Controller (GPIO)
1497 Memory Mapped Structure for General Purpose I/O
1498 @{
1499 */
1500
1501typedef struct
1502{
1503
1504
1505/**
1506 * @var GPIO_T::PMD
1507 * Offset: 0x00/0x40/0x80/0xC0/0x140 GPIO Port [A/B/C/D/F] Pin I/O Mode Control
1508 * ---------------------------------------------------------------------------------------------------
1509 * |Bits |Field |Descriptions
1510 * | :----: | :----: | :---- |
1511 * |[2n+1:2n]|PMDn |GPIOx I/O Pin[n] Mode Control
1512 * | | |Determine each I/O mode of GPIOx pins.
1513 * | | |00 = GPIO port [n] pin is in Input mode.
1514 * | | |01 = GPIO port [n] pin is in Push-pull Output mode.
1515 * | | |10 = GPIO port [n] pin is in Open-drain Output mode.
1516 * | | |11 = GPIO port [n] pin is in Quasi-bidirectional mode.
1517 * | | |Note:
1518 * | | |n = 10~15 for port A. Others are reserved.
1519 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1520 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1521 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1522 * | | |n = 0~3 for port F. Others are reserved.
1523 * @var GPIO_T::OFFD
1524 * Offset: 0x04/0x44/0x84/0xC4/0x144 GPIO Port [A/B/C/D/F] Pin Digital Input Path Disable Control
1525 * ---------------------------------------------------------------------------------------------------
1526 * |Bits |Field |Descriptions
1527 * | :----: | :----: | :---- |
1528 * |[[n+16]]|OFFDn |GPIOx Pin[n] Digital Input Path Disable Control
1529 * | | |Each of these bits is used to control if the digital input path of corresponding GPIO pin is disabled.
1530 * | | |If input is analog signal, users can disable GPIO digital input path to avoid current leakage.
1531 * | | |0 = I/O digital input path Enabled.
1532 * | | |1 = I/O digital input path Disabled (digital input tied to low).
1533 * | | |Note:
1534 * | | |n = 10~15 for port A. Others are reserved.
1535 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1536 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1537 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1538 * | | |n = 0~3 for port F. Others are reserved.
1539 * @var GPIO_T::DOUT
1540 * Offset: 0x08/0x48/0x88/0xC8/0x148 GPIO Port [A/B/C/D/F] Data Output Value
1541 * ---------------------------------------------------------------------------------------------------
1542 * |Bits |Field |Descriptions
1543 * | :----: | :----: | :---- |
1544 * |[n] |DOUTn |GPIOx Pin[n] Output Value
1545 * | | |Each of these bits controls the status of a Px.n pin when the Px.n is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1546 * | | |0 = Px.n will drive Low if the Px.n pin is configured as Push-pull output, Open-drain output or Quasi-bidirectional mode.
1547 * | | |1 = Px.n will drive High if the Px.n pin is configured as Push-pull output or Quasi-bidirectional mode.
1548 * | | |Note:
1549 * | | |n = 10~15 for port A. Others are reserved.
1550 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1551 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1552 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1553 * | | |n = 0~3 for port F. Others are reserved.
1554 * @var GPIO_T::DMASK
1555 * Offset: 0x0C/0x4C/0x8C/0xCC/0x14C GPIO Port [A/B/C/D/F] Data Output Write Mask
1556 * ---------------------------------------------------------------------------------------------------
1557 * |Bits |Field |Descriptions
1558 * | :----: | :----: | :---- |
1559 * |[n] |DMASKn |GPIOx Pin[n] Data Output Write Mask
1560 * | | |These bits are used to protect the corresponding DOUT (GPIOx_DOUT[n]) bit.
1561 * | | |When the DATMSK (GPIOx _DATMSK[n]) bit is set to 1, the corresponding DOUT (GPIOx _DOUT[n]) bit is protected.
1562 * | | |If the write signal is masked, writing data to the protect bit is ignored.
1563 * | | |0 = Corresponding DOUT (GPIOx_DOUT[n]) bit can be updated.
1564 * | | |1 = Corresponding DOUT (GPIOx_DOUT[n]) bit protected.
1565 * | | |Note1: This function only protect corresponding DOUT (GPIOx_DOUT[n]) bit, and will not protect corresponding bit control register GPIOxn_DOUT.
1566 * | | |Note2:
1567 * | | |n = 10~15 for port A. Others are reserved.
1568 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1569 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1570 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1571 * | | |n = 0~3 for port F. Others are reserved.
1572 * @var GPIO_T::PIN
1573 * Offset: 0x10/0x50/0x90/0xD0/0x150 GPIO Port [A/B/C/D/F] Pin Value
1574 * ---------------------------------------------------------------------------------------------------
1575 * |Bits |Field |Descriptions
1576 * | :----: | :----: | :---- |
1577 * |[n] |PINn |GPIOx Pin[n] Pin Values
1578 * | | |Each bit of the register reflects the actual status of the respective GPIO pin.
1579 * | | |If the bit is 1, it indicates the corresponding pin status is high, else the pin status is low.
1580 * | | |Note:
1581 * | | |n = 10~15 for port A. Others are reserved.
1582 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1583 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1584 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1585 * | | |n = 0~3 for port F. Others are reserved.
1586 * @var GPIO_T::DBEN
1587 * Offset: 0x14/0x54/0x94/0xD4/0x154 GPIO Port [A/B/C/D/F] De-bounce Enable
1588 * ---------------------------------------------------------------------------------------------------
1589 * |Bits |Field |Descriptions
1590 * | :----: | :----: | :---- |
1591 * |[n] |DBENn |GPIOx Pin[n] Input Signal De-Bounce Enable
1592 * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
1593 * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
1594 * | | |The de-bounce clock source is controlled by DBCLKSRC (DBNCECON [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (DBNCECON [3:0]).
1595 * | | |0 = Px.n de-bounce function Disabled.
1596 * | | |1 = Px.n de-bounce function Enabled.
1597 * | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1598 * | | |Note:
1599 * | | |n = 10~15 for port A. Others are reserved.
1600 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1601 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1602 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1603 * | | |n = 0~3 for port F. Others are reserved.
1604 * @var GPIO_T::IMD
1605 * Offset: 0x18/0x58/0x98/0xD8/0x158 GPIO Port [A/B/C/D/F] Interrupt Mode Control
1606 * ---------------------------------------------------------------------------------------------------
1607 * |Bits |Field |Descriptions
1608 * | :----: | :----: | :---- |
1609 * |[n] |IMDn |GPIOx Pin[n] Edge Or Level Detection Interrupt Control
1610 * | | |IMD[n] is used to control the interrupt is by level trigger or by edge trigger.
1611 * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
1612 * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
1613 * | | |0 = Edge trigger interrupt.
1614 * | | |1 = Level trigger interrupt.
1615 * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers GPIOx_IEN.
1616 * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
1617 * | | |The de-bounce function is valid only for edge triggered interrupt. If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
1618 * | | |Note:
1619 * | | |n = 10~15 for port A. Others are reserved.
1620 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1621 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1622 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1623 * | | |n = 0~3 for port F. Others are reserved.
1624 * @var GPIO_T::IEN
1625 * Offset: 0x1C/0x5C/0x9C/0xDC/0x15C GPIO Port [A/B/C/D/F] Interrupt Enable
1626 * ---------------------------------------------------------------------------------------------------
1627 * |Bits |Field |Descriptions
1628 * | :----: | :----: | :---- |
1629 * |[n] |IF_ENn |GPIOx Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
1630 * | | |The IF_EN (GPIOx_IEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
1631 * | | |When setting the IF_EN (Px_IEN[n]) bit to 1 :
1632 * | | |If the interrupt is level trigger (IMD (GPIOx_IMD[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
1633 * | | |If the interrupt is edge trigger(IMD (GPIOx_IMD[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from high to low.
1634 * | | |0 = Px.n level low or high to low interrupt Disabled.
1635 * | | |1 = Px.n level low or high to low interrupt Enabled.
1636 * | | |Note:
1637 * | | |n = 10~15 for port A. Others are reserved.
1638 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1639 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1640 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1641 * | | |n = 0~3 for port F. Others are reserved.
1642 * |[n+16] |IR_ENn |GPIOx Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
1643 * | | |The IR_EN (GPIOx_IEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin. Set bit to 1 also enable the pin wake-up function.
1644 * | | |When setting the IR_EN (GPIOx_IEN[n+16]) bit to 1 :
1645 * | | |If the interrupt is level trigger (IMD (GPIOx_IMD[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
1646 * | | |If the interrupt is edge trigger (IMD (Px_IMD[n]) bit is set to 0), the input Px.n pin will generate the interrupt while this pin state changed from low to high.
1647 * | | |0 = Px.n level high or low to high interrupt Disabled.
1648 * | | |1 = Px.n level high or low to high interrupt Enabled.
1649 * | | |Note:
1650 * | | |n = 10~15 for port A. Others are reserved.
1651 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1652 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1653 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1654 * | | |n = 0~3 for port F. Others are reserved.
1655 * @var GPIO_T::ISRC
1656 * Offset: 0x20/0x60/0xA0/0xE0/0x160 GPIO Port [A/B/C/D/F] Interrupt Source Flag
1657 * ---------------------------------------------------------------------------------------------------
1658 * |Bits |Field |Descriptions
1659 * | :----: | :----: | :---- |
1660 * |[n] |ISRCn |GPIOx Pin[n] Interrupt Source Flag
1661 * | | |Read :
1662 * | | |0 = No interrupt at Px.n.
1663 * | | |1 = Px.n generates an interrupt.
1664 * | | |Write :
1665 * | | |0= No action.
1666 * | | |1= Clear the corresponding pending interrupt.
1667 * | | |Note:
1668 * | | |n = 10~15 for port A. Others are reserved.
1669 * | | |n = 0~10, 12~15 for port B. Others are reserved.
1670 * | | |n = 0~5, 8~13 for port C. Others are reserved.
1671 * | | |n = 0~5, 8~11 for port D. Others are reserved.
1672 * | | |n = 0~3 for port F. Others are reserved.
1673 */
1674
1675 __IO uint32_t PMD; /* Offset: 0x00/0x40/0x80/0xC0/0x140 GPIO Port [A/B/C/D/F] Pin I/O Mode Control */
1676 __IO uint32_t OFFD; /* Offset: 0x04/0x44/0x84/0xC4/0x144 GPIO Port [A/B/C/D/F] Pin Digital Input Path Disable Control */
1677 __IO uint32_t DOUT; /* Offset: 0x08/0x48/0x88/0xC8/0x148 GPIO Port [A/B/C/D/F] Data Output Value */
1678 __IO uint32_t DMASK; /* Offset: 0x0C/0x4C/0x8C/0xCC/0x14C GPIO Port [A/B/C/D/F] Data Output Write Mask */
1679 __I uint32_t PIN; /* Offset: 0x10/0x50/0x90/0xD0/0x150 GPIO Port [A/B/C/D/F] Pin Value */
1680 __IO uint32_t DBEN; /* Offset: 0x14/0x54/0x94/0xD4/0x154 GPIO Port [A/B/C/D/F] De-bounce Enable */
1681 __IO uint32_t IMD; /* Offset: 0x18/0x58/0x98/0xD8/0x158 GPIO Port [A/B/C/D/F] Interrupt Mode Control */
1682 __IO uint32_t IEN; /* Offset: 0x1C/0x5C/0x9C/0xDC/0x15C GPIO Port [A/B/C/D/F] Interrupt Enable */
1683 __IO uint32_t ISRC; /* Offset: 0x20/0x60/0xA0/0xE0/0x160 GPIO Port [A/B/C/D/F] Interrupt Source Flag */
1684
1685} GPIO_T;
1686
1687
1688
1689
1690typedef struct
1691{
1692
1693
1694/**
1695 * @var GPIO_DBNCECON_T::DBNCECON
1696 * Offset: 0x180 External Interrupt De-bounce Control
1697 * ---------------------------------------------------------------------------------------------------
1698 * |Bits |Field |Descriptions
1699 * | :----: | :----: | :---- |
1700 * |[3:0] |DBCLKSEL |De-Bounce Sampling Cycle Selection
1701 * | | |0000 = Sample interrupt input once per 1 clocks.
1702 * | | |0001 = Sample interrupt input once per 2 clocks.
1703 * | | |0010 = Sample interrupt input once per 4 clocks.
1704 * | | |0011 = Sample interrupt input once per 8 clocks.
1705 * | | |0100 = Sample interrupt input once per 16 clocks.
1706 * | | |0101 = Sample interrupt input once per 32 clocks.
1707 * | | |0110 = Sample interrupt input once per 64 clocks.
1708 * | | |0111 = Sample interrupt input once per 128 clocks.
1709 * | | |1000 = Sample interrupt input once per 256 clocks.
1710 * | | |1001 = Sample interrupt input once per 2*256 clocks.
1711 * | | |1010 = Sample interrupt input once per 4*256clocks.
1712 * | | |1011 = Sample interrupt input once per 8*256 clocks.
1713 * | | |1100 = Sample interrupt input once per 16*256 clocks.
1714 * | | |1101 = Sample interrupt input once per 32*256 clocks.
1715 * | | |1110 = Sample interrupt input once per 64*256 clocks.
1716 * | | |1111 = Sample interrupt input once per 128*256 clocks.
1717 * |[4] |DBCLKSRC |De-Bounce Counter Clock Source Selection
1718 * | | |0 = De-bounce counter clock source is the HCLK.
1719 * | | |1 = De-bounce counter clock source is the internal 10 kHz low speed oscillator.
1720 * |[5] |ICLK_ON |Interrupt Clock On Mode
1721 * | | |0 = Edge detection circuit is active only if I/O pin corresponding GPIOx_IEN bit is set to 1.
1722 * | | |1 = All I/O pins edge detection circuit is always active after reset.
1723 * | | |It is recommended to turn off this bit to save system power if no special application concern.
1724 */
1725
1726 __IO uint32_t DBNCECON; /* Offset: 0x180 External Interrupt De-bounce Control */
1727
1728} GPIO_DBNCECON_T;
1729
1730
1731
1732/** @addtogroup REG_GPIO_BITMASK GPIO Bit Mask
1733 @{
1734 */
1735
1736/* GPIO PMD Bit Field Definitions */
1737#define GPIO_PMD_PMD15_Pos 30 /*!< GPIO_T::PMD: PMD15 Position */
1738#define GPIO_PMD_PMD15_Msk (0x3ul << GPIO_PMD_PMD15_Pos) /*!< GPIO_T::PMD: PMD15 Mask */
1739
1740#define GPIO_PMD_PMD14_Pos 28 /*!< GPIO_T::PMD: PMD14 Position */
1741#define GPIO_PMD_PMD14_Msk (0x3ul << GPIO_PMD_PMD14_Pos) /*!< GPIO_T::PMD: PMD14 Mask */
1742
1743#define GPIO_PMD_PMD13_Pos 26 /*!< GPIO_T::PMD: PMD13 Position */
1744#define GPIO_PMD_PMD13_Msk (0x3ul << GPIO_PMD_PMD13_Pos) /*!< GPIO_T::PMD: PMD13 Mask */
1745
1746#define GPIO_PMD_PMD12_Pos 24 /*!< GPIO_T::PMD: PMD12 Position */
1747#define GPIO_PMD_PMD12_Msk (0x3ul << GPIO_PMD_PMD12_Pos) /*!< GPIO_T::PMD: PMD12 Mask */
1748
1749#define GPIO_PMD_PMD11_Pos 22 /*!< GPIO_T::PMD: PMD11 Position */
1750#define GPIO_PMD_PMD11_Msk (0x3ul << GPIO_PMD_PMD11_Pos) /*!< GPIO_T::PMD: PMD11 Mask */
1751
1752#define GPIO_PMD_PMD10_Pos 20 /*!< GPIO_T::PMD: PMD10 Position */
1753#define GPIO_PMD_PMD10_Msk (0x3ul << GPIO_PMD_PMD10_Pos) /*!< GPIO_T::PMD: PMD10 Mask */
1754
1755#define GPIO_PMD_PMD9_Pos 18 /*!< GPIO_T::PMD: PMD9 Position */
1756#define GPIO_PMD_PMD9_Msk (0x3ul << GPIO_PMD_PMD9_Pos) /*!< GPIO_T::PMD: PMD9 Mask */
1757
1758#define GPIO_PMD_PMD8_Pos 16 /*!< GPIO_T::PMD: PMD8 Position */
1759#define GPIO_PMD_PMD8_Msk (0x3ul << GPIO_PMD_PMD8_Pos) /*!< GPIO_T::PMD: PMD8 Mask */
1760
1761#define GPIO_PMD_PMD7_Pos 14 /*!< GPIO_T::PMD: PMD7 Position */
1762#define GPIO_PMD_PMD7_Msk (0x3ul << GPIO_PMD_PMD7_Pos) /*!< GPIO_T::PMD: PMD7 Mask */
1763
1764#define GPIO_PMD_PMD6_Pos 12 /*!< GPIO_T::PMD: PMD6 Position */
1765#define GPIO_PMD_PMD6_Msk (0x3ul << GPIO_PMD_PMD6_Pos) /*!< GPIO_T::PMD: PMD6 Mask */
1766
1767#define GPIO_PMD_PMD5_Pos 10 /*!< GPIO_T::PMD: PMD5 Position */
1768#define GPIO_PMD_PMD5_Msk (0x3ul << GPIO_PMD_PMD5_Pos) /*!< GPIO_T::PMD: PMD5 Mask */
1769
1770#define GPIO_PMD_PMD4_Pos 8 /*!< GPIO_T::PMD: PMD4 Position */
1771#define GPIO_PMD_PMD4_Msk (0x3ul << GPIO_PMD_PMD4_Pos) /*!< GPIO_T::PMD: PMD4 Mask */
1772
1773#define GPIO_PMD_PMD3_Pos 6 /*!< GPIO_T::PMD: PMD3 Position */
1774#define GPIO_PMD_PMD3_Msk (0x3ul << GPIO_PMD_PMD3_Pos) /*!< GPIO_T::PMD: PMD3 Mask */
1775
1776#define GPIO_PMD_PMD2_Pos 4 /*!< GPIO_T::PMD: PMD2 Position */
1777#define GPIO_PMD_PMD2_Msk (0x3ul << GPIO_PMD_PMD2_Pos) /*!< GPIO_T::PMD: PMD2 Mask */
1778
1779#define GPIO_PMD_PMD1_Pos 2 /*!< GPIO_T::PMD: PMD1 Position */
1780#define GPIO_PMD_PMD1_Msk (0x3ul << GPIO_PMD_PMD1_Pos) /*!< GPIO_T::PMD: PMD1 Mask */
1781
1782#define GPIO_PMD_PMD0_Pos 0 /*!< GPIO_T::PMD: PMD0 Position */
1783#define GPIO_PMD_PMD0_Msk (0x3ul << GPIO_PMD_PMD0_Pos) /*!< GPIO_T::PMD: PMD0 Mask */
1784
1785/* GPIO OFFD Bit Field Definitions */
1786#define GPIO_OFFD_OFFD_Pos 16 /*!< GPIO_T::OFFD: OFFD Position */
1787#define GPIO_OFFD_OFFD_Msk (0xFFFFul << GPIO_OFFD_OFFD_Pos) /*!< GPIO_T::OFFD: OFFD Mask */
1788
1789/* GPIO DOUT Bit Field Definitions */
1790#define GPIO_DOUT_DOUT_Pos 0 /*!< GPIO_T::DOUT: DOUT Position */
1791#define GPIO_DOUT_DOUT_Msk (0xFFFFul << GPIO_DOUT_DOUT_Pos) /*!< GPIO_T::DOUT: DOUT Mask */
1792
1793/* GPIO DMASK Bit Field Definitions */
1794#define GPIO_DMASK_DMASK_Pos 0 /*!< GPIO_T::DMASK: DMASK Position */
1795#define GPIO_DMASK_DMASK_Msk (0xFFFFul << GPIO_DMASK_DMASK_Pos) /*!< GPIO_T::DMASK: DMASK Mask */
1796
1797/* GPIO PIN Bit Field Definitions */
1798#define GPIO_PIN_PIN_Pos 0 /*!< GPIO_T::PIN: PIN Position */
1799#define GPIO_PIN_PIN_Msk (0xFFFFul << GPIO_PIN_PIN_Pos) /*!< GPIO_T::PIN: PIN Mask */
1800
1801/* GPIO DBEN Bit Field Definitions */
1802#define GPIO_DBEN_DBEN_Pos 0 /*!< GPIO_T::DBEN: DBEN Position */
1803#define GPIO_DBEN_DBEN_Msk (0xFFFFul << GPIO_DBEN_DBEN_Pos) /*!< GPIO_T::DBEN: DBEN Mask */
1804
1805/* GPIO IMD Bit Field Definitions */
1806#define GPIO_IMD_IMD_Pos 0 /*!< GPIO_T::IMD: IMD Position */
1807#define GPIO_IMD_IMD_Msk (0xFFFFul << GPIO_IMD_IMD_Pos) /*!< GPIO_T::IMD: IMD Mask */
1808
1809/* GPIO IEN Bit Field Definitions */
1810#define GPIO_IEN_IR_EN_Pos 16 /*!< GPIO_T::IEN: IR_EN Position */
1811#define GPIO_IEN_IR_EN_Msk (0xFFFFul << GPIO_IEN_IR_EN_Pos) /*!< GPIO_T::IEN: IR_EN Mask */
1812
1813#define GPIO_IEN_IF_EN_Pos 0 /*!< GPIO_T::IEN: IF_EN Position */
1814#define GPIO_IEN_IF_EN_Msk (0xFFFFul << GPIO_IEN_IF_EN_Pos) /*!< GPIO_T::IEN: IF_EN Mask */
1815
1816/* GPIO ISRC Bit Field Definitions */
1817#define GPIO_ISRC_ISRC_Pos 0 /*!< GPIO_T::ISRC: ISRC Position */
1818#define GPIO_ISRC_ISRC_Msk (0xFFFFul << GPIO_ISRC_ISRC_Pos) /*!< GPIO_T::ISRC: ISRC Mask */
1819
1820/* GPIO DBNCECON Bit Field Definitions */
1821#define GPIO_DBNCECON_ICLK_ON_Pos 5 /*!< GPIO_DBNCECON_T::DBNCECON: ICLK_ON Position */
1822#define GPIO_DBNCECON_ICLK_ON_Msk (1ul << GPIO_DBNCECON_ICLK_ON_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: ICLK_ON Mask */
1823
1824#define GPIO_DBNCECON_DBCLKSRC_Pos 4 /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSRC Position */
1825#define GPIO_DBNCECON_DBCLKSRC_Msk (1ul << GPIO_DBNCECON_DBCLKSRC_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSRC Mask */
1826
1827#define GPIO_DBNCECON_DBCLKSEL_Pos 0 /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSEL Position */
1828#define GPIO_DBNCECON_DBCLKSEL_Msk (0xFul << GPIO_DBNCECON_DBCLKSEL_Pos) /*!< GPIO_DBNCECON_T::DBNCECON: DBCLKSEL Mask */
1829/*@}*/ /* end of group REG_GPIO_BITMASK */
1830/*@}*/ /* end of group REG_GPIO */
1831
1832/*------------------------------ I2C Controller ------------------------------*/
1833/** @addtogroup REG_I2C Inter-IC Bus Controller (I2C)
1834 Memory Mapped Structure for I2C Serial Interface Controller
1835 @{
1836 */
1837
1838typedef struct
1839{
1840
1841
1842/**
1843 * @var I2C_T::I2CON
1844 * Offset: 0x00 I2C Control Register
1845 * ---------------------------------------------------------------------------------------------------
1846 * |Bits |Field |Descriptions
1847 * | :----: | :----: | :---- |
1848 * |[2] |AA |Assert Acknowledge Control
1849 * | | |When AA =1 prior to address or data received, an acknowledged (low level to I2Cn_SDA) will be returned during the acknowledge clock pulse on the I2Cn_SCL line when 1.) A slave is acknowledging the address sent from master, 2.) The receiver devices are acknowledging the data sent by transmitter.
1850 * | | |When AA=0 prior to address or data received, a Not acknowledged (high level to I2Cn_SDA) will be returned during the acknowledge clock pulse on the I2Cn_SCL line.
1851 * |[3] |SI |I2C Interrupt Flag
1852 * | | |When a new I2C state is present in the I2CSTATUS register, the SI flag is set by hardware, and if bit EI (I2CON [7]) is set, the I2C interrupt is requested.
1853 * | | |SI must be cleared by software.
1854 * | | |Clear SI by writing 1 to this bit.
1855 * |[4] |STO |I2C STOP Control
1856 * | | |In Master mode, setting STO to transmit a STOP condition to bus then I2C hardware will check the bus condition if a STOP condition is detected this bit will be cleared by hardware automatically.
1857 * | | |In a slave mode, setting STO resets I2C hardware to the defined "not addressed" slave mode.
1858 * | | |This means it is NO LONGER in the slave receiver mode to receive data from the master transmit device.
1859 * |[5] |STA |I2C START Control
1860 * | | |Setting STA to logic 1 to enter Master mode, the I2C hardware sends a START or repeat START condition to bus when the bus is free.
1861 * |[6] |ENS1 |I2C Controller Enable
1862 * | | |0 = Disabled.
1863 * | | |1 = Enabled.
1864 * | | |Set to enable I2C serial function controller.
1865 * | | |When ENS1=1 the I2C serial function enables.
1866 * | | |The multi-function pin function of I2Cn_SDA and I2Cn_SCL must set to I2C function first.
1867 * |[7] |EI |Enable Interrupt
1868 * | | |0 = I2C interrupt Disabled.
1869 * | | |1 = I2C interrupt Enabled.
1870 * @var I2C_T::I2CADDR0
1871 * Offset: 0x04 I2C Slave Address Register0
1872 * ---------------------------------------------------------------------------------------------------
1873 * |Bits |Field |Descriptions
1874 * | :----: | :----: | :---- |
1875 * |[0] |GC |General Call Function
1876 * | | |0 = General Call Function Disabled.
1877 * | | |1 = General Call Function Enabled.
1878 * |[7:1] |I2CADDR |I2C Address Register
1879 * | | |The content of this register is irrelevant when I2C is in Master mode.
1880 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
1881 * | | |The I2C hardware will react if either of the address is matched.
1882 * @var I2C_T::I2CDAT
1883 * Offset: 0x08 I2C Data Register
1884 * ---------------------------------------------------------------------------------------------------
1885 * |Bits |Field |Descriptions
1886 * | :----: | :----: | :---- |
1887 * |[7:0] |I2CDAT |I2C Data Register
1888 * | | |Bit [7:0] is located with the 8-bit transferred data of I2C serial port.
1889 * @var I2C_T::I2CSTATUS
1890 * Offset: 0x0C I2C Status Register
1891 * ---------------------------------------------------------------------------------------------------
1892 * |Bits |Field |Descriptions
1893 * | :----: | :----: | :---- |
1894 * |[7:0] |I2CSTATUS |I2C Status Register
1895 * | | |The status register of I2C:
1896 * | | |The three least significant bits are always 0.
1897 * | | |The five most significant bits contain the status code.
1898 * | | |There are 26 possible status codes.
1899 * | | |When I2CSTATUS contains F8H, no serial interrupt is requested.
1900 * | | |All other I2CSTATUS values correspond to defined I2C states.
1901 * | | |When each of these states is entered, a status interrupt is requested (SI = 1).
1902 * | | |A valid status code is present in I2CSTATUS one cycle after SI is set by hardware and is still present one cycle after SI has been reset by software.
1903 * | | |In addition, states 00H stands for a Bus Error.
1904 * | | |A Bus Error occurs when a START or STOP condition is present at an illegal position in the formation frame.
1905 * | | |Example of illegal position are during the serial transfer of an address byte, a data byte or an acknowledge bit.
1906 * @var I2C_T::I2CLK
1907 * Offset: 0x10 I2C Clock Divided Register
1908 * ---------------------------------------------------------------------------------------------------
1909 * |Bits |Field |Descriptions
1910 * | :----: | :----: | :---- |
1911 * |[7:0] |I2CLK |I2C clock divided Register
1912 * | | |The I2C clock rate bits: Data Baud Rate of I2C = (system clock) / (4x (I2CLK+1)).
1913 * | | |Note: The minimum value of I2CLK is 4.
1914 * @var I2C_T::I2CTOC
1915 * Offset: 0x14 I2C Time-out Counter Register
1916 * ---------------------------------------------------------------------------------------------------
1917 * |Bits |Field |Descriptions
1918 * | :----: | :----: | :---- |
1919 * |[0] |TIF |Time-out Flag
1920 * | | |This bit is set by H/W when I2C time-out happened and it can interrupt CPU if I2C interrupt enable bit (EI) is set to 1.
1921 * | | |Note: Write 1 to clear this bit.
1922 * |[1] |DIV4 |Time-out Counter Input Clock Divided by 4
1923 * | | |0 = Disabled.
1924 * | | |1 = Enabled.
1925 * | | |When Enabled, The time-out period is extend 4 times.
1926 * |[2] |ENTI |Time-out Counter Enable/Disable
1927 * | | |0 = Disabled.
1928 * | | |1 = Enabled.
1929 * | | |When Enabled, the 14-bit time-out counter will start counting when SI is clear.
1930 * | | |Setting flag SI to high will reset counter and re-start up counting after SI is cleared.
1931 * @var I2C_T::I2CADDR1
1932 * Offset: 0x18 I2C Slave Address Register1
1933 * ---------------------------------------------------------------------------------------------------
1934 * |Bits |Field |Descriptions
1935 * | :----: | :----: | :---- |
1936 * |[0] |GC |General Call Function
1937 * | | |0 = General Call Function Disabled.
1938 * | | |1 = General Call Function Enabled.
1939 * |[7:1] |I2CADDR |I2C Address Register
1940 * | | |The content of this register is irrelevant when I2C is in Master mode.
1941 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
1942 * | | |The I2C hardware will react if either of the address is matched.
1943 * @var I2C_T::I2CADDR2
1944 * Offset: 0x1C I2C Slave Address Register2
1945 * ---------------------------------------------------------------------------------------------------
1946 * |Bits |Field |Descriptions
1947 * | :----: | :----: | :---- |
1948 * |[0] |GC |General Call Function
1949 * | | |0 = General Call Function Disabled.
1950 * | | |1 = General Call Function Enabled.
1951 * |[7:1] |I2CADDR |I2C Address Register
1952 * | | |The content of this register is irrelevant when I2C is in Master mode.
1953 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
1954 * | | |The I2C hardware will react if either of the address is matched.
1955 * @var I2C_T::I2CADDR3
1956 * Offset: 0x20 I2C Slave Address Register3
1957 * ---------------------------------------------------------------------------------------------------
1958 * |Bits |Field |Descriptions
1959 * | :----: | :----: | :---- |
1960 * |[0] |GC |General Call Function
1961 * | | |0 = General Call Function Disabled.
1962 * | | |1 = General Call Function Enabled.
1963 * |[7:1] |I2CADDR |I2C Address Register
1964 * | | |The content of this register is irrelevant when I2C is in Master mode.
1965 * | | |In the slave mode, the seven most significant bits must be loaded with the chip's own address.
1966 * | | |The I2C hardware will react if either of the address is matched.
1967 * @var I2C_T::I2CADM0
1968 * Offset: 0x24 I2C Slave Address Mask Register0
1969 * ---------------------------------------------------------------------------------------------------
1970 * |Bits |Field |Descriptions
1971 * | :----: | :----: | :---- |
1972 * |[7:1] |I2CADM |I2C Address Mask Register
1973 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1974 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
1975 * | | |I2C bus controllers support multiple address recognition with four address mask register.
1976 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
1977 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1978 * @var I2C_T::I2CADM1
1979 * Offset: 0x28 I2C Slave Address Mask Register1
1980 * ---------------------------------------------------------------------------------------------------
1981 * |Bits |Field |Descriptions
1982 * | :----: | :----: | :---- |
1983 * |[7:1] |I2CADM |I2C Address Mask Register
1984 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1985 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
1986 * | | |I2C bus controllers support multiple address recognition with four address mask register.
1987 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
1988 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
1989 * @var I2C_T::I2CADM2
1990 * Offset: 0x2C I2C Slave Address Mask Register2
1991 * ---------------------------------------------------------------------------------------------------
1992 * |Bits |Field |Descriptions
1993 * | :----: | :----: | :---- |
1994 * |[7:1] |I2CADM |I2C Address Mask Register
1995 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
1996 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
1997 * | | |I2C bus controllers support multiple address recognition with four address mask register.
1998 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
1999 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
2000 * @var I2C_T::I2CADM3
2001 * Offset: 0x30 I2C Slave Address Mask Register3
2002 * ---------------------------------------------------------------------------------------------------
2003 * |Bits |Field |Descriptions
2004 * | :----: | :----: | :---- |
2005 * |[7:1] |I2CADM |I2C Address Mask Register
2006 * | | |0 = Mask Disabled (the received corresponding register bit should be exact the same as address register.).
2007 * | | |1 = Mask Enabled (the received corresponding address bit is don't care.).
2008 * | | |I2C bus controllers support multiple address recognition with four address mask register.
2009 * | | |When the bit in the address mask register is set to one, it means the received corresponding address bit is don't-care.
2010 * | | |If the bit is set to zero, that means the received corresponding register bit should be exact the same as address register.
2011 * @var I2C_T::I2CWKUPCON
2012 * Offset: 0x3C I2C Wake-up Control Register
2013 * ---------------------------------------------------------------------------------------------------
2014 * |Bits |Field |Descriptions
2015 * | :----: | :----: | :---- |
2016 * |[0] |WKUPEN |I2C Wake-up Enable
2017 * | | |0 = I2C wake-up function Disabled.
2018 * | | |1= I2C wake-up function Enabled.
2019 * @var I2C_T::I2CWKUPSTS
2020 * Offset: 0x40 I2C Wake-up Status Register
2021 * ---------------------------------------------------------------------------------------------------
2022 * |Bits |Field |Descriptions
2023 * | :----: | :----: | :---- |
2024 * |[0] |WKUPIF |I2C Wake-up Flag
2025 * | | |When chip is woken up from Power-down mode by I2C, this bit is set to 1.
2026 * | | |Software can write 1 to clear this bit.
2027 */
2028
2029 __IO uint32_t I2CON; /* Offset: 0x00 I2C Control Register */
2030 __IO uint32_t I2CADDR0; /* Offset: 0x04 I2C Slave Address Register0 */
2031 __IO uint32_t I2CDAT; /* Offset: 0x08 I2C Data Register */
2032 __I uint32_t I2CSTATUS; /* Offset: 0x0C I2C Status Register */
2033 __IO uint32_t I2CLK; /* Offset: 0x10 I2C Clock Divided Register */
2034 __IO uint32_t I2CTOC; /* Offset: 0x14 I2C Time-out Counter Register */
2035 __IO uint32_t I2CADDR1; /* Offset: 0x18 I2C Slave Address Register1 */
2036 __IO uint32_t I2CADDR2; /* Offset: 0x1C I2C Slave Address Register2 */
2037 __IO uint32_t I2CADDR3; /* Offset: 0x20 I2C Slave Address Register3 */
2038 __IO uint32_t I2CADM0; /* Offset: 0x24 I2C Slave Address Mask Register0 */
2039 __IO uint32_t I2CADM1; /* Offset: 0x28 I2C Slave Address Mask Register1 */
2040 __IO uint32_t I2CADM2; /* Offset: 0x2C I2C Slave Address Mask Register2 */
2041 __IO uint32_t I2CADM3; /* Offset: 0x30 I2C Slave Address Mask Register3 */
2042 __I uint32_t RESERVED[2];
2043 __IO uint32_t I2CWKUPCON; /* Offset: 0x3C I2C Wake-up Control Register */
2044 __IO uint32_t I2CWKUPSTS; /* Offset: 0x40 I2C Wake-up Status Register */
2045
2046} I2C_T;
2047
2048
2049
2050/** @addtogroup REG_I2C_BITMASK I2C Bit Mask
2051 @{
2052 */
2053
2054/* I2C I2CON Bit Field Definitions */
2055#define I2C_I2CON_EI_Pos 7 /*!< I2C_T::I2CON: EI Position */
2056#define I2C_I2CON_EI_Msk (1ul << I2C_I2CON_EI_Pos) /*!< I2C_T::I2CON: EI Mask */
2057
2058#define I2C_I2CON_ENS1_Pos 6 /*!< I2C_T::I2CON: ENS1 Position */
2059#define I2C_I2CON_ENS1_Msk (1ul << I2C_I2CON_ENS1_Pos) /*!< I2C_T::I2CON: ENS1 Mask */
2060
2061#define I2C_I2CON_STA_Pos 5 /*!< I2C_T::I2CON: STA Position */
2062#define I2C_I2CON_STA_Msk (1ul << I2C_I2CON_STA_Pos) /*!< I2C_T::I2CON: STA Mask */
2063
2064#define I2C_I2CON_STO_Pos 4 /*!< I2C_T::I2CON: STO Position */
2065#define I2C_I2CON_STO_Msk (1ul << I2C_I2CON_STO_Pos) /*!< I2C_T::I2CON: STO Mask */
2066
2067#define I2C_I2CON_SI_Pos 3 /*!< I2C_T::I2CON: SI Position */
2068#define I2C_I2CON_SI_Msk (1ul << I2C_I2CON_SI_Pos) /*!< I2C_T::I2CON: SI Mask */
2069
2070#define I2C_I2CON_AA_Pos 2 /*!< I2C_T::I2CON: AA Position */
2071#define I2C_I2CON_AA_Msk (1ul << I2C_I2CON_AA_Pos) /*!< I2C_T::I2CON: AA Mask */
2072
2073/* I2C I2CADDR Bit Field Definitions */
2074#define I2C_I2CADDR_I2CADDR_Pos 1 /*!< I2C_T::I2CADDR1: I2CADDR Position */
2075#define I2C_I2CADDR_I2CADDR_Msk (0x7Ful << I2C_I2CADDR_I2CADDR_Pos) /*!< I2C_T::I2CADDR1: I2CADDR Mask */
2076
2077#define I2C_I2CADDR_GC_Pos 0 /*!< I2C_T::I2CADDR1: GC Position */
2078#define I2C_I2CADDR_GC_Msk (1ul << I2C_I2CADDR_GC_Pos) /*!< I2C_T::I2CADDR1: GC Mask */
2079
2080/* I2C I2CDAT Bit Field Definitions */
2081#define I2C_I2CDAT_I2CDAT_Pos 0 /*!< I2C_T::I2CDAT: I2CDAT Position */
2082#define I2C_I2CDAT_I2CDAT_Msk (0xFFul << I2C_I2CDAT_I2CDAT_Pos) /*!< I2C_T::I2CDAT: I2CDAT Mask */
2083
2084/* I2C I2CSTATUS Bit Field Definitions */
2085#define I2C_I2CSTATUS_I2CSTATUS_Pos 0 /*!< I2C_T::I2CSTATUS: I2CSTATUS Position */
2086#define I2C_I2CSTATUS_I2CSTATUS_Msk (0xFFul << I2C_I2CSTATUS_I2CSTATUS_Pos) /*!< I2C_T::I2CSTATUS: I2CSTATUS Mask */
2087
2088/* I2C I2CLK Bit Field Definitions */
2089#define I2C_I2CLK_I2CLK_Pos 0 /*!< I2C_T::I2CLK: I2CLK Position */
2090#define I2C_I2CLK_I2CLK_Msk (0xFFul << I2C_I2CLK_I2CLK_Pos) /*!< I2C_T::I2CLK: I2CLK Mask */
2091
2092/* I2C I2CTOC Bit Field Definitions */
2093#define I2C_I2CTOC_ENTI_Pos 2 /*!< I2C_T::I2CTOC: ENTI Position */
2094#define I2C_I2CTOC_ENTI_Msk (1ul << I2C_I2CTOC_ENTI_Pos) /*!< I2C_T::I2CTOC: ENTI Mask */
2095
2096#define I2C_I2CTOC_DIV4_Pos 1 /*!< I2C_T::I2CTOC: DIV4 Position */
2097#define I2C_I2CTOC_DIV4_Msk (1ul << I2C_I2CTOC_DIV4_Pos) /*!< I2C_T::I2CTOC: DIV4 Mask */
2098
2099#define I2C_I2CTOC_TIF_Pos 0 /*!< I2C_T::I2CTOC: TIF Position */
2100#define I2C_I2CTOC_TIF_Msk (1ul << I2C_I2CTOC_TIF_Pos) /*!< I2C_T::I2CTOC: TIF Mask */
2101
2102/* I2C I2CADM Bit Field Definitions */
2103#define I2C_I2CADM_I2CADM_Pos 1 /*!< I2C_T::I2CADM0: I2CADM Position */
2104#define I2C_I2CADM_I2CADM_Msk (0x7Ful << I2C_I2CADM_I2CADM_Pos) /*!< I2C_T::I2CADM0: I2CADM Mask */
2105
2106/* I2C I2CWKUPCON Bit Field Definitions */
2107#define I2C_I2CWKUPCON_WKUPEN_Pos 0 /*!< I2C_T::I2CWKUPCON: WKUPEN Position */
2108#define I2C_I2CWKUPCON_WKUPEN_Msk (1ul << I2C_I2CWKUPCON_WKUPEN_Pos) /*!< I2C_T::I2CWKUPCON: WKUPEN Mask */
2109
2110/* I2C I2CWKUPSTS Bit Field Definitions */
2111#define I2C_I2CWKUPSTS_WKUPIF_Pos 0 /*!< I2C_T::I2CWKUPSTS: WKUPIF Position */
2112#define I2C_I2CWKUPSTS_WKUPIF_Msk (1ul << I2C_I2CWKUPSTS_WKUPIF_Pos) /*!< I2C_T::I2CWKUPSTS: WKUPIF Mask */
2113/*@}*/ /* end of group REG_I2C_BITMASK */
2114/*@}*/ /* end of group REG_I2C */
2115
2116/*----------------------------- I2S Controller -------------------------------*/
2117/** @addtogroup REG_I2S Integrated Inter-chip Sound(I2S)
2118 Memory Mapped Structure for I2S Interface Controller
2119 @{
2120 */
2121
2122typedef struct
2123{
2124
2125
2126/**
2127 * @var I2S_T::CON
2128 * Offset: 0x00 I2S Control Register
2129 * ---------------------------------------------------------------------------------------------------
2130 * |Bits |Field |Descriptions
2131 * | :----: | :----: | :---- |
2132 * |[0] |I2SEN |I2S Controller Enable
2133 * | | |0 = Disabled.
2134 * | | |1 = Enabled.
2135 * |[1] |TXEN |Transmit Enable
2136 * | | |0 = Data transmit Disabled.
2137 * | | |1 = Data transmit Enabled.
2138 * |[2] |RXEN |Receive Enable
2139 * | | |0 = Data receiving Disabled.
2140 * | | |1 = Data receiving Enabled.
2141 * |[3] |MUTE |Transmit Mute Enable
2142 * | | |0 = Transmit data is shifted from buffer.
2143 * | | |1 = Send zero on transmit channel.
2144 * |[5:4] |WORDWIDTH |Word Width
2145 * | | |00 = data is 8-bit word.
2146 * | | |01 = data is 16-bit word.
2147 * | | |10 = data is 24-bit word.
2148 * | | |11 = data is 32-bit word.
2149 * |[6] |MONO |Monaural Data
2150 * | | |0 = Data is stereo format.
2151 * | | |1 = Data is monaural format.
2152 * |[7] |FORMAT |Data Format
2153 * | | |0 = I2S data format.
2154 * | | |1 = MSB justified data format.
2155 * |[8] |SLAVE |Slave Mode
2156 * | | |I2S can operate as master or slave.
2157 * | | |For Master mode, I2SBCLK and I2SLRCLK pins are output mode and send bit clock from NuMicro NUC123 series to Audio CODEC chip.
2158 * | | |In Slave mode, I2SBCLK and I2SLRCLK pins are input mode and I2SBCLK and I2SLRCLK signals are received from outer Audio CODEC chip.
2159 * | | |0 = Master mode.
2160 * | | |1 = Slave mode.
2161 * |[11:9] |TXTH |Transmit FIFO Threshold Level
2162 * | | |If the count of remaining data word (32 bits) in transmit FIFO is equal to or less than threshold level then TXTHF (I2SSTATUS[18]) is set.
2163 * | | |000 = 0 word data in transmit FIFO.
2164 * | | |001 = 1 word data in transmit FIFO.
2165 * | | |010 = 2 words data in transmit FIFO.
2166 * | | |011 = 3 words data in transmit FIFO.
2167 * | | |100 = 4 words data in transmit FIFO.
2168 * | | |101 = 5 words data in transmit FIFO.
2169 * | | |110 = 6 words data in transmit FIFO.
2170 * | | |111 = 7 words data in transmit FIFO.
2171 * |[14:12] |RXTH |Receive FIFO Threshold Level
2172 * | | |When the count of received data word(s) in buffer is equal to or higher than threshold level, RXTHF (I2SSTATUS[10]) will be set.
2173 * | | |000 = 1 word data in receive FIFO.
2174 * | | |001 = 2 word data in receive FIFO.
2175 * | | |010 = 3 word data in receive FIFO.
2176 * | | |011 = 4 word data in receive FIFO.
2177 * | | |100 = 5 word data in receive FIFO.
2178 * | | |101 = 6 word data in receive FIFO.
2179 * | | |110 = 7 word data in receive FIFO.
2180 * | | |111 = 8 word data in receive FIFO.
2181 * |[15] |MCLKEN |Master Clock Enable
2182 * | | |If MCLKEN is set to 1, I2S controller will generate master clock on I2S_MCLK pin for external audio devices.
2183 * | | |0 = Master clock Disabled.
2184 * | | |1 = Master clock Enabled.
2185 * |[16] |RCHZCEN |Right Channel Zero Cross Detection Enable
2186 * | | |If this bit is set to 1, when right channel data sign bit change or next shift data bits are all 0 then RZCF flag in I2SSTATUS register is set to 1.
2187 * | | |This function is only available in transmit operation.
2188 * | | |0 = Right channel zero cross detection Disabled.
2189 * | | |1 = Right channel zero cross detection Enabled.
2190 * |[17] |LCHZCEN |Left Channel Zero Cross Detection Enable
2191 * | | |If this bit is set to 1, when left channel data sign bit changes or next shift data bits are all 0 then LZCF flag in I2SSTATUS register is set to 1.
2192 * | | |This function is only available in transmit operation.
2193 * | | |0 = Left channel zero cross detection Disabled.
2194 * | | |1 = Left channel zero cross detection Enabled.
2195 * |[18] |CLR_TXFIFO|Clear Transmit FIFO
2196 * | | |Write 1 to clear transmit FIFO, internal pointer is reset to FIFO start point, and TX_LEVEL[3:0] returns to 0 and
2197 * | | |transmit FIFO becomes empty but data in transmit FIFO is not changed.
2198 * | | |This bit is cleared by hardware automatically. Returns 0 on read.
2199 * |[19] |CLR_RXFIFO|Clear Receive FIFO
2200 * | | |Write 1 to clear receive FIFO, internal pointer is reset to FIFO start point, and RX_LEVEL[3:0] returns 0 and receive FIFO becomes empty.
2201 * | | |This bit is cleared by hardware automatically. Returns 0 on read.
2202 * |[20] |TXDMA |Enable Transmit DMA
2203 * | | |When TX DMA is enabled, I2S request DMA to transfer data from SRAM to transmit FIFO if FIFO is not full.
2204 * | | |0 = TX DMA Disabled.
2205 * | | |1 = TX DMA Enabled.
2206 * |[21] |RXDMA |Enable Receive DMA
2207 * | | |When RX DMA is enabled, I2S requests DMA to transfer data from receive FIFO to SRAM if FIFO is not empty.
2208 * | | |0 = RX DMA Disabled.
2209 * | | |1 = RX DMA Enabled.
2210 * |[23] |RXLCH |Receive Left Channel Enable
2211 * | | |When monaural format is selected (MONO = 1), I2S controller will receive right channel data if RXLCH is set to 0,
2212 * | | |and receive left channel data if RXLCH is set to 1.
2213 * | | |0 = Receive right channel data in Mono mode.
2214 * | | |1 = Receive left channel data in Mono mode.
2215 * @var I2S_T::CLKDIV
2216 * Offset: 0x04 I2S Clock Divider Control Register
2217 * ---------------------------------------------------------------------------------------------------
2218 * |Bits |Field |Descriptions
2219 * | :----: | :----: | :---- |
2220 * |[2:0] |MCLK_DIV |Master Clock Divider
2221 * | | |If MCLKEN is set to 1, I2S controller will generate master clock for external audio devices.
2222 * | | |The master clock rate, F_MCLK, is determined by the following expressions.
2223 * | | |If MCLK_DIV >= 1, F_MCLK = F_I2SCLK/(2x(MCLK_DIV)).
2224 * | | |If MCLK_DIV = 0, F_MCLK = F_I2SCLK.
2225 * | | |F_I2SCLK is the frequency of I2S peripheral clock.
2226 * | | |In general, the master clock rate is 256 times sampling clock rate.
2227 * |[15:8] |BCLK_DIV |Bit Clock Divider
2228 * | | |The I2S controller will generate bit clock in Master mode.
2229 * | | |The bit clock rate, F_BCLK, is determined by the following expression.
2230 * | | |F_BCLK = F_I2SCLK /(2x(BCLK_DIV + 1)) , where F_I2SCLK is the frequency of I2S peripheral clock.
2231 * @var I2S_T::IE
2232 * Offset: 0x08 I2S Interrupt Enable Register
2233 * ---------------------------------------------------------------------------------------------------
2234 * |Bits |Field |Descriptions
2235 * | :----: | :----: | :---- |
2236 * |[0] |RXUDFIE |Receive FIFO Underflow Interrupt Enable
2237 * | | |0 = Interrupt Disabled.
2238 * | | |1 = Interrupt Enabled.
2239 * |[1] |RXOVFIE |Receive FIFO Overflow Interrupt Enable
2240 * | | |0 = Interrupt Disabled.
2241 * | | |1 = Interrupt Enabled.
2242 * |[2] |RXTHIE |Receive FIFO Threshold Level Interrupt Enable
2243 * | | |When the count of data words in receive FIFO is equal to or higher than RXTH (I2SCON[14:12]) and
2244 * | | |this bit is set to 1, receive FIFO threshold level interrupt will be asserted.
2245 * | | |0 = Interrupt Disabled.
2246 * | | |1 = Interrupt Enabled.
2247 * |[8] |TXUDFIE |Transmit FIFO Underflow Interrupt Enable
2248 * | | |Interrupt occurs if this bit is set to 1 and the transmit FIFO underflow flag is set to 1.
2249 * | | |0 = Interrupt Disabled.
2250 * | | |1 = Interrupt Enabled.
2251 * |[9] |TXOVFIE |Transmit FIFO Overflow Interrupt Enable
2252 * | | |Interrupt occurs if this bit is set to 1 and the transmit FIFO overflow flag is set to 1
2253 * | | |0 = Interrupt Disabled.
2254 * | | |1 = Interrupt Enabled.
2255 * |[10] |TXTHIE |Transmit FIFO Threshold Level Interrupt Enable
2256 * | | |Interrupt occurs if this bit is set to 1 and the count of data words in transmit FIFO is less than TXTH (I2SCON[11:9]).
2257 * | | |0 = Interrupt Disabled.
2258 * | | |1 = Interrupt Enabled.
2259 * |[11] |RZCIE |Right Channel Zero-Cross Interrupt Enable
2260 * | | |Interrupt occurs if this bit is set to 1 and right channel zero-cross event is detected.
2261 * | | |0 = Interrupt Disabled.
2262 * | | |1 = Interrupt Enabled.
2263 * |[12] |LZCIE |Left Channel Zero-Cross Interrupt Enable
2264 * | | |Interrupt occurs if this bit is set to 1 and left channel zero-cross event is detected.
2265 * | | |0 = Interrupt Disabled.
2266 * | | |1 = Interrupt Enabled.
2267 * @var I2S_T::STATUS
2268 * Offset: 0x0C I2S Status Register
2269 * ---------------------------------------------------------------------------------------------------
2270 * |Bits |Field |Descriptions
2271 * | :----: | :----: | :---- |
2272 * |[0] |I2SINT |I2S Interrupt Flag
2273 * | | |This bit is wire-OR of I2STXINT and I2SRXINT bits.
2274 * | | |0 = No I2S interrupt.
2275 * | | |1 = I2S interrupt.
2276 * | | |Note: This bit is read only.
2277 * |[1] |I2SRXINT |I2S Receive Interrupt
2278 * | | |0 = No receive interrupt.
2279 * | | |1 = Receive interrupt.
2280 * | | |Note: This bit is read only.
2281 * |[2] |I2STXINT |I2S Transmit Interrupt
2282 * | | |0 = No transmit interrupt.
2283 * | | |1 = Transmit interrupt.
2284 * | | |Note: This bit is read only.
2285 * |[3] |RIGHT |Right Channel
2286 * | | |This bit indicates current transmit data is belong to which channel
2287 * | | |0 = Left channel.
2288 * | | |1 = Right channel.
2289 * | | |Note: This bit is read only.
2290 * |[8] |RXUDF |Receive FIFO Underflow Flag
2291 * | | |Underflow event will occur if read the empty receive FIFO.
2292 * | | |0 = No underflow event occurred.
2293 * | | |1 = Underflow.
2294 * | | |Note: Write 1 to clear this bit to 0.
2295 * |[9] |RXOVF |Receive FIFO Overflow Flag
2296 * | | |When receive FIFO is full and hardware attempt to write data to receive FIFO, this bit will be set to 1, data in 1st buffer will be overwrote.
2297 * | | |0 = No overflow.
2298 * | | |1 = Overflow.
2299 * | | |Note: Write 1 to clear this bit to 0.
2300 * |[10] |RXTHF |Receive FIFO Threshold Flag
2301 * | | |When data word(s) in receive FIFO is equal to or larger than threshold value set in RXTH (I2SCON[14:12]).
2302 * | | |The RXTHF bit becomes to 1.
2303 * | | |It keeps at 1 till RX_LEVEL (I2SSTATUS[27:24]) is less than RXTH.
2304 * | | |0 = Data word(s) in FIFO is less than threshold level.
2305 * | | |1 = Data word(s) in FIFO is equal to or larger than threshold level.
2306 * | | |Note: This bit is read only.
2307 * |[11] |RXFULL |Receive FIFO Full
2308 * | | |This bit reflects the count of data in receive FIFO is 8
2309 * | | |0 = Not full.
2310 * | | |1 = Full.
2311 * | | |Note: This bit is read only.
2312 * |[12] |RXEMPTY |Receive FIFO Empty
2313 * | | |This bit reflects the count of data in receive FIFO is 0
2314 * | | |0 = Not empty.
2315 * | | |1 = Empty.
2316 * | | |Note: This bit is read only.
2317 * |[16] |TXUDF |Transmit FIFO Underflow Flag
2318 * | | |If transmit FIFO is empty and hardware reads data from transmit FIFO. This bit will be set to 1.
2319 * | | |0 = No underflow.
2320 * | | |1 = Underflow.
2321 * | | |Note: Software can write 1 to clear this bit to 0.
2322 * |[17] |TXOVF |Transmit FIFO Overflow Flag
2323 * | | |This bit will be set to 1 if writes data to transmit FIFO when transmit FIFO is full.
2324 * | | |0 = No overflow.
2325 * | | |1 = Overflow.
2326 * | | |Note: Write 1 to clear this bit to 0.
2327 * |[18] |TXTHF |Transmit FIFO Threshold Flag
2328 * | | |When the count of data stored in transmit-FIFO is equal to or less than threshold value set in TXTH (I2SCON[11:9]).
2329 * | | |The TXTHF bit becomes to 1.
2330 * | | |It keeps at 1 till TX_LEVEL (I2SSTATUS[31:28]) is larger than TXTH.
2331 * | | |0 = Data word(s) in FIFO is larger than threshold level.
2332 * | | |1 = Data word(s) in FIFO is equal to or less than threshold level.
2333 * | | |Note: This bit is read only.
2334 * |[19] |TXFULL |Transmit FIFO Full
2335 * | | |This bit reflects data word number in transmit FIFO is 8
2336 * | | |0 = Not full.
2337 * | | |1 = Full.
2338 * | | |Note: This bit is read only.
2339 * |[20] |TXEMPTY |Transmit FIFO Empty
2340 * | | |This bit reflects data word number in transmit FIFO is 0
2341 * | | |0 = Not empty.
2342 * | | |1 = Empty.
2343 * | | |Note: This bit is read only.
2344 * |[21] |TXBUSY |Transmit Busy
2345 * | | |This bit is cleared to 0 when all data in transmit FIFO and shift buffer is shifted out.
2346 * | | |And set to 1 when 1st data is load to shift buffer.
2347 * | | |0 = Transmit shift buffer is empty.
2348 * | | |1 = Transmit shift buffer is not empty.
2349 * | | |Note: This bit is read only.
2350 * |[22] |RZCF |Right Channel Zero-Cross Flag
2351 * | | |It indicates the sign bit of right channel sample data is changed or all data bits are 0.
2352 * | | |0 = No zero-cross.
2353 * | | |1 = Right channel zero-cross event is detected.
2354 * | | |Note: Write 1 to clear this bit to 0.
2355 * |[23] |LZCF |Left Channel Zero-Cross Flag
2356 * | | |It indicates the sign bit of left channel sample data is changed or all data bits are 0.
2357 * | | |0 = No zero-cross.
2358 * | | |1 = Left channel zero-cross event is detected.
2359 * | | |Note: Write 1 to clear this bit to 0.
2360 * |[27:24] |RX_LEVEL |Receive FIFO Level
2361 * | | |These bits indicate word number in receive FIFO
2362 * | | |0000 = No data.
2363 * | | |0001 = 1 word in receive FIFO.
2364 * | | |....
2365 * | | |1000 = 8 words in receive FIFO.
2366 * |[31:28] |TX_LEVEL |Transmit FIFO Level
2367 * | | |These bits indicate word number in transmit FIFO
2368 * | | |0000 = No data.
2369 * | | |0001 = 1 word in transmit FIFO.
2370 * | | |....
2371 * | | |1000 = 8 words in transmit FIFO.
2372 * @var I2S_T::TXFIFO
2373 * Offset: 0x10 I2S Transmit FIFO Register
2374 * ---------------------------------------------------------------------------------------------------
2375 * |Bits |Field |Descriptions
2376 * | :----: | :----: | :---- |
2377 * |[31:0] |TXFIFO |Transmit FIFO Register
2378 * | | |I2S contains 8 words (8x32 bits) data buffer for data transmit.
2379 * | | |Write data to this register to prepare data for transmission.
2380 * | | |The remaining word number is indicated by TX_LEVEL (I2SSTATUS[31:28]).
2381 * @var I2S_T::RXFIFO
2382 * Offset: 0x14 I2S Receive FIFO Register
2383 * ---------------------------------------------------------------------------------------------------
2384 * |Bits |Field |Descriptions
2385 * | :----: | :----: | :---- |
2386 * |[31:0] |RXFIFO |Receive FIFO Register
2387 * | | |I2S contains 8 words (8x32 bits) data buffer for data receive.
2388 * | | |Read this register to get data of receive FIFO.
2389 * | | |The remaining data word number is indicated by RX_LEVEL (I2SSTATUS[27:24]).
2390 */
2391
2392 __IO uint32_t CON; /* Offset: 0x00 I2S Control Register */
2393 __IO uint32_t CLKDIV; /* Offset: 0x04 I2S Clock Divider Control Register */
2394 __IO uint32_t IE; /* Offset: 0x08 I2S Interrupt Enable Register */
2395 __IO uint32_t STATUS; /* Offset: 0x0C I2S Status Register */
2396 __O uint32_t TXFIFO; /* Offset: 0x10 I2S Transmit FIFO Register */
2397 __I uint32_t RXFIFO; /* Offset: 0x14 I2S Receive FIFO Register */
2398
2399} I2S_T;
2400
2401
2402
2403/** @addtogroup REG_I2S_BITMASK I2S Bit Mask
2404 @{
2405 */
2406
2407/* I2S I2SCON Bit Field Definitions */
2408#define I2S_CON_PCM_Pos 24 /*!< I2S_T::CON: PCM Position */
2409#define I2S_CON_PCM_Msk (1ul << I2S_CON_PCM_Pos) /*!< I2S_T::CON: PCM Mask */
2410
2411#define I2S_CON_RXLCH_Pos 23 /*!< I2S_T::CON: RXLCH Position */
2412#define I2S_CON_RXLCH_Msk (1ul << I2S_CON_RXLCH_Pos) /*!< I2S_T::CON: RXLCH Mask */
2413
2414#define I2S_CON_RXDMA_Pos 21 /*!< I2S_T::CON: RXDMA Position */
2415#define I2S_CON_RXDMA_Msk (1ul << I2S_CON_RXDMA_Pos) /*!< I2S_T::CON: RXDMA Mask */
2416
2417#define I2S_CON_TXDMA_Pos 20 /*!< I2S_T::CON: TXDMA Position */
2418#define I2S_CON_TXDMA_Msk (1ul << I2S_CON_TXDMA_Pos) /*!< I2S_T::CON: TXDMA Mask */
2419
2420#define I2S_CON_CLR_RXFIFO_Pos 19 /*!< I2S_T::CON: CLR_RXFIFO Position */
2421#define I2S_CON_CLR_RXFIFO_Msk (1ul << I2S_CON_CLR_RXFIFO_Pos) /*!< I2S_T::CON: CLR_RXFIFO Mask */
2422
2423#define I2S_CON_CLR_TXFIFO_Pos 18 /*!< I2S_T::CON: CLR_TXFIFO Position */
2424#define I2S_CON_CLR_TXFIFO_Msk (1ul << I2S_CON_CLR_TXFIFO_Pos) /*!< I2S_T::CON: CLR_TXFIFO Mask */
2425
2426#define I2S_CON_LCHZCEN_Pos 17 /*!< I2S_T::CON: LCHZCEN Position */
2427#define I2S_CON_LCHZCEN_Msk (1ul << I2S_CON_LCHZCEN_Pos) /*!< I2S_T::CON: LCHZCEN Mask */
2428
2429#define I2S_CON_RCHZCEN_Pos 16 /*!< I2S_T::CON: RCHZCEN Position */
2430#define I2S_CON_RCHZCEN_Msk (1ul << I2S_CON_RCHZCEN_Pos) /*!< I2S_T::CON: RCHZCEN Mask */
2431
2432#define I2S_CON_MCLKEN_Pos 15 /*!< I2S_T::CON: MCLKEN Position */
2433#define I2S_CON_MCLKEN_Msk (1ul << I2S_CON_MCLKEN_Pos) /*!< I2S_T::CON: MCLKEN Mask */
2434
2435#define I2S_CON_RXTH_Pos 12 /*!< I2S_T::CON: RXTH Position */
2436#define I2S_CON_RXTH_Msk (7ul << I2S_CON_RXTH_Pos) /*!< I2S_T::CON: RXTH Mask */
2437
2438#define I2S_CON_TXTH_Pos 9 /*!< I2S_T::CON: TXTH Position */
2439#define I2S_CON_TXTH_Msk (7ul << I2S_CON_TXTH_Pos) /*!< I2S_T::CON: TXTH Mask */
2440
2441#define I2S_CON_SLAVE_Pos 8 /*!< I2S_T::CON: SLAVE Position */
2442#define I2S_CON_SLAVE_Msk (1ul << I2S_CON_SLAVE_Pos) /*!< I2S_T::CON: SLAVE Mask */
2443
2444#define I2S_CON_FORMAT_Pos 7 /*!< I2S_T::CON: FORMAT Position */
2445#define I2S_CON_FORMAT_Msk (1ul << I2S_CON_FORMAT_Pos) /*!< I2S_T::CON: FORMAT Mask */
2446
2447#define I2S_CON_MONO_Pos 6 /*!< I2S_T::CON: MONO Position */
2448#define I2S_CON_MONO_Msk (1ul << I2S_CON_MONO_Pos) /*!< I2S_T::CON: MONO Mask */
2449
2450#define I2S_CON_WORDWIDTH_Pos 4 /*!< I2S_T::CON: WORDWIDTH Position */
2451#define I2S_CON_WORDWIDTH_Msk (3ul << I2S_CON_WORDWIDTH_Pos) /*!< I2S_T::CON: WORDWIDTH Mask */
2452
2453#define I2S_CON_MUTE_Pos 3 /*!< I2S_T::CON: MUTE Position */
2454#define I2S_CON_MUTE_Msk (1ul << I2S_CON_MUTE_Pos) /*!< I2S_T::CON: MUTE Mask */
2455
2456#define I2S_CON_RXEN_Pos 2 /*!< I2S_T::CON: RXEN Position */
2457#define I2S_CON_RXEN_Msk (1ul << I2S_CON_RXEN_Pos) /*!< I2S_T::CON: RXEN Mask */
2458
2459#define I2S_CON_TXEN_Pos 1 /*!< I2S_T::CON: TXEN Position */
2460#define I2S_CON_TXEN_Msk (1ul << I2S_CON_TXEN_Pos) /*!< I2S_T::CON: TXEN Mask */
2461
2462#define I2S_CON_I2SEN_Pos 0 /*!< I2S_T::CON: I2SEN Position */
2463#define I2S_CON_I2SEN_Msk (1ul << I2S_CON_I2SEN_Pos) /*!< I2S_T::CON: I2SEN Mask */
2464
2465/* I2S I2SCLKDIV Bit Field Definitions */
2466#define I2S_CLKDIV_BCLK_DIV_Pos 8 /*!< I2S_T::CLKDIV: BCLK_DIV Position */
2467#define I2S_CLKDIV_BCLK_DIV_Msk (0xFFul << I2S_CLKDIV_BCLK_DIV_Pos) /*!< I2S_T::CLKDIV: BCLK_DIV Mask */
2468
2469#define I2S_CLKDIV_MCLK_DIV_Pos 0 /*!< I2S_T::CLKDIV: MCLK_DIV Position */
2470#define I2S_CLKDIV_MCLK_DIV_Msk (7ul << I2S_CLKDIV_MCLK_DIV_Pos) /*!< I2S_T::CLKDIV: MCLK_DIV Mask */
2471
2472/* I2S I2SIE Bit Field Definitions */
2473#define I2S_IE_LZCIE_Pos 12 /*!< I2S_T::IE: LZCIE Position */
2474#define I2S_IE_LZCIE_Msk (1ul << I2S_IE_LZCIE_Pos) /*!< I2S_T::IE: LZCIE Mask */
2475
2476#define I2S_IE_RZCIE_Pos 11 /*!< I2S_T::IE: RZCIE Position */
2477#define I2S_IE_RZCIE_Msk (1ul << I2S_IE_RZCIE_Pos) /*!< I2S_T::IE: RZCIE Mask */
2478
2479#define I2S_IE_TXTHIE_Pos 10 /*!< I2S_T::IE: TXTHIE Position */
2480#define I2S_IE_TXTHIE_Msk (1ul << I2S_IE_TXTHIE_Pos) /*!< I2S_T::IE: TXTHIE Mask */
2481
2482#define I2S_IE_TXOVFIE_Pos 9 /*!< I2S_T::IE: TXOVFIE Position */
2483#define I2S_IE_TXOVFIE_Msk (1ul << I2S_IE_TXOVFIE_Pos) /*!< I2S_T::IE: TXOVFIE Mask */
2484
2485#define I2S_IE_TXUDFIE_Pos 8 /*!< I2S_T::IE: TXUDFIE Position */
2486#define I2S_IE_TXUDFIE_Msk (1ul << I2S_IE_TXUDFIE_Pos) /*!< I2S_T::IE: TXUDFIE Mask */
2487
2488#define I2S_IE_RXTHIE_Pos 2 /*!< I2S_T::IE: RXTHIE Position */
2489#define I2S_IE_RXTHIE_Msk (1ul << I2S_IE_RXTHIE_Pos) /*!< I2S_T::IE: RXTHIE Mask */
2490
2491#define I2S_IE_RXOVFIE_Pos 1 /*!< I2S_T::IE: RXOVFIE Position */
2492#define I2S_IE_RXOVFIE_Msk (1ul << I2S_IE_RXOVFIE_Pos) /*!< I2S_T::IE: RXOVFIE Mask */
2493
2494#define I2S_IE_RXUDFIE_Pos 0 /*!< I2S_T::IE: RXUDFIE Position */
2495#define I2S_IE_RXUDFIE_Msk (1ul << I2S_IE_RXUDFIE_Pos) /*!< I2S_T::IE: RXUDFIE Mask */
2496
2497
2498/* I2S I2SSTATUS Bit Field Definitions */
2499#define I2S_STATUS_TX_LEVEL_Pos 28 /*!< I2S_T::STATUS: TX_LEVEL Position */
2500#define I2S_STATUS_TX_LEVEL_Msk (0xFul << I2S_STATUS_TX_LEVEL_Pos) /*!< I2S_T::STATUS: TX_LEVEL Mask */
2501
2502#define I2S_STATUS_RX_LEVEL_Pos 24 /*!< I2S_T::STATUS: RX_LEVEL Position */
2503#define I2S_STATUS_RX_LEVEL_Msk (0xFul << I2S_STATUS_RX_LEVEL_Pos) /*!< I2S_T::STATUS: RX_LEVEL Mask */
2504
2505#define I2S_STATUS_LZCF_Pos 23 /*!< I2S_T::STATUS: LZCF Position */
2506#define I2S_STATUS_LZCF_Msk (1ul << I2S_STATUS_LZCF_Pos) /*!< I2S_T::STATUS: LZCF Mask */
2507
2508#define I2S_STATUS_RZCF_Pos 22 /*!< I2S_T::STATUS: RZCF Position */
2509#define I2S_STATUS_RZCF_Msk (1ul << I2S_STATUS_RZCF_Pos) /*!< I2S_T::STATUS: RZCF Mask */
2510
2511#define I2S_STATUS_TXBUSY_Pos 21 /*!< I2S_T::STATUS: TXBUSY Position */
2512#define I2S_STATUS_TXBUSY_Msk (1ul << I2S_STATUS_TXBUSY_Pos) /*!< I2S_T::STATUS: TXBUSY Mask */
2513
2514#define I2S_STATUS_TXEMPTY_Pos 20 /*!< I2S_T::STATUS: TXEMPTY Position */
2515#define I2S_STATUS_TXEMPTY_Msk (1ul << I2S_STATUS_TXEMPTY_Pos) /*!< I2S_T::STATUS: TXEMPTY Mask */
2516
2517#define I2S_STATUS_TXFULL_Pos 19 /*!< I2S_T::STATUS: TXFULL Position */
2518#define I2S_STATUS_TXFULL_Msk (1ul << I2S_STATUS_TXFULL_Pos) /*!< I2S_T::STATUS: TXFULL Mask */
2519
2520#define I2S_STATUS_TXTHF_Pos 18 /*!< I2S_T::STATUS: TXTHF Position */
2521#define I2S_STATUS_TXTHF_Msk (1ul << I2S_STATUS_TXTHF_Pos) /*!< I2S_T::STATUS: TXTHF Mask */
2522
2523#define I2S_STATUS_TXOVF_Pos 17 /*!< I2S_T::STATUS: TXOVF Position */
2524#define I2S_STATUS_TXOVF_Msk (1ul << I2S_STATUS_TXOVF_Pos) /*!< I2S_T::STATUS: TXOVF Mask */
2525
2526#define I2S_STATUS_TXUDF_Pos 16 /*!< I2S_T::STATUS: TXUDF Position */
2527#define I2S_STATUS_TXUDF_Msk (1ul << I2S_STATUS_TXUDF_Pos) /*!< I2S_T::STATUS: TXUDF Mask */
2528
2529#define I2S_STATUS_RXEMPTY_Pos 12 /*!< I2S_T::STATUS: RXEMPTY Position */
2530#define I2S_STATUS_RXEMPTY_Msk (1ul << I2S_STATUS_RXEMPTY_Pos) /*!< I2S_T::STATUS: RXEMPTY Mask */
2531
2532#define I2S_STATUS_RXFULL_Pos 11 /*!< I2S_T::STATUS: RXFULL Position */
2533#define I2S_STATUS_RXFULL_Msk (1ul << I2S_STATUS_RXFULL_Pos) /*!< I2S_T::STATUS: RXFULL Mask */
2534
2535#define I2S_STATUS_RXTHF_Pos 10 /*!< I2S_T::STATUS: RXTHF Position */
2536#define I2S_STATUS_RXTHF_Msk (1ul << I2S_STATUS_RXTHF_Pos) /*!< I2S_T::STATUS: RXTHF Mask */
2537
2538#define I2S_STATUS_RXOVF_Pos 9 /*!< I2S_T::STATUS: RXOVF Position */
2539#define I2S_STATUS_RXOVF_Msk (1ul << I2S_STATUS_RXOVF_Pos) /*!< I2S_T::STATUS: RXOVF Mask */
2540
2541#define I2S_STATUS_RXUDF_Pos 8 /*!< I2S_T::STATUS: RXUDF Position */
2542#define I2S_STATUS_RXUDF_Msk (1ul << I2S_STATUS_RXUDF_Pos) /*!< I2S_T::STATUS: RXUDF Mask */
2543
2544#define I2S_STATUS_RIGHT_Pos 3 /*!< I2S_T::STATUS: RIGHT Position */
2545#define I2S_STATUS_RIGHT_Msk (1ul << I2S_STATUS_RIGHT_Pos) /*!< I2S_T::STATUS: RIGHT Mask */
2546
2547#define I2S_STATUS_I2STXINT_Pos 2 /*!< I2S_T::STATUS: I2STXINT Position */
2548#define I2S_STATUS_I2STXINT_Msk (1ul << I2S_STATUS_I2STXINT_Pos) /*!< I2S_T::STATUS: I2STXINT Mask */
2549
2550#define I2S_STATUS_I2SRXINT_Pos 1 /*!< I2S_T::STATUS: I2SRXINT Position */
2551#define I2S_STATUS_I2SRXINT_Msk (1ul << I2S_STATUS_I2SRXINT_Pos) /*!< I2S_T::STATUS: I2SRXINT Mask */
2552
2553#define I2S_STATUS_I2SINT_Pos 0 /*!< I2S_T::STATUS: I2SINT Position */
2554#define I2S_STATUS_I2SINT_Msk (1ul << I2S_STATUS_I2SINT_Pos) /*!< I2S_T::STATUS: I2SINT Mask */
2555/*@}*/ /* end of group REG_I2S_BITMASK */
2556/*@}*/ /* end of group REG_I2S */
2557
2558/*------------------------------ DMA Controller -----------------------------*/
2559/** @addtogroup REG_PDMA Peripheral Direct Memory Access Controller (PDMA)
2560 Memory Mapped Structure for PDMA Controller
2561 @{
2562 */
2563
2564typedef struct
2565{
2566
2567
2568/**
2569 * @var PDMA_T::CSR
2570 * Offset: 0x00 PDMA Channel x Control Register
2571 * ---------------------------------------------------------------------------------------------------
2572 * |Bits |Field |Descriptions
2573 * | :----: | :----: | :---- |
2574 * |[0] |PDMACEN |PDMA Channel Enable Bit
2575 * | | |Setting this bit to 1 enables PDMA operation.
2576 * | | |If this bit is cleared, PDMA will ignore all PDMA request and force Bus Master into IDLE state.
2577 * |[1] |SW_RST |Software Engine Reset
2578 * | | |0 = No effect.
2579 * | | |1 = Reset the internal state machine, pointers and internal buffer.
2580 * | | |The contents of control register will not be cleared.
2581 * | | |This bit will be automatically cleared after one AHB clock cycle.
2582 * |[3:2] |MODE_SEL |PDMA Mode Selection
2583 * | | |00 = Memory to Memory mode (Memory-to-Memory).
2584 * | | |01 = Peripheral to Memory mode (Peripheral-to-Memory).
2585 * | | |10 = Memory to Peripheral mode (Memory-to-Peripheral).
2586 * |[5:4] |SAD_SEL |Transfer Source Address Direction Selection
2587 * | | |00 = Transfer source address is increasing successively.
2588 * | | |01 = Reserved.
2589 * | | |10 = Transfer source address is fixed (This feature can be used when data where transferred from a single source to multiple destinations).
2590 * | | |11 = Reserved.
2591 * |[7:6] |DAD_SEL |Transfer Destination Address Direction Selection
2592 * | | |00 = Transfer destination address is increasing successively.
2593 * | | |01 = Reserved.
2594 * | | |10 = Transfer destination address is fixed.
2595 * | | |(This feature can be used when data where transferred from multiple sources to a single destination).
2596 * | | |11 = Reserved.
2597 * |[20:19] |APB_TWS |Peripheral Transfer Width Selection
2598 * | | |00 = One word (32-bit) is transferred for every PDMA operation.
2599 * | | |01 = One byte (8-bit) is transferred for every PDMA operation.
2600 * | | |10 = One half-word (16-bit) is transferred for every PDMA operation.
2601 * | | |11 = Reserved.
2602 * | | |Note: This field is meaningful only when MODE_SEL (PDMA_CSRx[3:2]) is Peripheral to Memory mode (Peripheral-to-Memory) or Memory to Peripheral mode (Memory-to-Peripheral).
2603 * |[23] |TRIG_EN |Trigger Enable Bit
2604 * | | |0 = No effect.
2605 * | | |1 = PDMA data read or write transfer Enabled.
2606 * | | |Note1: When PDMA transfer completed, this bit will be cleared automatically.
2607 * | | |Note2: If the bus error occurs, all PDMA transfer will be stopped.
2608 * | | |Software must reset all PDMA channel, and then trigger again.
2609 * @var PDMA_T::SAR
2610 * Offset: 0x04 PDMA Channel x Source Address Register
2611 * ---------------------------------------------------------------------------------------------------
2612 * |Bits |Field |Descriptions
2613 * | :----: | :----: | :---- |
2614 * |[31:0] |PDMA_SAR |PDMA Transfer Source Address Register
2615 * | | |This field indicates a 32-bit source address of PDMA.
2616 * | | |Note: The source address must be word alignment.
2617 * @var PDMA_T::DAR
2618 * Offset: 0x08 PDMA Channel x Destination Address Register
2619 * ---------------------------------------------------------------------------------------------------
2620 * |Bits |Field |Descriptions
2621 * | :----: | :----: | :---- |
2622 * |[31:0] |PDMA_DAR |PDMA Transfer Destination Address Register
2623 * | | |This field indicates a 32-bit destination address of PDMA.
2624 * | | |Note: The destination address must be word alignment
2625 * @var PDMA_T::BCR
2626 * Offset: 0x0C PDMA Channel x Transfer Byte Count Register
2627 * ---------------------------------------------------------------------------------------------------
2628 * |Bits |Field |Descriptions
2629 * | :----: | :----: | :---- |
2630 * |[15:0] |PDMA_BCR |PDMA Transfer Byte Count Register
2631 * | | |This field indicates a 16-bit transfer byte count number of PDMA; it must be word alignment.
2632 * @var PDMA_T::POINT
2633 * Offset: 0x10 PDMA Channel x Internal buffer pointer Register
2634 * ---------------------------------------------------------------------------------------------------
2635 * |Bits |Field |Descriptions
2636 * | :----: | :----: | :---- |
2637 * |[3:0] |PDMA_POINT|PDMA Internal Buffer Pointer Register (Read Only)
2638 * | | |This field indicates the internal buffer pointer.
2639 * @var PDMA_T::CSAR
2640 * Offset: 0x14 PDMA Channel x Current Source Address Register
2641 * ---------------------------------------------------------------------------------------------------
2642 * |Bits |Field |Descriptions
2643 * | :----: | :----: | :---- |
2644 * |[31:0] |PDMA_CSAR |PDMA Current Source Address Register (Read Only)
2645 * | | |This field indicates the source address where the PDMA transfer just occurred.
2646 * @var PDMA_T::CDAR
2647 * Offset: 0x18 PDMA Channel x Current Destination Address Register
2648 * ---------------------------------------------------------------------------------------------------
2649 * |Bits |Field |Descriptions
2650 * | :----: | :----: | :---- |
2651 * |[31:0] |PDMA_CDAR |PDMA Current Destination Address Register (Read Only)
2652 * | | |This field indicates the destination address where the PDMA transfer just occurred.
2653 * @var PDMA_T::CBCR
2654 * Offset: 0x1C PDMA Channel x Current Transfer Byte Count Register
2655 * ---------------------------------------------------------------------------------------------------
2656 * |Bits |Field |Descriptions
2657 * | :----: | :----: | :---- |
2658 * |[15:0] |PDMA_CBCR |PDMA Current Byte Count Register (Read Only)
2659 * | | |This field indicates the current remained byte count of PDMA.
2660 * | | |Note: SW_RST will clear this register value.
2661 * @var PDMA_T::IER
2662 * Offset: 0x20 PDMA Channel x Interrupt Enable Register
2663 * ---------------------------------------------------------------------------------------------------
2664 * |Bits |Field |Descriptions
2665 * | :----: | :----: | :---- |
2666 * |[0] |TABORT_IE |PDMA Read/Write Target Abort Interrupt Enable Bit
2667 * | | |0 = Target abort interrupt generation Disabled during PDMA transfer.
2668 * | | |1 = Target abort interrupt generation Enabled during PDMA transfer.
2669 * |[1] |BLKD_IE |PDMA Block Transfer Done Interrupt Enable Bit
2670 * | | |0 = Interrupt generator Disabled when PDMA transfer is done.
2671 * | | |1 = Interrupt generator Enabled when PDMA transfer is done.
2672 * @var PDMA_T::ISR
2673 * Offset: 0x24 PDMA Channel x Interrupt Status Register
2674 * ---------------------------------------------------------------------------------------------------
2675 * |Bits |Field |Descriptions
2676 * | :----: | :----: | :---- |
2677 * |[0] |TABORT_IF |PDMA Read/Write Target Abort Interrupt Flag
2678 * | | |This bit can be cleared to 0 by software writing '1'.
2679 * | | |0 = No bus ERROR response received.
2680 * | | |1 = Bus ERROR response received.
2681 * | | |Note: This bit filed indicates bus master received ERROR response or not.
2682 * | | |If bus master received ERROR response, it means that target abort is happened.
2683 * | | |PDMA controller will stop transfer and respond this event to software then goes to IDLE state.
2684 * | | |When target abort occurred, software must reset PDMA, and then transfer those data again.
2685 * |[1] |BLKD_IF |PDMA Block Transfer Done Interrupt Flag
2686 * | | |This bit indicates that PDMA has finished all transfers. This bit can be cleared to 0 by software writing '1'
2687 * | | |0 = Not finished.
2688 * | | |1 = Done.
2689 * @var PDMA_T::SBUF
2690 * Offset: 0x80 PDMA Channel x Shared Buffer FIFO x Register
2691 * ---------------------------------------------------------------------------------------------------
2692 * |Bits |Field |Descriptions
2693 * | :----: | :----: | :---- |
2694 * |[31:0] |PDMA_SBUF0|PDMA Shared Buffer FIFO 0 (Read Only)
2695 * | | |Each channel has its own 1 word internal buffer.
2696 */
2697
2698 __IO uint32_t CSR; /* Offset: 0x00 PDMA Channel x Control Register */
2699 __IO uint32_t SAR; /* Offset: 0x04 PDMA Channel x Source Address Register */
2700 __IO uint32_t DAR; /* Offset: 0x08 PDMA Channel x Destination Address Register */
2701 __IO uint32_t BCR; /* Offset: 0x0C PDMA Channel x Transfer Byte Count Register */
2702 __I uint32_t POINT; /* Offset: 0x10 PDMA Channel x Internal buffer pointer Register */
2703 __I uint32_t CSAR; /* Offset: 0x14 PDMA Channel x Current Source Address Register */
2704 __I uint32_t CDAR; /* Offset: 0x18 PDMA Channel x Current Destination Address Register */
2705 __I uint32_t CBCR; /* Offset: 0x1C PDMA Channel x Current Transfer Byte Count Register */
2706 __IO uint32_t IER; /* Offset: 0x20 PDMA Channel x Interrupt Enable Register */
2707 __IO uint32_t ISR; /* Offset: 0x24 PDMA Channel x Interrupt Status Register */
2708 __I uint32_t RESERVE[22];
2709 __I uint32_t SBUF; /* Offset: 0x80 PDMA Channel x Shared Buffer FIFO x Register */
2710
2711} PDMA_T;
2712
2713
2714
2715
2716typedef struct
2717{
2718
2719
2720/**
2721 * @var PDMA_GCR_T::GCRCSR
2722 * Offset: 0x00 PDMA Global Control Register
2723 * ---------------------------------------------------------------------------------------------------
2724 * |Bits |Field |Descriptions
2725 * | :----: | :----: | :---- |
2726 * |[8] |CLK0_EN |PDMA Controller Channel 0 Clock Enable Control
2727 * | | |0 = CRC controller clock Disabled.
2728 * | | |1 = CRC controller clock Enabled.
2729 * |[9] |CLK1_EN |PDMA Controller Channel 1 Clock Enable Control
2730 * | | |0 = PDMA channel 1 clock Disabled.
2731 * | | |1 = PDMA channel 1 clock Enabled.
2732 * |[10] |CLK2_EN |PDMA Controller Channel 2 Clock Enable Control
2733 * | | |0 = PDMA channel 2 clock Disabled.
2734 * | | |1 = PDMA channel 2 clock Enabled.
2735 * |[11] |CLK3_EN |PDMA Controller Channel 3 Clock Enable Control
2736 * | | |0 = PDMA channel 3 clock Disabled.
2737 * | | |1 = PDMA channel 3 clock Enabled.
2738 * |[12] |CLK4_EN |PDMA Controller Channel 4 Clock Enable Control
2739 * | | |0 = PDMA channel 4 clock Disabled.
2740 * | | |1 = PDMA channel 4 clock Enabled.
2741 * |[13] |CLK5_EN |PDMA Controller Channel 5 Clock Enable Control
2742 * | | |0 = PDMA channel 5 clock Disabled.
2743 * | | |1 = PDMA channel 5 clock Enabled.
2744 * |[24] |CRC_CLK_EN|CRC Controller Clock Enable Control
2745 * | | |0 = CRC controller clock Disabled.
2746 * | | |1 = CRC controller clock Enabled.
2747 * @var PDMA_GCR_T::PDSSR0
2748 * Offset: 0x04 PDMA Service Selection Control Register 0
2749 * ---------------------------------------------------------------------------------------------------
2750 * |Bits |Field |Descriptions
2751 * | :----: | :----: | :---- |
2752 * |[3:0] |SPI0_RXSEL|PDMA SPI0 RX Selection
2753 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI0 RX.
2754 * | | |Software can change the channel RX setting by SPI0_RXSEL.
2755 * | | |0000: CH0
2756 * | | |0001: CH1
2757 * | | |0010: CH2
2758 * | | |0011: CH3
2759 * | | |0100: CH4
2760 * | | |0101: CH5
2761 * | | |Others : Reserved
2762 * | | |Note: For example, SPI0_RXSEL = 0100, that means SPI0_RX is connected to PDMA_CH4.
2763 * |[7:4] |SPI0_TXSEL|PDMA SPI0 TX Selection
2764 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI0 TX.
2765 * | | |Software can configure the TX channel setting by SPI0_TXSEL.
2766 * | | |The channel configuration is the same as SPI0_RXSEL field.
2767 * | | |Please refer to the explanation of SPI0_RXSEL.
2768 * |[11:8] |SPI1_RXSEL|PDMA SPI1 RX Selection
2769 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI1 RX.
2770 * | | |Software can configure the RX channel setting by SPI1_RXSEL.
2771 * | | |The channel configuration is the same as SPI0_RXSEL field.
2772 * | | |Please refer to the explanation of SPI0_RXSEL.
2773 * |[15:12] |SPI1_TXSEL|PDMA SPI1 TX Selection
2774 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI1 TX.
2775 * | | |Software can configure the TX channel setting by SPI1_TXSEL.
2776 * | | |The channel configuration is the same as SPI0_RXSEL field.
2777 * | | |Please refer to the explanation of SPI0_RXSEL.
2778 * |[19:16] |SPI2_RXSEL|PDMA SPI2 RX Selection
2779 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI2 RX.
2780 * | | |Software can configure the RX channel setting by SPI2_RXSEL.
2781 * | | |The channel configuration is the same as SPI0_RXSEL field.
2782 * | | |Please refer to the explanation of SPI0_RXSEL.
2783 * |[23:20] |SPI2_TXSEL|PDMA SPI2 TX Selection
2784 * | | |This field defines which PDMA channel is connected to the on-chip peripheral SPI2 TX.
2785 * | | |Software can configure the TX channel setting by SPI2_TXSEL.
2786 * | | |The channel configuration is the same as SPI0_RXSEL field.
2787 * | | |Please refer to the explanation of SPI0_RXSEL.
2788 * @var PDMA_GCR_T::PDSSR1
2789 * Offset: 0x08 PDMA Service Selection Control Register 1
2790 * ---------------------------------------------------------------------------------------------------
2791 * |Bits |Field |Descriptions
2792 * | :----: | :----: | :---- |
2793 * |[3:0] |UART0_RXSEL|PDMA UART0 RX Selection
2794 * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART0 RX.
2795 * | | |Software can change the channel RX setting by UART0_RXSEL.
2796 * | | |0000: CH0
2797 * | | |0001: CH1
2798 * | | |0010: CH2
2799 * | | |0011: CH3
2800 * | | |0100: CH4
2801 * | | |0101: CH5
2802 * | | |Others : Reserved
2803 * | | |Note: For example, UART0_RXSEL = 0100, which means UART0_RX is connected to PDMA_CH4.
2804 * |[7:4] |UART0_TXSEL|PDMA UART0 TX Selection
2805 * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART0 TX.
2806 * | | |Software can configure the TX channel setting by UART0_TXSEL.
2807 * | | |The channel configuration is the same as UART0_RXSEL field.
2808 * | | |Please refer to the explanation of UART0_RXSEL.
2809 * |[11:8] |UART1_RXSEL|PDMA UART1 RX Selection
2810 * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART1 RX.
2811 * | | |Software can configure the RX channel setting by UART1_RXSEL.
2812 * | | |The channel configuration is the same as UART0_RXSEL field.
2813 * | | |Please refer to the explanation of UART0_RXSEL.
2814 * |[15:12] |UART1_TXSEL|PDMA UART1 TX Selection
2815 * | | |This field defines which PDMA channel is connected to the on-chip peripheral UART1 TX.
2816 * | | |Software can configure the TX channel setting by UART1_TXSEL.
2817 * | | |The channel configuration is the same as UART0_RXSEL field.
2818 * | | |Please refer to the explanation of UART0_RXSEL.
2819 * |[27:24] |ADC_RXSEL |PDMA ADC RX Selection
2820 * | | |This field defines which PDMA channel is connected to the on-chip peripheral ADC RX.
2821 * | | |Software can configure the RX channel setting by ADC_RXSEL.
2822 * | | |The channel configuration is the same as UART0_RXSEL field.
2823 * | | |Please refer to the explanation of UART0_RXSEL.
2824 * @var PDMA_GCR_T::GCRISR
2825 * Offset: 0x0C PDMA Global Interrupt Status Register
2826 * ---------------------------------------------------------------------------------------------------
2827 * |Bits |Field |Descriptions
2828 * | :----: | :----: | :---- |
2829 * |[0] |INTR0 |Interrupt Status Of Channel 0
2830 * | | |This bit is the interrupt status of PDMA channel 0.
2831 * | | |Note: This bit is read only
2832 * |[1] |INTR1 |Interrupt Status Of Channel 1
2833 * | | |This bit is the interrupt status of PDMA channel 1.
2834 * | | |Note: This bit is read only
2835 * |[2] |INTR2 |Interrupt Status Of Channel 2
2836 * | | |This bit is the interrupt status of PDMA channel 2.
2837 * | | |Note: This bit is read only
2838 * |[3] |INTR3 |Interrupt Status Of Channel 3
2839 * | | |This bit is the interrupt status of PDMA channel 3.
2840 * | | |Note: This bit is read only
2841 * |[4] |INTR4 |Interrupt Status Of Channel 4
2842 * | | |This bit is the interrupt status of PDMA channel 4.
2843 * | | |Note: This bit is read only
2844 * |[5] |INTR5 |Interrupt Status Of Channel 5
2845 * | | |This bit is the interrupt status of PDMA channel 5.
2846 * | | |Note: This bit is read only
2847 * |[16] |INTRCRC |Interrupt Status Of CRC Controller
2848 * | | |This bit is the interrupt status of CRC controller
2849 * | | |Note: This bit is read only
2850 * |[31] |INTR |Interrupt Status
2851 * | | |This bit is the interrupt status of PDMA controller.
2852 * | | |Note: This bit is read only
2853 * @var PDMA_GCR_T::PDSSR2
2854 * Offset: 0x10 PDMA Service Selection Control Register 2
2855 * ---------------------------------------------------------------------------------------------------
2856 * |Bits |Field |Descriptions
2857 * | :----: | :----: | :---- |
2858 * |[3:0] |I2S_RXSEL |PDMA I2S RX Selection
2859 * | | |This field defines which PDMA channel is connected to the on-chip peripheral I2S RX.
2860 * | | |Software can change the channel RX setting by I2S_RXSEL.
2861 * | | |0000: CH0
2862 * | | |0001: CH1
2863 * | | |0010: CH2
2864 * | | |0011: CH3
2865 * | | |0100: CH4
2866 * | | |0101: CH5
2867 * | | |Others : Reserved
2868 * | | |Note: For example: I2S_RXSEL (PDMA_PDSSR2[3:0]) = 0100, that means I2S_RX is connected to PDMA_CH4.
2869 * |[7:4] |I2S_TXSEL |PDMA I2S TX Selection
2870 * | | |This field defines which PDMA channel is connected to the on-chip peripheral I2S TX.
2871 * | | |Software can configure the TX channel setting by I2S_TXSEL.
2872 * | | |The channel configuration is the same as I2S_RXSEL field.
2873 * | | |Please refer to the explanation of I2S_RXSEL.
2874 * |[11:8] |PWM0_RXSEL|PDMA PWM0 RX Selection
2875 * | | |This filed defines which PDMA channel is connected to the on-chip peripheral PWM0 RX.
2876 * | | |Software can configure the RX channel setting by PWM0_RXSEL.
2877 * | | |The channel configuration is the same as I2S_RXSEL field.
2878 * | | |Please refer to the explanation of I2S_RXSEL.
2879 * |[15:12] |PWM1_RXSEL|PDMA PWM1 RX Selection
2880 * | | |This filed defines which PDMA channel is connected to the on-chip peripheral PWM1 RX.
2881 * | | |Software can configure the RX channel setting by PWM1_RXSEL.
2882 * | | |The channel configuration is the same as I2S_RXSEL field.
2883 * | | |Please refer to the explanation of I2S_RXSEL.
2884 * |[19:16] |PWM2_RXSEL|PDMA PWM2 RX Selection
2885 * | | |This field defines which PDMA channel is connected to the on-chip peripheral PWM2 RX.
2886 * | | |Software can configure the RX channel setting by PWM2_RXSEL.
2887 * | | |The channel configuration is the same as I2S_RXSEL field.
2888 * | | |Please refer to the explanation of I2S_RXSEL.
2889 * |[23:20] |PWM3_RXSEL|PDMA PWM3 RX Selection
2890 * | | |This field defines which PDMA channel is connected to the on-chip peripheral PWM3 RX.
2891 * | | |Software can configure the RX channel setting by PWM3_RXSEL.
2892 * | | |The channel configuration is the same as I2S_RXSEL field.
2893 * | | |Please refer to the explanation of I2S_RXSEL.
2894 */
2895
2896 __IO uint32_t GCRCSR; /* Offset: 0x00 PDMA Global Control Register */
2897 __IO uint32_t PDSSR0; /* Offset: 0x04 PDMA Service Selection Control Register 0 */
2898 __IO uint32_t PDSSR1; /* Offset: 0x08 PDMA Service Selection Control Register 1 */
2899 __IO uint32_t GCRISR; /* Offset: 0x0C PDMA Global Interrupt Status Register */
2900 __IO uint32_t PDSSR2; /* Offset: 0x10 PDMA Service Selection Control Register 2 */
2901
2902} PDMA_GCR_T;
2903
2904
2905
2906
2907/** @addtogroup REG_PDMA_BITMASK PDMA Bit Mask
2908 @{
2909 */
2910
2911/* PDMA CSR Bit Field Definitions */
2912#define PDMA_CSR_TRIG_EN_Pos 23 /*!< PDMA_T::CSR: TRIG_EN Position */
2913#define PDMA_CSR_TRIG_EN_Msk (1ul << PDMA_CSR_TRIG_EN_Pos) /*!< PDMA_T::CSR: TRIG_EN Mask */
2914
2915#define PDMA_CSR_APB_TWS_Pos 19 /*!< PDMA_T::CSR: APB_TWS Position */
2916#define PDMA_CSR_APB_TWS_Msk (3ul << PDMA_CSR_APB_TWS_Pos) /*!< PDMA_T::CSR: APB_TWS Mask */
2917
2918#define PDMA_CSR_DAD_SEL_Pos 6 /*!< PDMA_T::CSR: DAD_SEL Position */
2919#define PDMA_CSR_DAD_SEL_Msk (3ul << PDMA_CSR_DAD_SEL_Pos) /*!< PDMA_T::CSR: DAD_SEL Mask */
2920
2921#define PDMA_CSR_SAD_SEL_Pos 4 /*!< PDMA_T::CSR: SAD_SEL Position */
2922#define PDMA_CSR_SAD_SEL_Msk (3ul << PDMA_CSR_SAD_SEL_Pos) /*!< PDMA_T::CSR: SAD_SEL Mask */
2923
2924#define PDMA_CSR_MODE_SEL_Pos 2 /*!< PDMA_T::CSR: MODE_SEL Position */
2925#define PDMA_CSR_MODE_SEL_Msk (3ul << PDMA_CSR_MODE_SEL_Pos) /*!< PDMA_T::CSR: MODE_SEL Mask */
2926
2927#define PDMA_CSR_SW_RST_Pos 1 /*!< PDMA_T::CSR: SW_RST Position */
2928#define PDMA_CSR_SW_RST_Msk (1ul << PDMA_CSR_SW_RST_Pos) /*!< PDMA_T::CSR: SW_RST Mask */
2929
2930#define PDMA_CSR_PDMACEN_Pos 0 /*!< PDMA_T::CSR: PDMACEN Position */
2931#define PDMA_CSR_PDMACEN_Msk (1ul << PDMA_CSR_PDMACEN_Pos) /*!< PDMA_T::CSR: PDMACEN Mask */
2932
2933/* PDMA BCR Bit Field Definitions */
2934#define PDMA_BCR_BCR_Pos 0 /*!< PDMA_T::BCR: BCR Position */
2935#define PDMA_BCR_BCR_Msk (0xFFFFul << PDMA_BCR_BCR_Pos) /*!< PDMA_T::BCR: BCR Mask */
2936
2937/* PDMA POINT Bit Field Definitions */
2938#define PDMA_POINT_POINT_Pos 0 /*!< PDMA_T::POINT: POINT Position */
2939#define PDMA_POINT_POINT_Msk (0xFul << PDMA_POINT_POINT_Pos) /*!< PDMA_T::POINT: POINT Mask */
2940
2941/* PDMA CBCR Bit Field Definitions */
2942#define PDMA_CBCR_CBCR_Pos 0 /*!< PDMA_T::CBCR: CBCR Position */
2943#define PDMA_CBCR_CBCR_Msk (0xFFFFul << PDMA_CBCR_CBCR_Pos) /*!< PDMA_T::CBCR: CBCR Mask */
2944
2945/* PDMA IER Bit Field Definitions */
2946#define PDMA_IER_BLKD_IE_Pos 1 /*!< PDMA_T::IER: BLKD_IE Position */
2947#define PDMA_IER_BLKD_IE_Msk (1ul << PDMA_IER_BLKD_IE_Pos) /*!< PDMA_T::IER: BLKD_IE Mask */
2948
2949#define PDMA_IER_TABORT_IE_Pos 0 /*!< PDMA_T::IER: TABORT_IE Position */
2950#define PDMA_IER_TABORT_IE_Msk (1ul << PDMA_IER_TABORT_IE_Pos) /*!< PDMA_T::IER: TABORT_IE Mask */
2951
2952/* PDMA ISR Bit Field Definitions */
2953#define PDMA_ISR_BLKD_IF_Pos 1 /*!< PDMA_T::ISR: BLKD_IF Position */
2954#define PDMA_ISR_BLKD_IF_Msk (1ul << PDMA_ISR_BLKD_IF_Pos) /*!< PDMA_T::ISR: BLKD_IF Mask */
2955
2956#define PDMA_ISR_TABORT_IF_Pos 0 /*!< PDMA_T::ISR: TABORT_IF Position */
2957#define PDMA_ISR_TABORT_IF_Msk (1ul << PDMA_ISR_TABORT_IF_Pos) /*!< PDMA_T::ISR: TABORT_IF Mask */
2958
2959/* PDMA GCRCSR Bit Field Definitions */
2960#define PDMA_GCRCSR_CRC_CLK_EN_Pos 24 /*!< PDMA_GCR_T::GCRCSR: CRC_CLK_EN Position */
2961#define PDMA_GCRCSR_CRC_CLK_EN_Msk (1ul << PDMA_GCRCSR_CRC_CLK_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CRC_CLK_EN Mask */
2962
2963#define PDMA_GCRCSR_CLK5_EN_Pos 13 /*!< PDMA_GCR_T::GCRCSR: CLK5_EN Position */
2964#define PDMA_GCRCSR_CLK5_EN_Msk (1ul << PDMA_GCRCSR_CLK5_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK5_EN Mask */
2965
2966#define PDMA_GCRCSR_CLK4_EN_Pos 12 /*!< PDMA_GCR_T::GCRCSR: CLK4_EN Position */
2967#define PDMA_GCRCSR_CLK4_EN_Msk (1ul << PDMA_GCRCSR_CLK4_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK4_EN Mask */
2968
2969#define PDMA_GCRCSR_CLK3_EN_Pos 11 /*!< PDMA_GCR_T::GCRCSR: CLK3_EN Position */
2970#define PDMA_GCRCSR_CLK3_EN_Msk (1ul << PDMA_GCRCSR_CLK3_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK3_EN Mask */
2971
2972#define PDMA_GCRCSR_CLK2_EN_Pos 10 /*!< PDMA_GCR_T::GCRCSR: CLK2_EN Position */
2973#define PDMA_GCRCSR_CLK2_EN_Msk (1ul << PDMA_GCRCSR_CLK2_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK2_EN Mask */
2974
2975#define PDMA_GCRCSR_CLK1_EN_Pos 9 /*!< PDMA_GCR_T::GCRCSR: CLK1_EN Position */
2976#define PDMA_GCRCSR_CLK1_EN_Msk (1ul << PDMA_GCRCSR_CLK1_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK1_EN Mask */
2977
2978#define PDMA_GCRCSR_CLK0_EN_Pos 8 /*!< PDMA_GCR_T::GCRCSR: CLK0_EN Position */
2979#define PDMA_GCRCSR_CLK0_EN_Msk (1ul << PDMA_GCRCSR_CLK0_EN_Pos) /*!< PDMA_GCR_T::GCRCSR: CLK0_EN Mask */
2980
2981/* PDMA PDSSR0 Bit Field Definitions */
2982#define PDMA_PDSSR0_SPI2_TXSEL_Pos 20 /*!< PDMA_GCR_T::PDSSR0: SPI2_TXSEL Position */
2983#define PDMA_PDSSR0_SPI2_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI2_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI2_TXSEL Mask */
2984
2985#define PDMA_PDSSR0_SPI2_RXSEL_Pos 16 /*!< PDMA_GCR_T::PDSSR0: SPI2_RXSEL Position */
2986#define PDMA_PDSSR0_SPI2_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI2_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI2_RXSEL Mask */
2987
2988#define PDMA_PDSSR0_SPI1_TXSEL_Pos 12 /*!< PDMA_GCR_T::PDSSR0: SPI1_TXSEL Position */
2989#define PDMA_PDSSR0_SPI1_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI1_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI1_TXSEL Mask */
2990
2991#define PDMA_PDSSR0_SPI1_RXSEL_Pos 8 /*!< PDMA_GCR_T::PDSSR0: SPI1_RXSEL Position */
2992#define PDMA_PDSSR0_SPI1_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI1_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI1_RXSEL Mask */
2993
2994#define PDMA_PDSSR0_SPI0_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR0: SPI0_TXSEL Position */
2995#define PDMA_PDSSR0_SPI0_TXSEL_Msk (0xFul << PDMA_PDSSR0_SPI0_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI0_TXSEL Mask */
2996
2997#define PDMA_PDSSR0_SPI0_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR0: SPI0_RXSEL Position */
2998#define PDMA_PDSSR0_SPI0_RXSEL_Msk (0xFul << PDMA_PDSSR0_SPI0_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR0: SPI0_RXSEL Mask */
2999
3000/* PDMA PDSSR1 Bit Field Definitions */
3001#define PDMA_PDSSR1_ADC_RXSEL_Pos 24 /*!< PDMA_GCR_T::PDSSR1: ADC_RXSEL Position */
3002#define PDMA_PDSSR1_ADC_RXSEL_Msk (0xFul << PDMA_PDSSR1_ADC_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: ADC_RXSEL Mask */
3003
3004#define PDMA_PDSSR1_UART1_TXSEL_Pos 12 /*!< PDMA_GCR_T::PDSSR1: UART1_TXSEL Position */
3005#define PDMA_PDSSR1_UART1_TXSEL_Msk (0xFul << PDMA_PDSSR1_UART1_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART1_TXSEL Mask */
3006
3007#define PDMA_PDSSR1_UART1_RXSEL_Pos 8 /*!< PDMA_GCR_T::PDSSR1: UART1_RXSEL Position */
3008#define PDMA_PDSSR1_UART1_RXSEL_Msk (0xFul << PDMA_PDSSR1_UART1_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART1_RXSEL Mask */
3009
3010#define PDMA_PDSSR1_UART0_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR1: UART0_TXSEL Position */
3011#define PDMA_PDSSR1_UART0_TXSEL_Msk (0xFul << PDMA_PDSSR1_UART0_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART0_TXSEL Mask */
3012
3013#define PDMA_PDSSR1_UART0_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR1: UART0_RXSEL Position */
3014#define PDMA_PDSSR1_UART0_RXSEL_Msk (0xFul << PDMA_PDSSR1_UART0_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR1: UART0_RXSEL Mask */
3015
3016/* PDMA GCRISR Bit Field Definitions */
3017#define PDMA_GCRISR_INTR_Pos 31 /*!< PDMA_GCR_T::GCRISR: INTR Position */
3018#define PDMA_GCRISR_INTR_Msk (1ul << PDMA_GCRISR_INTR_Pos) /*!< PDMA_GCR_T::GCRISR: INTR Mask */
3019
3020#define PDMA_GCRISR_INTRCRC_Pos 16 /*!< PDMA_GCR_T::GCRISR: INTRCRC Position */
3021#define PDMA_GCRISR_INTRCRC_Msk (1ul << PDMA_GCRISR_INTRCRC_Pos) /*!< PDMA_GCR_T::GCRISR: INTRCRC Mask */
3022
3023#define PDMA_GCRISR_INTR5_Pos 5 /*!< PDMA_GCR_T::GCRISR: INTR5 Position */
3024#define PDMA_GCRISR_INTR5_Msk (1ul << PDMA_GCRISR_INTR5_Pos) /*!< PDMA_GCR_T::GCRISR: INTR5 Mask */
3025
3026#define PDMA_GCRISR_INTR4_Pos 4 /*!< PDMA_GCR_T::GCRISR: INTR4 Position */
3027#define PDMA_GCRISR_INTR4_Msk (1ul << PDMA_GCRISR_INTR4_Pos) /*!< PDMA_GCR_T::GCRISR: INTR4 Mask */
3028
3029#define PDMA_GCRISR_INTR3_Pos 3 /*!< PDMA_GCR_T::GCRISR: INTR3 Position */
3030#define PDMA_GCRISR_INTR3_Msk (1ul << PDMA_GCRISR_INTR3_Pos) /*!< PDMA_GCR_T::GCRISR: INTR3 Mask */
3031
3032#define PDMA_GCRISR_INTR2_Pos 2 /*!< PDMA_GCR_T::GCRISR: INTR2 Position */
3033#define PDMA_GCRISR_INTR2_Msk (1ul << PDMA_GCRISR_INTR2_Pos) /*!< PDMA_GCR_T::GCRISR: INTR2 Mask */
3034
3035#define PDMA_GCRISR_INTR1_Pos 1 /*!< PDMA_GCR_T::GCRISR: INTR1 Position */
3036#define PDMA_GCRISR_INTR1_Msk (1ul << PDMA_GCRISR_INTR1_Pos) /*!< PDMA_GCR_T::GCRISR: INTR1 Mask */
3037
3038#define PDMA_GCRISR_INTR0_Pos 0 /*!< PDMA_GCR_T::GCRISR: INTR0 Position */
3039#define PDMA_GCRISR_INTR0_Msk (1ul << PDMA_GCRISR_INTR0_Pos) /*!< PDMA_GCR_T::GCRISR: INTR0 Mask */
3040
3041/* PDMA PDSSR2 Bit Field Definitions */
3042#define PDMA_PDSSR2_PWM3_RXSEL_Pos 20 /*!< PDMA_GCR_T::PDSSR2: PWM3_RXSEL Position */
3043#define PDMA_PDSSR2_PWM3_RXSEL_Msk (0xFul << PDMA_PDSSR2_PWM3_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: PWM3_RXSEL Mask */
3044
3045#define PDMA_PDSSR2_PWM2_RXSEL_Pos 16 /*!< PDMA_GCR_T::PDSSR2: PWM2_RXSEL Position */
3046#define PDMA_PDSSR2_PWM2_RXSEL_Msk (0xFul << PDMA_PDSSR2_PWM2_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: PWM2_RXSEL Mask */
3047
3048#define PDMA_PDSSR2_PWM1_RXSEL_Pos 12 /*!< PDMA_GCR_T::PDSSR2: PWM1_RXSEL Position */
3049#define PDMA_PDSSR2_PWM1_RXSEL_Msk (0xFul << PDMA_PDSSR2_PWM1_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: PWM1_RXSEL Mask */
3050
3051#define PDMA_PDSSR2_PWM0_RXSEL_Pos 8 /*!< PDMA_GCR_T::PDSSR2: PWM0_RXSEL Position */
3052#define PDMA_PDSSR2_PWM0_RXSEL_Msk (0xFul << PDMA_PDSSR2_PWM0_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: PWM0_RXSEL Mask */
3053
3054#define PDMA_PDSSR2_I2S_TXSEL_Pos 4 /*!< PDMA_GCR_T::PDSSR2: I2S_TXSEL Position */
3055#define PDMA_PDSSR2_I2S_TXSEL_Msk (0xFul << PDMA_PDSSR2_I2S_TXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: I2S_TXSEL Mask */
3056
3057#define PDMA_PDSSR2_I2S_RXSEL_Pos 0 /*!< PDMA_GCR_T::PDSSR2: I2S_RXSEL Position */
3058#define PDMA_PDSSR2_I2S_RXSEL_Msk (0xFul << PDMA_PDSSR2_I2S_RXSEL_Pos) /*!< PDMA_GCR_T::PDSSR2: I2S_RXSEL Mask */
3059/*@}*/ /* end of group REG_PDMA_BITMASK */
3060/*@}*/ /* end of group REG_PDMA */
3061
3062
3063/*------------------------------ PS2 Controller ------------------------------*/
3064/** @addtogroup REG_PS2 PS2 Serial Interface (PS2)
3065 Memory Mapped Structure for PS2 Serial Interface Controller
3066 @{
3067 */
3068
3069typedef struct
3070{
3071
3072
3073/**
3074 * @var PS2_T::PS2CON
3075 * Offset: 0x00 PS/2 Control Register
3076 * ---------------------------------------------------------------------------------------------------
3077 * |Bits |Field |Descriptions
3078 * | :----: | :----: | :---- |
3079 * |[0] |PS2EN |Enable PS/2 Device
3080 * | | |Enable PS/2 device controller
3081 * | | |0 = Disabled.
3082 * | | |1 = Enabled.
3083 * |[1] |TXINTEN |Enable Transmit Interrupt
3084 * | | |0 = Data transmit complete interrupt Disabled.
3085 * | | |1 = Data transmit complete interrupt Enabled.
3086 * |[2] |RXINTEN |Enable Receive Interrupt
3087 * | | |0 = Data receive complete interrupt Disabled.
3088 * | | |1 = Data receive complete interrupt Enabled.
3089 * |[6:3] |TXFIFO_DEPTH|Transmit Data FIFO Depth
3090 * | | |There are 16 bytes buffer for data transmit.
3091 * | | |Software can define the FIFO depth from 1 to 16 bytes depends on application needs.
3092 * | | |0 = 1 byte.
3093 * | | |1 = 2 bytes.
3094 * | | |...
3095 * | | |14 = 15 bytes.
3096 * | | |15 = 16 bytes.
3097 * |[7] |ACK |Acknowledge Enable
3098 * | | |0 = Always send acknowledge to host at 12th clock for host to device communication.
3099 * | | |1 = If parity bit error or stop bit is not received correctly, acknowledge bit will not be sent to host at 12th clock.
3100 * |[8] |CLRFIFO |Clear TX FIFO
3101 * | | |Write 1 to this bit to terminate device to host transmission.
3102 * | | |The TXEMPTY(PS2STATUS[7]) bit will be set to 1 and pointer BYTEIDEX(PS2STATUS[11:8]) is reset to 0 regardless there is residue data in buffer or not.
3103 * | | |The buffer content is not been cleared.
3104 * | | |0 = Not active.
3105 * | | |1 = Clear FIFO.
3106 * |[9] |OVERRIDE |Software Override PS/2 CLK/DATA Pin State
3107 * | | |0 = PS2_CLK and PS2_DATA pins are controlled by internal state machine.
3108 * | | |1 = PS2_CLK and PS2_DATA pins are controlled by software.
3109 * |[10] |FPS2CLK |Force PS2CLK Line
3110 * | | |It forces PS2_CLK line high or low regardless of the internal state of the device controller if OVERRIDE(PS2CON[9]) is set to 1.
3111 * | | |0 = Force PS2_CLK line low.
3112 * | | |1 = Force PS2_CLK line high.
3113 * |[11] |FPS2DAT |Force PS2DATA Line
3114 * | | |It forces PS2_DATA high or low regardless of the internal state of the device controller if OVERRIDE (PS2CON[9]) is set to 1.
3115 * | | |0 = Force PS2_DATA low.
3116 * | | |1 = Force PS2_DATA high.
3117 * @var PS2_T::PS2TXDATA0
3118 * Offset: 0x04 PS/2 Transmit Data Register 0
3119 * ---------------------------------------------------------------------------------------------------
3120 * |Bits |Field |Descriptions
3121 * | :----: | :----: | :---- |
3122 * |[31:0] |PS2TXDATAx|Transmit Data
3123 * | | |Writing data to this register starts in device to host communication if bus is in IDLE state.
3124 * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer.
3125 * @var PS2_T::PS2TXDATA1
3126 * Offset: 0x08 PS/2 Transmit Data Register 1
3127 * ---------------------------------------------------------------------------------------------------
3128 * |Bits |Field |Descriptions
3129 * | :----: | :----: | :---- |
3130 * |[31:0] |PS2TXDATAx|Transmit Data
3131 * | | |Writing data to this register starts in device to host communication if bus is in IDLE state.
3132 * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer.
3133 * @var PS2_T::PS2TXDATA2
3134 * Offset: 0x0C PS/2 Transmit Data Register 2
3135 * ---------------------------------------------------------------------------------------------------
3136 * |Bits |Field |Descriptions
3137 * | :----: | :----: | :---- |
3138 * |[31:0] |PS2TXDATAx|Transmit Data
3139 * | | |Writing data to this register starts in device to host communication if bus is in IDLE state.
3140 * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer.
3141 * @var PS2_T::PS2TXDATA3
3142 * Offset: 0x10 PS/2 Transmit Data Register 3
3143 * ---------------------------------------------------------------------------------------------------
3144 * |Bits |Field |Descriptions
3145 * | :----: | :----: | :---- |
3146 * |[31:0] |PS2TXDATAx|Transmit Data
3147 * | | |Writing data to this register starts in device to host communication if bus is in IDLE state.
3148 * | | |Software must enable PS2EN(PS2CON[0]) before writing data to TX buffer.
3149 * @var PS2_T::PS2RXDATA
3150 * Offset: 0x14 PS/2 Receive Data Register
3151 * ---------------------------------------------------------------------------------------------------
3152 * |Bits |Field |Descriptions
3153 * | :----: | :----: | :---- |
3154 * |[7:0] |RXDATA |Received Data
3155 * | | |For host to device communication, after acknowledge bit is sent, the received data is copied from receive shift register to PS2RXDATA register.
3156 * | | |CPU must read this register before next byte reception complete, otherwise the data will be overwritten and RXOVF(PS2STATUS[6]) bit will be set to 1.
3157 * @var PS2_T::PS2STATUS
3158 * Offset: 0x18 PS/2 Status Register
3159 * ---------------------------------------------------------------------------------------------------
3160 * |Bits |Field |Descriptions
3161 * | :----: | :----: | :---- |
3162 * |[0] |PS2CLK |CLK Pin State
3163 * | | |This bit reflects the status of the PS2_CLK line after synchronizing.
3164 * |[1] |PS2DATA |DATA Pin State
3165 * | | |This bit reflects the status of the PS2_DATA line after synchronizing and sampling.
3166 * |[2] |FRAMERR |Frame Error
3167 * | | |For host to device communication, this bit sets to 1 if STOP bit (logic 1) is not received.
3168 * | | |If frame error occurs, the PS/2_DATA line may keep at low state after 12th clock.
3169 * | | |At this moment, software overrides PS2_CLK to send clock till PS2_DATA release to high state.
3170 * | | |After that, device sends a "Resend" command to host.
3171 * | | |0 = No frame error.
3172 * | | |1 = Frame error occur.
3173 * | | |Write 1 to clear this bit.
3174 * |[3] |RXPARITY |Received Parity
3175 * | | |This bit reflects the parity bit for the last received data byte (odd parity).
3176 * | | |This bit is read only.
3177 * |[4] |RXBUSY |Receive Busy
3178 * | | |This bit indicates that the PS/2 device is currently receiving data.
3179 * | | |0 = Idle.
3180 * | | |1 = Currently receiving data.
3181 * | | |This bit is read only.
3182 * |[5] |TXBUSY |Transmit Busy
3183 * | | |This bit indicates that the PS/2 device is currently sending data.
3184 * | | |0 = Idle.
3185 * | | |1 = Currently sending data.
3186 * | | |This bit is read only.
3187 * |[6] |RXOVF |RX Buffer Overwrite
3188 * | | |0 = No overwrite.
3189 * | | |1 = Data in PS2RXDATA register is overwritten by new received data.
3190 * | | |Write 1 to clear this bit.
3191 * |[7] |TXEMPTY |TX FIFO Empty
3192 * | | |When software writes data to PS2TXDATA0-3, the TXEMPTY bit is cleared to 0 immediately if PS2EN(PS2CON[0]) is enabled.
3193 * | | |When transmitted data byte number is equal to FIFODEPTH(PS2CON[6:3]) then TXEMPTY bit is set to 1.
3194 * | | |0 = There is data to be transmitted.
3195 * | | |1 = FIFO is empty.
3196 * | | |This bit is read only.
3197 * |[11:8] |BYTEIDX |Byte Index
3198 * | | |It indicates which data byte in transmit data shift register.
3199 * | | |When all data in FIFO is transmitted and it will be cleared to 0.
3200 * | | |This bit is read only.
3201 * | | |BYTEIDX, DATA Transmit , BYTEIDX, DATA Transmit
3202 * | | |0000 , PS2TXDATA0[ 7: 0], 1000 , PS2TXDATA2[ 7: 0],
3203 * | | |0001 , PS2TXDATA0[15: 8], 1001 , PS2TXDATA2[15: 8],
3204 * | | |0010 , PS2TXDATA0[23:16], 1010 , PS2TXDATA2[23:16],
3205 * | | |0011 , PS2TXDATA0[31:24], 1011 , PS2TXDATA2[31:24],
3206 * | | |0100 , PS2TXDATA1[ 7: 0], 1100 , PS2TXDATA3[ 7: 0],
3207 * | | |0101 , PS2TXDATA1[15: 8], 1101 , PS2TXDATA3[15: 8],
3208 * | | |0110 , PS2TXDATA1[23:16], 1110 , PS2TXDATA3[23:16],
3209 * | | |0111 , PS2TXDATA1[31:24], 1111 , PS2TXDATA3[31:24],
3210 * @var PS2_T::PS2INTID
3211 * Offset: 0x1C PS/2 Interrupt Identification Register
3212 * ---------------------------------------------------------------------------------------------------
3213 * |Bits |Field |Descriptions
3214 * | :----: | :----: | :---- |
3215 * |[0] |RXINT |Receive Interrupt
3216 * | | |This bit is set to 1 when acknowledge bit is sent for Host to device communication.
3217 * | | |Interrupt occurs if RXINTEN(PS2CON[2]) bit is set to 1.
3218 * | | |0 = No interrupt.
3219 * | | |1 = Receive interrupt occurs.
3220 * | | |Write 1 to clear this bit to 0.
3221 * |[1] |TXINT |Transmit Interrupt
3222 * | | |This bit is set to 1 after STOP bit is transmitted.
3223 * | | |Interrupt occur if TXINTEN(PS2CON[1]) bit is set to 1.
3224 * | | |0 = No interrupt.
3225 * | | |1 = Transmit interrupt occurs.
3226 * | | |Write 1 to clear this bit to 0.
3227 */
3228
3229 __IO uint32_t PS2CON; /* Offset: 0x00 PS/2 Control Register */
3230 __IO uint32_t PS2TXDATA0; /* Offset: 0x04 PS/2 Transmit Data Register 0 */
3231 __IO uint32_t PS2TXDATA1; /* Offset: 0x08 PS/2 Transmit Data Register 1 */
3232 __IO uint32_t PS2TXDATA2; /* Offset: 0x0C PS/2 Transmit Data Register 2 */
3233 __IO uint32_t PS2TXDATA3; /* Offset: 0x10 PS/2 Transmit Data Register 3 */
3234 __IO uint32_t PS2RXDATA; /* Offset: 0x14 PS/2 Receive Data Register */
3235 __IO uint32_t PS2STATUS; /* Offset: 0x18 PS/2 Status Register */
3236 __IO uint32_t PS2INTID; /* Offset: 0x1C PS/2 Interrupt Identification Register */
3237
3238} PS2_T;
3239
3240
3241
3242/** @addtogroup REG_PS2_BITMASK PS2 Bit Mask
3243 @{
3244 */
3245
3246/* PS2 PS2CON Bit Field Definitions */
3247#define PS2_PS2CON_PS2EN_Pos 0 /*!< PS2_T::PS2CON: PS2EN Position */
3248#define PS2_PS2CON_PS2EN_Msk (1ul << PS2_PS2CON_PS2EN_Pos) /*!< PS2_T::PS2CON: PS2EN Mask */
3249
3250#define PS2_PS2CON_TXINTEN_Pos 1 /*!< PS2_T::PS2CON: TXINTEN Position */
3251#define PS2_PS2CON_TXINTEN_Msk (1ul << PS2_PS2CON_TXINTEN_Pos) /*!< PS2_T::PS2CON: TXINTEN Mask */
3252
3253#define PS2_PS2CON_RXINTEN_Pos 2 /*!< PS2_T::PS2CON: RXINTEN Position */
3254#define PS2_PS2CON_RXINTEN_Msk (1ul << PS2_PS2CON_RXINTEN_Pos) /*!< PS2_T::PS2CON: RXINTEN Mask */
3255
3256#define PS2_PS2CON_TXFIFO_DEPTH_Pos 3 /*!< PS2_T::PS2CON: TXFIFO_DEPTH Position */
3257#define PS2_PS2CON_TXFIFO_DEPTH_Msk (0xFul << PS2_PS2CON_TXFIFO_DEPTH_Pos) /*!< PS2_T::PS2CON: TXFIFO_DEPTH Mask */
3258
3259#define PS2_PS2CON_ACK_Pos 7 /*!< PS2_T::PS2CON: ACK Position */
3260#define PS2_PS2CON_ACK_Msk (1ul << PS2_PS2CON_ACK_Pos) /*!< PS2_T::PS2CON: ACK Mask */
3261
3262#define PS2_PS2CON_CLRFIFO_Pos 8 /*!< PS2_T::PS2CON: CLRFIFO Position */
3263#define PS2_PS2CON_CLRFIFO_Msk (1ul << PS2_PS2CON_CLRFIFO_Pos) /*!< PS2_T::PS2CON: CLRFIFO Mask */
3264
3265#define PS2_PS2CON_OVERRIDE_Pos 9 /*!< PS2_T::PS2CON: OVERRIDE Position */
3266#define PS2_PS2CON_OVERRIDE_Msk (1ul << PS2_PS2CON_OVERRIDE_Pos) /*!< PS2_T::PS2CON: OVERRIDE Mask */
3267
3268#define PS2_PS2CON_FPS2CLK_Pos 10 /*!< PS2_T::PS2CON: FPS2CLK Position */
3269#define PS2_PS2CON_FPS2CLK_Msk (1ul << PS2_PS2CON_FPS2CLK_Pos) /*!< PS2_T::PS2CON: FPS2CLK Mask */
3270
3271#define PS2_PS2CON_FPS2DAT_Pos 11 /*!< PS2_T::PS2CON: FPS2DAT Position */
3272#define PS2_PS2CON_FPS2DAT_Msk (1ul << PS2_PS2CON_FPS2DAT_Pos) /*!< PS2_T::PS2CON: FPS2DAT Mask */
3273
3274/* PS/2 PS2RXDATA Bit Field Definitions */
3275#define PS2_PS2RXDATA_RXDATA_Pos 0 /*!< PS2_T::PS2RXDATA: RXDATA Position */
3276#define PS2_PS2RXDATA_RXDATA_Msk (0xFFul << PS2_PS2RXDATA_RXDATA_Pos) /*!< PS2_T::PS2RXDATA: RXDATA Mask */
3277
3278/* PS/2 PS2STATUS Bit Field Definitions */
3279#define PS2_PS2STATUS_PS2CLK_Pos 0 /*!< PS2_T::PS2STATUS: PS2CLK Position */
3280#define PS2_PS2STATUS_PS2CLK_Msk (1ul << PS2_PS2STATUS_PS2CLK_Pos) /*!< PS2_T::PS2STATUS: PS2CLK Mask */
3281
3282#define PS2_PS2STATUS_PS2DATA_Pos 1 /*!< PS2_T::PS2STATUS: PS2DATA Position */
3283#define PS2_PS2STATUS_PS2DATA_Msk (1ul << PS2_PS2STATUS_PS2DATA_Pos) /*!< PS2_T::PS2STATUS: PS2DATA Mask */
3284
3285#define PS2_PS2STATUS_FRAMERR_Pos 2 /*!< PS2_T::PS2STATUS: FRAMERR Position */
3286#define PS2_PS2STATUS_FRAMERR_Msk (1ul << PS2_PS2STATUS_FRAMERR_Pos) /*!< PS2_T::PS2STATUS: FRAMERR Mask */
3287
3288#define PS2_PS2STATUS_RXPARITY_Pos 3 /*!< PS2_T::PS2STATUS: RXPARITY Position */
3289#define PS2_PS2STATUS_RXPARITY_Msk (1ul << PS2_PS2STATUS_RXPARITY_Pos) /*!< PS2_T::PS2STATUS: RXPARITY Mask */
3290
3291#define PS2_PS2STATUS_RXBUSY_Pos 4 /*!< PS2_T::PS2STATUS: RXBUSY Position */
3292#define PS2_PS2STATUS_RXBUSY_Msk (1ul << PS2_PS2STATUS_RXBUSY_Pos) /*!< PS2_T::PS2STATUS: RXBUSY Mask */
3293
3294#define PS2_PS2STATUS_TXBUSY_Pos 5 /*!< PS2_T::PS2STATUS: TXBUSY Position */
3295#define PS2_PS2STATUS_TXBUSY_Msk (1ul << PS2_PS2STATUS_TXBUSY_Pos) /*!< PS2_T::PS2STATUS: TXBUSY Mask */
3296
3297#define PS2_PS2STATUS_RXOVF_Pos 6 /*!< PS2_T::PS2STATUS: RXOVF Position */
3298#define PS2_PS2STATUS_RXOVF_Msk (1ul << PS2_PS2STATUS_RXOVF_Pos) /*!< PS2_T::PS2STATUS: RXOVF Mask */
3299
3300#define PS2_PS2STATUS_TXEMPTY_Pos 7 /*!< PS2_T::PS2STATUS: TXEMPTY Position */
3301#define PS2_PS2STATUS_TXEMPTY_Msk (1ul << PS2_PS2STATUS_TXEMPTY_Pos) /*!< PS2_T::PS2STATUS: TXEMPTY Mask */
3302
3303#define PS2_PS2STATUS_BYTEIDX_Pos 8 /*!< PS2_T::PS2STATUS: BYTEIDX Position */
3304#define PS2_PS2STATUS_BYTEIDX_Msk (0xFul << PS2_PS2STATUS_BYTEIDX_Pos) /*!< PS2_T::PS2STATUS: BYTEIDX Mask */
3305
3306/* PS/2 PS2INTID Bit Field Definitions */
3307#define PS2_PS2INTID_RXINT_Pos 0 /*!< PS2_T::PS2INTID: RXINT Position */
3308#define PS2_PS2INTID_RXINT_Msk (1ul << PS2_PS2INTID_RXINT_Pos) /*!< PS2_T::PS2INTID: RXINT Mask */
3309
3310#define PS2_PS2INTID_TXINT_Pos 1 /*!< PS2_T::PS2INTID: TXINT Position */
3311#define PS2_PS2INTID_TXINT_Msk (1ul << PS2_PS2INTID_TXINT_Pos) /*!< PS2_T::PS2INTID: TXINT Mask */
3312/*@}*/ /* end of group REG_PS2_BITMASK */
3313/*@}*/ /* end of group REG_PS2 */
3314
3315/*----------------------------- PWM Controller -------------------------------*/
3316/** @addtogroup REG_PWM Pulse Width Modulation Controller (PWM)
3317 Memory Mapped Structure for PWM Generator and Capture Timer
3318 @{
3319 */
3320
3321typedef struct
3322{
3323
3324
3325/**
3326 * @var PWM_T::PPR
3327 * Offset: 0x00 PWM Prescaler Register
3328 * ---------------------------------------------------------------------------------------------------
3329 * |Bits |Field |Descriptions
3330 * | :----: | :----: | :---- |
3331 * |[7:0] |CP01 |Clock Prescaler 0 (PWM-Timer 0 / 1 For Group A)
3332 * | | |Clock input is divided by (CP01 + 1) before it is fed to the corresponding PWM-timer
3333 * | | |If CP01=0, then the clock prescaler 0 output clock will be stopped.
3334 * | | |So corresponding PWM-timer will also be stopped.
3335 * |[15:8] |CP23 |Clock Prescaler 2 (PWM-Timer2 / 3 For Group A)
3336 * | | |Clock input is divided by (CP23 + 1) before it is fed to the corresponding PWM-timer
3337 * | | |If CP23=0, then the clock prescaler 2 output clock will be stopped.
3338 * | | |So corresponding PWM-timer will also be stopped.
3339 * |[23:16] |DZI01 |Dead-Zone Interval For Pair Of Channel 0 And Channel 1 (PWM0 And PWM1 Pair For PWM Group A)
3340 * | | |These 8-bit determine the Dead-zone length.
3341 * | | |The unit time of dead-zone length is received from corresponding CSR bits.
3342 * |[31:24] |DZI23 |Dead-Zone Interval For Pair Of Channel2 And Channel3 (PWM2 And PWM3 Pair For PWM Group A)
3343 * | | |These 8-bit determine the Dead-zone length.
3344 * | | |The unit time of dead-zone length is received from corresponding CSR bits.
3345 * @var PWM_T::CSR