1 files changed, 199 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h
new file mode 100644
index 000000000..ba4871636
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2020 Codetector <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+#pragma once
+#if defined(HT32F52342) || defined(HT32F52352)
+    #define HT32F523x2
+#else
+    #error "Unknown HT32 device"
+#endif
+#if defined(HT32F523x2)
+    #define HT32
+#endif
+/*
+ * ==============================================================
+ * ---------- Interrupt Number Definition -----------------------
+ * ==============================================================
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ****************/
+    InitialSP_IRQn                = -16,
+    InitialPC_IRQn                = -15,
+    NonMaskableInt_IRQn           = -14,
+    HardFault_IRQn                = -13,
+    SVCall_IRQn                   = -5,
+    PendSV_IRQn                   = -2,
+    SysTick_IRQn                  = -1,
+/******  HT32F165x Specific Interrupt Numbers ***********************/
+    LVD_IRQn                      = 0,
+    RTC_IRQn                      = 1,
+    FMC_IRQn                      = 2,
+    WKUP_IRQn                     = 3,
+    EXTI0_1_IRQn                  = 4,
+    EXTI2_3_IRQn                  = 5,
+    EXTI4_15_IRQn                 = 6,
+    CMP_IRQn                      = 7,
+    ADC_IRQn                      = 8,
+    MCTM_IRQn                     = 10,
+    GPTM1_IRQn                    = 11,
+    GPTM0_IRQn                    = 12,
+    SCTM0_IRQn                    = 13,
+    SCTM1_IRQn                    = 14,
+    BFTM0_IRQn                    = 17,
+    BFTM1_IRQn                    = 18,
+    I2C0_IRQn                     = 19,
+    I2C1_IRQn                     = 20,
+    SPI0_IRQn                     = 21,
+    SPI1_IRQn                     = 22,
+    USART0_IRQn                   = 23,
+    USART1_IRQn                   = 24,
+    UART0_IRQn                    = 25,
+    UART1_IRQn                    = 26,
+    SCI_IRQn                      = 27,
+    I2S_IRQn                      = 28,
+    USB_IRQn                      = 29,
+    PDMA_CH0_1_IRQn               = 30,
+    PDMA_CH2_5_IRQn               = 31
+} IRQn_Type;
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+/**
+ * @brief HT32F165x Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __FPU_PRESENT           0
+#define __MPU_PRESENT           0
+#define __NVIC_PRIO_BITS        8
+#define __Vendor_SysTickConfig  0
+#include "core_cm0plus.h"           /* Cortex-M0+ processor and core peripherals */
+/****************************************************************/
+/*                  Peripheral memory map                       */
+/****************************************************************/
+#define USART0_BASE             ((uint32_t)0x40000000)
+#define UART0_BASE              ((uint32_t)0x40001000)
+#define SPI0_BASE               ((uint32_t)0x40004000)
+#define ADC_BASE                ((uint32_t)0x40010000)
+#define AFIO_BASE               ((uint32_t)0x40022000)
+#define EXTI_BASE               ((uint32_t)0x40024000)
+#define I2S_BASE                ((uint32_t)0x40026000)
+#define MCTM0_BASE              ((uint32_t)0x4002C000)
+#define MCTM1_BASE              ((uint32_t)0x4002D000)
+#define USART1_BASE             ((uint32_t)0x40040000)
+#define UART1_BASE              ((uint32_t)0x40041000)
+#define SCI_BASE                ((uint32_t)0x40043000)
+#define SPI1_BASE               ((uint32_t)0x40044000)
+#define I2C0_BASE               ((uint32_t)0x40048000)
+#define I2C1_BASE               ((uint32_t)0x40049000)
+#define CMP0_BASE               ((uint32_t)0x40058000)
+#define CMP1_BASE               ((uint32_t)0x40058100)
+#define WDT_BASE                ((uint32_t)0x40068000)
+#define RTC_BASE                ((uint32_t)0x4006A000)
+#define PWRCU_BASE              ((uint32_t)0x4006A000)
+#define GPTM0_BASE              ((uint32_t)0x4006E000)
+#define GPTM1_BASE              ((uint32_t)0x4006F000)
+#define BFTM0_BASE              ((uint32_t)0x40076000)
+#define BFTM1_BASE              ((uint32_t)0x40077000)
+#define FMC_BASE                ((uint32_t)0x40080000)
+#define CKCU_BASE               ((uint32_t)0x40088000)
+#define RSTCU_BASE              ((uint32_t)0x40088000)
+#define CRC_BASE                ((uint32_t)0x4008A000)
+#define PDMA_BASE               ((uint32_t)0x40090000)
+#define EBI_BASE                ((uint32_t)0x40098000)
+#define USB_BASE                ((uint32_t)0x400A8000)
+#define USB_SRAM_BASE           ((uint32_t)0x400AA000)
+#define GPIO_A_BASE             ((uint32_t)0x400B0000)
+#define GPIO_B_BASE             ((uint32_t)0x400B2000)
+#define GPIO_C_BASE             ((uint32_t)0x400B4000)
+#define GPIO_D_BASE             ((uint32_t)0x400B6000)
+// Registers Headers
+#include "ht32f523x2_reg.h"
+/****************************************************************/
+/*                 Peripheral declaration                       */
+/****************************************************************/
+#define USART0                  ((USART_TypeDef *)  USART0_BASE)
+#define UART0                   ((USART_TypeDef *)  UART0_BASE)
+#define SPI0                    ((SPI_TypeDef *)    SPI0_BASE)
+#define ADC                     ((ADC_TypeDef *)    ADC_BASE)
+#define AFIO                    ((AFIO_TypeDef *)   AFIO_BASE)
+#define EXTI                    ((EXTI_TypeDef *)   EXTI_BASE)
+#define I2S                     ((I2S_TypeDef *)    I2S_BASE)
+#define MCTM0                   ((TM_TypeDef *)     MCTM0_BASE)
+#define MCTM1                   ((TM_TypeDef *)     MCTM1_BASE)
+#define USART1                  ((USART_TypeDef *)  USART1_BASE)
+#define UART1                   ((USART_TypeDef *)  UART1_BASE)
+#define SCI                     ((SCI_TypeDef *)    SCI_BASE)
+#define SPI1                    ((SPI_TypeDef *)    SPI1_BASE)
+#define I2C0                    ((I2C_TypeDef *)    I2C0_BASE)
+#define I2C1                    ((I2C_TypeDef *)    I2C1_BASE)
+#define CMP0                    ((CMP_TypeDef *)    CMP0_BASE)
+#define CMP1                    ((CMP_TypeDef *)    CMP1_BASE)
+#define WDT                     ((WDT_TypeDef *)    WDT_BASE)
+#define RTC                     ((RTC_TypeDef *)    RTC_BASE)
+#define PWRCU                   ((PWRCU_TypeDef *)  PWRCU_BASE)
+#define GPTM0                   ((TM_TypeDef *)     GPTM0_BASE)
+#define GPTM1                   ((TM_TypeDef *)     GPTM1_BASE)
+#define BFTM0                   ((BFTM_TypeDef *)   BFTM0_BASE)
+#define BFTM1                   ((BFTM_TypeDef *)   BFTM1_BASE)
+#define FMC                     ((FMC_TypeDef *)    FMC_BASE)
+#define CKCU                    ((CKCU_TypeDef *)   CKCU_BASE)
+#define RSTCU                   ((RSTCU_TypeDef *)  RSTCU_BASE)
+#define CRC                     ((CRC_TypeDef *)    CRC_BASE)
+#define PDMA                    ((PDMA_TypeDef *)   PDMA_BASE)
+#define EBI                     ((EBI_TypeDef *)    EBI_BASE)
+#define USB                     ((USB_TypeDef *)    USB_BASE)
+#define GPIOA                   ((GPIO_TypeDef *)   GPIO_A_BASE)
+#define GPIO_A GPIOA
+#define GPIOB                   ((GPIO_TypeDef *)   GPIO_B_BASE)
+#define GPIO_B GPIOB
+#define GPIOC                   ((GPIO_TypeDef *)   GPIO_C_BASE)
+#define GPIO_C GPIOC
+#define GPIOD                   ((GPIO_TypeDef *)   GPIO_D_BASE)
+#define GPIO_D GPIOD

diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h new file mode 100644 index 000000000..ba4871636 --- /dev/null +++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h
@@ -0,0 +1,199 @@
	1	/*
	2	* Copyright (C) 2020 Codetector <[email protected]>
	3	*
	4	* Permission is hereby granted, free of charge, to any person obtaining
	5	* a copy of this software and associated documentation files (the "Software"),
	6	* to deal in the Software without restriction, including without limitation
	7	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	8	* and/or sell copies of the Software, and to permit persons to whom the
	9	* Software is furnished to do so, subject to the following conditions:
	10	*
	11	* The above copyright notice and this permission notice shall be included in
	12	* all copies or substantial portions of the Software.
	13	*
	14	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
	15	* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	16	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
	17	* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	18	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
	19	* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	20	* SOFTWARE.
	21	*/
	22
	23	#pragma once
	24
	25	#if defined(HT32F52342) \|\| defined(HT32F52352)
	26	#define HT32F523x2
	27	#else
	28	#error "Unknown HT32 device"
	29	#endif
	30
	31	#if defined(HT32F523x2)
	32	#define HT32
	33	#endif
	34
	35	/*
	36	* ==============================================================
	37	* ---------- Interrupt Number Definition -----------------------
	38	* ==============================================================
	39	*/
	40	typedef enum IRQn
	41	{
	42	/**** Cortex-M3 Processor Exceptions Numbers **************/
	43	InitialSP_IRQn = -16,
	44	InitialPC_IRQn = -15,
	45	NonMaskableInt_IRQn = -14,
	46	HardFault_IRQn = -13,
	47	SVCall_IRQn = -5,
	48	PendSV_IRQn = -2,
	49	SysTick_IRQn = -1,
	50
	51	/**** HT32F165x Specific Interrupt Numbers *********************/
	52	LVD_IRQn = 0,
	53	RTC_IRQn = 1,
	54	FMC_IRQn = 2,
	55	WKUP_IRQn = 3,
	56	EXTI0_1_IRQn = 4,
	57	EXTI2_3_IRQn = 5,
	58	EXTI4_15_IRQn = 6,
	59	CMP_IRQn = 7,
	60	ADC_IRQn = 8,
	61
	62	MCTM_IRQn = 10,
	63	GPTM1_IRQn = 11,
	64	GPTM0_IRQn = 12,
	65	SCTM0_IRQn = 13,
	66	SCTM1_IRQn = 14,
	67
	68	BFTM0_IRQn = 17,
	69	BFTM1_IRQn = 18,
	70	I2C0_IRQn = 19,
	71	I2C1_IRQn = 20,
	72	SPI0_IRQn = 21,
	73	SPI1_IRQn = 22,
	74	USART0_IRQn = 23,
	75	USART1_IRQn = 24,
	76	UART0_IRQn = 25,
	77	UART1_IRQn = 26,
	78	SCI_IRQn = 27,
	79	I2S_IRQn = 28,
	80	USB_IRQn = 29,
	81	PDMA_CH0_1_IRQn = 30,
	82	PDMA_CH2_5_IRQn = 31
	83	} IRQn_Type;
	84
	85	/*
	86	* ==========================================================================
	87	* ----------- Processor and Core Peripheral Section ------------------------
	88	* ==========================================================================
	89	*/
	90
	91	/**
	92	* @brief HT32F165x Interrupt Number Definition, according to the selected device
	93	* in @ref Library_configuration_section
	94	*/
	95	#define __FPU_PRESENT 0
	96	#define __MPU_PRESENT 0
	97	#define __NVIC_PRIO_BITS 8
	98	#define __Vendor_SysTickConfig 0
	99
	100	#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
	101
	102	/****************************************************************/
	103	/* Peripheral memory map */
	104	/****************************************************************/
	105	#define USART0_BASE ((uint32_t)0x40000000)
	106	#define UART0_BASE ((uint32_t)0x40001000)
	107	#define SPI0_BASE ((uint32_t)0x40004000)
	108	#define ADC_BASE ((uint32_t)0x40010000)
	109
	110	#define AFIO_BASE ((uint32_t)0x40022000)
	111	#define EXTI_BASE ((uint32_t)0x40024000)
	112	#define I2S_BASE ((uint32_t)0x40026000)
	113	#define MCTM0_BASE ((uint32_t)0x4002C000)
	114	#define MCTM1_BASE ((uint32_t)0x4002D000)
	115
	116	#define USART1_BASE ((uint32_t)0x40040000)
	117	#define UART1_BASE ((uint32_t)0x40041000)
	118	#define SCI_BASE ((uint32_t)0x40043000)
	119	#define SPI1_BASE ((uint32_t)0x40044000)
	120	#define I2C0_BASE ((uint32_t)0x40048000)
	121	#define I2C1_BASE ((uint32_t)0x40049000)
	122
	123	#define CMP0_BASE ((uint32_t)0x40058000)
	124	#define CMP1_BASE ((uint32_t)0x40058100)
	125
	126	#define WDT_BASE ((uint32_t)0x40068000)
	127	#define RTC_BASE ((uint32_t)0x4006A000)
	128	#define PWRCU_BASE ((uint32_t)0x4006A000)
	129	#define GPTM0_BASE ((uint32_t)0x4006E000)
	130	#define GPTM1_BASE ((uint32_t)0x4006F000)
	131	#define BFTM0_BASE ((uint32_t)0x40076000)
	132	#define BFTM1_BASE ((uint32_t)0x40077000)
	133
	134	#define FMC_BASE ((uint32_t)0x40080000)
	135	#define CKCU_BASE ((uint32_t)0x40088000)
	136	#define RSTCU_BASE ((uint32_t)0x40088000)
	137	#define CRC_BASE ((uint32_t)0x4008A000)
	138	#define PDMA_BASE ((uint32_t)0x40090000)
	139	#define EBI_BASE ((uint32_t)0x40098000)
	140	#define USB_BASE ((uint32_t)0x400A8000)
	141	#define USB_SRAM_BASE ((uint32_t)0x400AA000)
	142	#define GPIO_A_BASE ((uint32_t)0x400B0000)
	143	#define GPIO_B_BASE ((uint32_t)0x400B2000)
	144	#define GPIO_C_BASE ((uint32_t)0x400B4000)
	145	#define GPIO_D_BASE ((uint32_t)0x400B6000)
	146
	147
	148	// Registers Headers
	149	#include "ht32f523x2_reg.h"
	150
	151	/****************************************************************/
	152	/* Peripheral declaration */
	153	/****************************************************************/
	154	#define USART0 ((USART_TypeDef *) USART0_BASE)
	155	#define UART0 ((USART_TypeDef *) UART0_BASE)
	156	#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
	157	#define ADC ((ADC_TypeDef *) ADC_BASE)
	158
	159	#define AFIO ((AFIO_TypeDef *) AFIO_BASE)
	160	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
	161	#define I2S ((I2S_TypeDef *) I2S_BASE)
	162	#define MCTM0 ((TM_TypeDef *) MCTM0_BASE)
	163	#define MCTM1 ((TM_TypeDef *) MCTM1_BASE)
	164
	165	#define USART1 ((USART_TypeDef *) USART1_BASE)
	166	#define UART1 ((USART_TypeDef *) UART1_BASE)
	167	#define SCI ((SCI_TypeDef *) SCI_BASE)
	168	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
	169	#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
	170	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
	171
	172	#define CMP0 ((CMP_TypeDef *) CMP0_BASE)
	173	#define CMP1 ((CMP_TypeDef *) CMP1_BASE)
	174
	175	#define WDT ((WDT_TypeDef *) WDT_BASE)
	176	#define RTC ((RTC_TypeDef *) RTC_BASE)
	177	#define PWRCU ((PWRCU_TypeDef *) PWRCU_BASE)
	178	#define GPTM0 ((TM_TypeDef *) GPTM0_BASE)
	179	#define GPTM1 ((TM_TypeDef *) GPTM1_BASE)
	180	#define BFTM0 ((BFTM_TypeDef *) BFTM0_BASE)
	181	#define BFTM1 ((BFTM_TypeDef *) BFTM1_BASE)
	182
	183	#define FMC ((FMC_TypeDef *) FMC_BASE)
	184	#define CKCU ((CKCU_TypeDef *) CKCU_BASE)
	185	#define RSTCU ((RSTCU_TypeDef *) RSTCU_BASE)
	186	#define CRC ((CRC_TypeDef *) CRC_BASE)
	187	#define PDMA ((PDMA_TypeDef *) PDMA_BASE)
	188	#define EBI ((EBI_TypeDef *) EBI_BASE)
	189	#define USB ((USB_TypeDef *) USB_BASE)
	190
	191	#define GPIOA ((GPIO_TypeDef *) GPIO_A_BASE)
	192	#define GPIO_A GPIOA
	193	#define GPIOB ((GPIO_TypeDef *) GPIO_B_BASE)
	194	#define GPIO_B GPIOB
	195	#define GPIOC ((GPIO_TypeDef *) GPIO_C_BASE)
	196	#define GPIO_C GPIOC
	197	#define GPIOD ((GPIO_TypeDef *) GPIO_D_BASE)
	198	#define GPIO_D GPIOD
	199