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1/*
2 * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining
5 * a copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
17 * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
20 * SOFTWARE.
21 */
22
23#ifndef _KL26Z_H_
24#define _KL26Z_H_
25
26/**
27 * @brief KL2x Interrupt Number Definition, according to the selected device
28 * in @ref Library_configuration_section
29 */
30#define __MPU_PRESENT 0
31#define __VTOR_PRESENT 1
32#define __NVIC_PRIO_BITS 2
33#define __Vendor_SysTickConfig 0
34
35/*
36 * ==============================================================
37 * ---------- Interrupt Number Definition -----------------------
38 * ==============================================================
39 */
40typedef enum IRQn
41{
42/****** Cortex-M0 Processor Exceptions Numbers ****************/
43 Reset_IRQn = -15,
44 NonMaskableInt_IRQn = -14,
45 HardFault_IRQn = -13,
46 SVCall_IRQn = -5,
47 PendSV_IRQn = -2,
48 SysTick_IRQn = -1,
49
50/****** KL2x Specific Interrupt Numbers ***********************/
51 DMA0_IRQn = 0,
52 DMA1_IRQn = 1,
53 DMA2_IRQn = 2,
54 DMA3_IRQn = 3,
55 Reserved0_IRQn = 4,
56 FTFA_IRQn = 5,
57 PMC_IRQn = 6,
58 LLWU_IRQn = 7,
59 I2C0_IRQn = 8,
60 I2C1_IRQn = 9,
61 SPI0_IRQn = 10,
62 SPI1_IRQn = 11,
63 UART0_IRQn = 12,
64 UART1_IRQn = 13,
65 UART2_IRQn = 14,
66 ADC0_IRQn = 15,
67 CMP0_IRQn = 16,
68 TPM0_IRQn = 17,
69 TPM1_IRQn = 18,
70 TPM2_IRQn = 19,
71 RTC0_IRQn = 20,
72 RTC1_IRQn = 21,
73 PIT_IRQn = 22,
74 I2S0_IRQn = 23,
75 USB_OTG_IRQn = 24,
76 DAC0_IRQn = 25,
77 TSI0_IRQn = 26,
78 MCG_IRQn = 27,
79 LPTMR0_IRQn = 28,
80 Reserved2_IRQn = 29,
81 PINA_IRQn = 30,
82 PINCD_IRQn = 31,
83} IRQn_Type;
84
85#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
86
87/*
88 * ==========================================================================
89 * ----------- Processor and Core Peripheral Section ------------------------
90 * ==========================================================================
91 */
92
93typedef struct
94{
95 __IO uint8_t C1;
96 __IO uint8_t C2;
97 __IO uint8_t C3;
98 __IO uint8_t C4;
99 __IO uint8_t C5;
100 __IO uint8_t C6;
101 __I uint8_t S;
102 uint8_t RESERVED0[1];
103 __IO uint8_t SC;
104 uint8_t RESERVED1[1];
105 __IO uint8_t ATCVH;
106 __IO uint8_t ATCVL;
107 __IO uint8_t C7;
108 __IO uint8_t C8;
109 __IO uint8_t C9;
110 __IO uint8_t C10;
111} MCG_TypeDef;
112
113typedef struct
114{
115 __IO uint32_t SC;
116 __IO uint32_t CNT;
117 __IO uint32_t MOD;
118 struct { // Channels
119 __IO uint32_t SC;
120 __IO uint32_t V;
121 } C[6];
122 uint32_t RESERVED0[5];
123 __IO uint32_t STATUS;
124 uint32_t RESERVED1[12];
125 __IO uint32_t CONF;
126} TPM_TypeDef;
127
128typedef struct
129{
130 __IO uint32_t GENCS;
131 __IO uint32_t DATA;
132 __IO uint32_t TSHD;
133} TSI_TypeDef;
134
135typedef struct
136{
137 __IO uint8_t S;
138 __IO uint8_t BR;
139 __IO uint8_t C2;
140 __IO uint8_t C1;
141 __IO uint8_t ML;
142 __IO uint8_t MH;
143 __IO uint8_t DL;
144 __IO uint8_t DH;
145 uint8_t RESERVED0[2];
146 __IO uint8_t CI;
147 __IO uint8_t C3;
148} SPI_TypeDef;
149
150typedef struct
151{
152 __IO uint8_t A1;
153 __IO uint8_t F;
154 __IO uint8_t C1;
155 __IO uint8_t S; /* Denoted 'S1' in datasheet. */
156 __IO uint8_t D;
157 __IO uint8_t C2;
158 __IO uint8_t FLT;
159 __IO uint8_t RA;
160 __IO uint8_t SMB;
161 __IO uint8_t A2;
162 __IO uint8_t SLTH;
163 __IO uint8_t SLTL;
164} I2C_TypeDef;
165
166typedef struct
167{
168 __IO uint8_t BDH;
169 __IO uint8_t BDL;
170 __IO uint8_t C1;
171 __IO uint8_t C2;
172 __I uint8_t S1;
173 __IO uint8_t S2;
174 __IO uint8_t C3;
175 __IO uint8_t D;
176 __IO uint8_t C4;
177} UART_TypeDef;
178
179typedef struct
180{
181 __IO uint8_t BDH;
182 __IO uint8_t BDL;
183 __IO uint8_t C1;
184 __IO uint8_t C2;
185 __IO uint8_t S1;
186 __IO uint8_t S2;
187 __IO uint8_t C3;
188 __IO uint8_t D;
189 __IO uint8_t MA1;
190 __IO uint8_t MA2;
191 __IO uint8_t C4;
192 __IO uint8_t C5;
193} UARTLP_TypeDef;
194
195typedef struct {
196 __I uint8_t PERID; // 0x00
197 uint8_t RESERVED0[3];
198 __I uint8_t IDCOMP; // 0x04
199 uint8_t RESERVED1[3];
200 __I uint8_t REV; // 0x08
201 uint8_t RESERVED2[3];
202 __I uint8_t ADDINFO; // 0x0C
203 uint8_t RESERVED3[3];
204 __IO uint8_t OTGISTAT; // 0x10
205 uint8_t RESERVED4[3];
206 __IO uint8_t OTGICR; // 0x14
207 uint8_t RESERVED5[3];
208 __IO uint8_t OTGSTAT; // 0x18
209 uint8_t RESERVED6[3];
210 __IO uint8_t OTGCTL; // 0x1C
211 uint8_t RESERVED7[99];
212 __IO uint8_t ISTAT; // 0x80
213 uint8_t RESERVED8[3];
214 __IO uint8_t INTEN; // 0x84
215 uint8_t RESERVED9[3];
216 __IO uint8_t ERRSTAT; // 0x88
217 uint8_t RESERVED10[3];
218 __IO uint8_t ERREN; // 0x8C
219 uint8_t RESERVED11[3];
220 __I uint8_t STAT; // 0x90
221 uint8_t RESERVED12[3];
222 __IO uint8_t CTL; // 0x94
223 uint8_t RESERVED13[3];
224 __IO uint8_t ADDR; // 0x98
225 uint8_t RESERVED14[3];
226 __IO uint8_t BDTPAGE1; // 0x9C
227 uint8_t RESERVED15[3];
228 __IO uint8_t FRMNUML; // 0xA0
229 uint8_t RESERVED16[3];
230 __IO uint8_t FRMNUMH; // 0xA4
231 uint8_t RESERVED17[3];
232 __IO uint8_t TOKEN; // 0xA8
233 uint8_t RESERVED18[3];
234 __IO uint8_t SOFTHLD; // 0xAC
235 uint8_t RESERVED19[3];
236 __IO uint8_t BDTPAGE2; // 0xB0
237 uint8_t RESERVED20[3];
238 __IO uint8_t BDTPAGE3; // 0xB4
239 uint8_t RESERVED21[11];
240 struct {
241 __IO uint8_t V; // 0xC0
242 uint8_t RESERVED[3];
243 } ENDPT[16];
244 __IO uint8_t USBCTRL; // 0x100
245 uint8_t RESERVED22[3];
246 __I uint8_t OBSERVE; // 0x104
247 uint8_t RESERVED23[3];
248 __IO uint8_t CONTROL; // 0x108
249 uint8_t RESERVED24[3];
250 __IO uint8_t USBTRC0; // 0x10C
251 uint8_t RESERVED25[7];
252 __IO uint8_t USBFRMADJUST; // 0x114
253} USBOTG_TypeDef;
254
255typedef struct
256{
257 __I uint8_t SRS0;
258 __I uint8_t SRS1;
259 uint8_t RESERVED0[2];
260 __IO uint8_t RPFC;
261 __IO uint8_t RPFW;
262} RCM_TypeDef;
263
264typedef struct {
265 __IO uint32_t TCSR; // 0x00
266 uint32_t RESERVED0[1];
267 __IO uint32_t TCR2; // 0x08
268 __IO uint32_t TCR3; // 0x0C
269 __IO uint32_t TCR4; // 0x10
270 __IO uint32_t TCR5; // 0x14
271 uint32_t RESERVED1[2];
272 __O uint32_t TDR0; // 0x20
273 uint32_t RESERVED2[15];
274 __IO uint32_t TMR; // 0x60
275 uint32_t RESERVED3[7];
276 __IO uint32_t RCSR; // 0x80
277 uint32_t RESERVED4[1];
278 __IO uint32_t RCR2; // 0x88
279 __IO uint32_t RCR3; // 0x8C
280 __IO uint32_t RCR4; // 0x90
281 __IO uint32_t RCR5; // 0x94
282 uint32_t RESERVED5[2];
283 __I uint32_t RDR0; // 0xA0
284 uint32_t RESERVED6[15];
285 __IO uint32_t RMR; // 0xE0
286 uint32_t RESERVED7[7];
287 __IO uint32_t MCR; // 0x100
288} I2S_TypeDef;
289
290/****************************************************************/
291/* Peripheral memory map */
292/****************************************************************/
293#define DMA_BASE ((uint32_t)0x40008100)
294#define FTFA_BASE ((uint32_t)0x40020000)
295#define DMAMUX_BASE ((uint32_t)0x40021000)
296#define I2S0_BASE ((uint32_t)0x4002F000) // TODO: registers not implemented
297#define PIT_BASE ((uint32_t)0x40037000)
298#define TPM0_BASE ((uint32_t)0x40038000)
299#define TPM1_BASE ((uint32_t)0x40039000)
300#define TPM2_BASE ((uint32_t)0x4003A000)
301#define ADC0_BASE ((uint32_t)0x4003B000)
302#define RTC_BASE ((uint32_t)0x4003D000)
303#define DAC0_BASE ((uint32_t)0x4003F000)
304#define LPTMR0_BASE ((uint32_t)0x40040000)
305#define TSI0_BASE ((uint32_t)0x40045000)
306#define SIM_BASE ((uint32_t)0x40047000)
307#define PORTA_BASE ((uint32_t)0x40049000)
308#define PORTB_BASE ((uint32_t)0x4004A000)
309#define PORTC_BASE ((uint32_t)0x4004B000)
310#define PORTD_BASE ((uint32_t)0x4004C000)
311#define PORTE_BASE ((uint32_t)0x4004D000)
312#define MCG_BASE ((uint32_t)0x40064000)
313#define OSC0_BASE ((uint32_t)0x40065000)
314#define I2C0_BASE ((uint32_t)0x40066000)
315#define I2C1_BASE ((uint32_t)0x40067000)
316#define UART0_BASE ((uint32_t)0x4006A000)
317#define UART1_BASE ((uint32_t)0x4006B000)
318#define UART2_BASE ((uint32_t)0x4006C000)
319#define USBOTG_BASE ((uint32_t)0x40072000)
320#define CMP_BASE ((uint32_t)0x40073000)
321#define SPI0_BASE ((uint32_t)0x40076000)
322#define SPI1_BASE ((uint32_t)0x40077000)
323#define LLWU_BASE ((uint32_t)0x4007C000)
324#define PMC_BASE ((uint32_t)0x4007D000)
325#define SMC_BASE ((uint32_t)0x4007E000)
326#define RCM_BASE ((uint32_t)0x4007F000)
327#define GPIOA_BASE ((uint32_t)0x400FF000)
328#define GPIOB_BASE ((uint32_t)0x400FF040)
329#define GPIOC_BASE ((uint32_t)0x400FF080)
330#define GPIOD_BASE ((uint32_t)0x400FF0C0)
331#define GPIOE_BASE ((uint32_t)0x400FF100)
332#define MCM_BASE ((uint32_t)0xF0003000)
333
334/****************************************************************/
335/* Peripheral declaration */
336/****************************************************************/
337#define DMA ((DMA_TypeDef *) DMA_BASE)
338#define FTFA ((FTFA_TypeDef *) FTFA_BASE)
339#define DMAMUX ((DMAMUX_TypeDef *) DMAMUX_BASE)
340#define I2S0 ((I2S_TypeDef *) I2S0_BASE)
341#define PIT ((PIT_TypeDef *) PIT_BASE)
342#define TPM0 ((TPM_TypeDef *) TPM0_BASE)
343#define TPM1 ((TPM_TypeDef *) TPM1_BASE)
344#define TPM2 ((TPM_TypeDef *) TPM2_BASE)
345#define ADC0 ((ADC_TypeDef *) ADC0_BASE)
346#define RTC0 ((RTC_TypeDef *) RTC0_BASE)
347#define DAC0 ((DAC_TypeDef *) DAC0_BASE)
348#define LPTMR0 ((LPTMR_TypeDef *) LPTMR0_BASE)
349#define TSI0 ((TSI_TypeDef *) TSI0_BASE)
350#define SIM ((SIM_TypeDef *) SIM_BASE)
351#define LLWU ((LLWU_TypeDef *) LLWU_BASE)
352#define PMC ((PMC_TypeDef *) PMC_BASE)
353#define PORTA ((PORT_TypeDef *) PORTA_BASE)
354#define PORTB ((PORT_TypeDef *) PORTB_BASE)
355#define PORTC ((PORT_TypeDef *) PORTC_BASE)
356#define PORTD ((PORT_TypeDef *) PORTD_BASE)
357#define PORTE ((PORT_TypeDef *) PORTE_BASE)
358#define USB0 ((USBOTG_TypeDef *) USBOTG_BASE)
359#define CMP ((CMP_TypeDef *) CMP_BASE)
360#define MCG ((MCG_TypeDef *) MCG_BASE)
361#define OSC0 ((OSC_TypeDef *) OSC0_BASE)
362#define SPI0 ((SPI_TypeDef *) SPI0_BASE)
363#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
364#define I2C0 ((I2C_TypeDef *) I2C0_BASE)
365#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
366#define UART0 ((UARTLP_TypeDef *) UART0_BASE)
367#define UART1 ((UART_TypeDef *) UART1_BASE)
368#define UART2 ((UART_TypeDef *) UART2_BASE)
369#define SMC ((SMC_TypeDef *) SMC_BASE)
370#define RCM ((RCM_TypeDef *) RCM_BASE)
371#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
372#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
373#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
374#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
375#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
376#define MCM ((MCM_TypeDef *) MCM_BASE)
377
378/****************************************************************/
379/* Peripheral Registers Bits Definition */
380/****************************************************************/
381
382/****************************************************************/
383/* */
384/* System Integration Module (SIM) */
385/* */
386/****************************************************************/
387/********* Bits definition for SIM_SOPT1 register *************/
388#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) /*!< USB voltage regulator enable */
389#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) /*!< USB voltage regulator in standby mode during Stop, VLPS, LLS and VLLS modes */
390#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) /*!< USB voltage regulator in standby mode during VLPR and VLPW modes */
391#define SIM_SOPT1_OSC32KSEL_SHIFT 18 /*!< 32K oscillator clock select (shift) */
392#define SIM_SOPT1_OSC32KSEL_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT1_OSC32KSEL_SHIFT)) /*!< 32K oscillator clock select (mask) */
393#define SIM_SOPT1_OSC32KSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT1_OSC32KSEL_SHIFT) & SIM_SOPT1_OSC32KSEL_MASK)) /*!< 32K oscillator clock select */
394
395/******* Bits definition for SIM_SOPT1CFG register ************/
396#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) /*!< USB voltage regulator stop standby write enable */
397#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) /*!< USB voltage regulator VLP standby write enable */
398#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) /*!< USB voltage regulator voltage regulator write enable */
399
400/******* Bits definition for SIM_SOPT2 register ************/
401#define SIM_SOPT2_UART0SRC_SHIFT 26 /*!< UART0 clock source select (shift) */
402#define SIM_SOPT2_UART0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_UART0SRC_SHIFT)) /*!< UART0 clock source select (mask) */
403#define SIM_SOPT2_UART0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_UART0SRC_SHIFT) & SIM_SOPT2_UART0SRC_MASK)) /*!< UART0 clock source select */
404#define SIM_SOPT2_TPMSRC_SHIFT 24 /*!< TPM clock source select (shift) */
405#define SIM_SOPT2_TPMSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT2_TPMSRC_SHIFT)) /*!< TPM clock source select (mask) */
406#define SIM_SOPT2_TPMSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_TPMSRC_SHIFT) & SIM_SOPT2_TPMSRC_MASK)) /*!< TPM clock source select */
407#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) /*!< USB clock source select */
408#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) /*!< PLL/FLL clock select */
409#define SIM_SOPT2_CLKOUTSEL_SHIFT 5 /*!< CLKOUT select (shift) */
410#define SIM_SOPT2_CLKOUTSEL_MASK ((uint32_t)((uint32_t)0x07 << SIM_SOPT2_CLKOUTSEL_SHIFT)) /*!< CLKOUT select (mask) */
411#define SIM_SOPT2_CLKOUTSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT2_CLKOUTSEL_SHIFT) & SIM_SOPT2_CLKOUTSEL_MASK)) /*!< CLKOUT select */
412#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) /*!< RTC clock out select */
413
414/******* Bits definition for SIM_SOPT4 register ************/
415#define SIM_SOPT4_TPM2CLKSEL ((uint32_t)0x04000000) /*!< TPM2 External Clock Pin Select */
416#define SIM_SOPT4_TPM1CLKSEL ((uint32_t)0x02000000) /*!< TPM1 External Clock Pin Select */
417#define SIM_SOPT4_TPM0CLKSEL ((uint32_t)0x01000000) /*!< TPM0 External Clock Pin Select */
418#define SIM_SOPT4_TPM2CH0SRC ((uint32_t)0x00100000) /*!< TPM2 channel 0 input capture source select */
419#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18 /*!< TPM1 channel 0 input capture source select (shift) */
420#define SIM_SOPT4_TPM1CH0SRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT4_TPM1CH0SRC_SHIFT)) /*!< TPM1 channel 0 input capture source select (mask) */
421#define SIM_SOPT4_TPM1CH0SRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT4_TPM1CH0SRC_SHIFT) & SIM_SOPT4_TPM1CH0SRC_MASK)) /*!< TPM1 channel 0 input capture source select */
422
423/******* Bits definition for SIM_SOPT5 register ************/
424#define SIM_SOPT5_UART2ODE ((uint32_t)0x00040000) /*!< UART2 Open Drain Enable */
425#define SIM_SOPT5_UART1ODE ((uint32_t)0x00020000) /*!< UART1 Open Drain Enable */
426#define SIM_SOPT5_UART0ODE ((uint32_t)0x00010000) /*!< UART0 Open Drain Enable */
427#define SIM_SOPT5_UART1RXSRC ((uint32_t)0x00000040) /*!< UART1 receive data source select */
428#define SIM_SOPT5_UART1TXSRC_SHIFT 4 /*!< UART1 transmit data source select (shift) */
429#define SIM_SOPT5_UART1TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART1TXSRC_SHIFT)) /*!< UART1 transmit data source select (mask) */
430#define SIM_SOPT5_UART1TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART1TXSRC_SHIFT) & SIM_SOPT5_UART1TXSRC_MASK)) /*!< UART1 transmit data source select */
431#define SIM_SOPT5_UART0RXSRC ((uint32_t)0x00000040) /*!< UART0 receive data source select */
432#define SIM_SOPT5_UART0TXSRC_SHIFT 0 /*!< UART0 transmit data source select (shift) */
433#define SIM_SOPT5_UART0TXSRC_MASK ((uint32_t)((uint32_t)0x03 << SIM_SOPT5_UART0TXSRC_SHIFT)) /*!< UART0 transmit data source select (mask) */
434#define SIM_SOPT5_UART0TXSRC(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT5_UART0TXSRC_SHIFT) & SIM_SOPT5_UART0TXSRC_MASK)) /*!< UART0 transmit data source select */
435
436/******* Bits definition for SIM_SOPT7 register ************/
437#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) /*!< ADC0 Alternate Trigger Enable */
438#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) /*!< ADC0 Pretrigger Select */
439#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0 /*!< ADC0 Trigger Select (shift) */
440#define SIM_SOPT7_ADC0TRGSEL_MASK ((uint32_t)((uint32_t)0x0F << SIM_SOPT7_ADC0TRGSEL_SHIFT)) /*!< ADC0 Trigger Select (mask) */
441#define SIM_SOPT7_ADC0TRGSEL(x) ((uint32_t)(((uint32_t)(x) << SIM_SOPT7_ADC0TRGSEL_SHIFT) & SIM_SOPT7_ADC0TRGSEL_MASK)) /*!< ADC0 Trigger Select */
442
443/******** Bits definition for SIM_SDID register ************/
444#define SIM_SDID_FAMID_SHIFT 28 /*!< Kinetis family ID (shift) */
445#define SIM_SDID_FAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_FAMID_SHIFT)) /*!< Kinetis family ID (mask) */
446#define SIM_SDID_SUBFAMID_SHIFT 24 /*!< Kinetis Sub-Family ID (shift) */
447#define SIM_SDID_SUBFAMID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SUBFAMID_SHIFT)) /*!< Kinetis Sub-Family ID (mask) */
448#define SIM_SDID_SERIESID_SHIFT 20 /*!< Kinetis Series ID (shift) */
449#define SIM_SDID_SERIESID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SERIESID_SHIFT)) /*!< Kinetis Series ID (mask) */
450#define SIM_SDID_SRAMSIZE_SHIFT 16 /*!< System SRAM Size (shift) */
451#define SIM_SDID_SRAMSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_SRAMSIZE_SHIFT)) /*!< System SRAM Size (mask) */
452#define SIM_SDID_REVID_SHIFT 12 /*!< Device revision number (shift) */
453#define SIM_SDID_REVID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_REVID_SHIFT)) /*!< Device revision number (mask) */
454#define SIM_SDID_DIEID_SHIFT 7 /*!< Device die number (shift) */
455#define SIM_SDID_DIEID_MASK ((uint32_t)((uint32_t)0x1F << SIM_SDID_DIEID_SHIFT)) /*!< Device die number (mask) */
456#define SIM_SDID_PINID_SHIFT 0 /*!< Pincount identification (shift) */
457#define SIM_SDID_PINID_MASK ((uint32_t)((uint32_t)0x0F << SIM_SDID_PINID_SHIFT)) /*!< Pincount identification (mask) */
458
459/******* Bits definition for SIM_SCGC4 register ************/
460#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) /*!< SPI1 Clock Gate Control */
461#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) /*!< SPI0 Clock Gate Control */
462#define SIM_SCGC4_CMP ((uint32_t)0x00080000) /*!< Comparator Clock Gate Control */
463#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) /*!< USB Clock Gate Control */
464#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) /*!< UART2 Clock Gate Control */
465#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) /*!< UART1 Clock Gate Control */
466#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) /*!< UART0 Clock Gate Control */
467#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) /*!< I2C1 Clock Gate Control */
468#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) /*!< I2C0 Clock Gate Control */
469
470/******* Bits definition for SIM_SCGC5 register ************/
471#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) /*!< Port E Clock Gate Control */
472#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) /*!< Port D Clock Gate Control */
473#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) /*!< Port C Clock Gate Control */
474#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) /*!< Port B Clock Gate Control */
475#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) /*!< Port A Clock Gate Control */
476#define SIM_SCGC5_TSI ((uint32_t)0x00000020) /*!< TSI Access Control */
477#define SIM_SCGC5_LPTMR ((uint32_t)0x00000001) /*!< Low Power Timer Access Control */
478
479/******* Bits definition for SIM_SCGC6 register ************/
480#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) /*!< DAC0 Clock Gate Control */
481#define SIM_SCGC6_RTC ((uint32_t)0x20000000) /*!< RTC Access Control */
482#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) /*!< ADC0 Clock Gate Control */
483#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) /*!< TPM2 Clock Gate Control */
484#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) /*!< TPM1 Clock Gate Control */
485#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) /*!< TPM0 Clock Gate Control */
486#define SIM_SCGC6_PIT ((uint32_t)0x00800000) /*!< PIT Clock Gate Control */
487#define SIM_SCGC6_I2S ((uint32_t)0x00008000) /*!< I2S0 Clock Gate Control */
488#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) /*!< DMA Mux Clock Gate Control */
489#define SIM_SCGC6_FTF ((uint32_t)0x00000001) /*!< Flash Memory Clock Gate Control */
490
491/******* Bits definition for SIM_SCGC7 register ************/
492#define SIM_SCGC7_DMA ((uint32_t)0x00000100) /*!< DMA Clock Gate Control */
493
494/****** Bits definition for SIM_CLKDIV1 register ***********/
495#define SIM_CLKDIV1_OUTDIV1_SHIFT 28 /*!< Clock 1 output divider value (shift) */
496#define SIM_CLKDIV1_OUTDIV1_MASK ((uint32_t)((uint32_t)0x0F << SIM_CLKDIV1_OUTDIV1_SHIFT)) /*!< Clock 1 output divider value (mask) */
497#define SIM_CLKDIV1_OUTDIV1(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV1_SHIFT) & SIM_CLKDIV1_OUTDIV1_MASK)) /*!< Clock 1 output divider value */
498#define SIM_CLKDIV1_OUTDIV4_SHIFT 16 /*!< Clock 4 output divider value (shift) */
499#define SIM_CLKDIV1_OUTDIV4_MASK ((uint32_t)((uint32_t)0x07 << SIM_CLKDIV1_OUTDIV4_SHIFT)) /*!< Clock 4 output divider value (mask) */
500#define SIM_CLKDIV1_OUTDIV4(x) ((uint32_t)(((uint32_t)(x) << SIM_CLKDIV1_OUTDIV4_SHIFT) & SIM_CLKDIV1_OUTDIV4_MASK)) /*!< Clock 4 output divider value */
501
502/******* Bits definition for SIM_FCFG1 register ************/
503#define SIM_FCFG1_PFSIZE_SHIFT 24 /*!< Program Flash Size (shift) */
504#define SIM_FCFG1_PFSIZE_MASK ((uint32_t)((uint32_t)0x0F << SIM_FCFG1_PFSIZE_SHIFT)) /*!< Program Flash Size (mask) */
505#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) /*!< Flash Doze */
506#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) /*!< Flash Disable */
507
508/******* Bits definition for SIM_FCFG2 register ************/
509#define SIM_FCFG2_MAXADDR0_SHIFT 24 /*!< Max address lock (shift) */
510#define SIM_FCFG2_MAXADDR0_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR0_SHIFT)) /*!< Max address lock (mask) */
511#define SIM_FCFG2_MAXADDR1_SHIFT 16 /*!< Max address lock (block 1) (shift) */
512#define SIM_FCFG2_MAXADDR1_MASK ((uint32_t)((uint32_t)0x7F << SIM_FCFG2_MAXADDR1_SHIFT)) /*!< Max address lock (block 1) (mask) */
513
514/******* Bits definition for SIM_UIDMH register ************/
515#define SIM_UIDMH_UID_MASK ((uint32_t)0x0000FFFF) /*!< Unique Identification */
516
517/******* Bits definition for SIM_UIDML register ************/
518#define SIM_UIDML_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */
519
520/******* Bits definition for SIM_UIDL register *************/
521#define SIM_UIDL_UID_MASK ((uint32_t)0xFFFFFFFF) /*!< Unique Identification */
522
523/******* Bits definition for SIM_COPC register *************/
524#define SIM_COPC_COPT_SHIFT 2 /*!< COP Watchdog Timeout (shift) */
525#define SIM_COPC_COPT_MASK ((uint32_t)((uint32_t)0x03 << SIM_COPC_COPT_SHIFT)) /*!< COP Watchdog Timeout (mask) */
526#define SIM_COPC_COPT(x) ((uint32_t)(((uint32_t)(x) << SIM_COPC_COPT_SHIFT) & SIM_COPC_COPT_MASK)) /*!< COP Watchdog Timeout */
527#define SIM_COPC_COPCLKS ((uint32_t)0x00000002) /*!< COP Clock Select */
528#define SIM_COPC_COPW ((uint32_t)0x00000001) /*!< COP windowed mode */
529
530/******* Bits definition for SIM_SRVCOP register ***********/
531#define SIM_SRVCOP_SRVCOP_SHIFT 0 /*!< Sevice COP Register (shift) */
532#define SIM_SRVCOP_SRVCOP_MASK ((uint32_t)((uint32_t)0xFF << SIM_SRVCOP_SRVCOP_SHIFT)) /*!< Sevice COP Register (mask) */
533#define SIM_SRVCOP_SRVCOP(x) ((uint32_t)(((uint32_t)(x) << SIM_SRVCOP_SRVCOP_SHIFT) & SIM_SRVCOP_SRVCOP_MASK)) /*!< Sevice COP Register */
534
535
536/****************************************************************/
537/* */
538/* Low-Leakage Wakeup Unit (LLWU) */
539/* */
540/****************************************************************/
541
542/* Device independent */
543
544/****************************************************************/
545/* */
546/* Port Control and interrupts (PORT) */
547/* */
548/****************************************************************/
549
550/* Device independent */
551
552/****************************************************************/
553/* */
554/* Oscillator (OSC) */
555/* */
556/****************************************************************/
557
558/* Device independent */
559
560/****************************************************************/
561/* */
562/* Direct Memory Access (DMA) */
563/* */
564/****************************************************************/
565
566/* Device independent */
567
568/****************************************************************/
569/* */
570/* Direct Memory Access Multiplexer (DMAMUX) */
571/* */
572/****************************************************************/
573
574/* Device independent */
575
576/****************************************************************/
577/* */
578/* Periodic Interrupt Timer (PIT) */
579/* */
580/****************************************************************/
581
582/* Device independent */
583
584/****************************************************************/
585/* */
586/* Analog-to-Digital Converter (ADC) */
587/* */
588/****************************************************************/
589
590/* Device independent */
591
592/****************************************************************/
593/* */
594/* Low-Power Timer (LPTMR) */
595/* */
596/****************************************************************/
597
598/* Device independent */
599
600/****************************************************************/
601/* */
602/* Touch Sensing Input (TSI) */
603/* */
604/****************************************************************/
605/********** Bits definition for TSIx_GENCS register ***********/
606#define TSIx_GENCS_OUTRGF ((uint32_t)((uint32_t)1 << 31)) /*!< Out of Range Flag */
607#define TSIx_GENCS_ESOR ((uint32_t)((uint32_t)1 << 28)) /*!< End-of-scan/Out-of-Range Interrupt Selection */
608#define TSIx_GENCS_MODE_SHIFT 24 /*!< TSI analog modes setup and status bits (shift) */
609#define TSIx_GENCS_MODE_MASK ((uint32_t)((uint32_t)0x0F << TSIx_GENCS_MODE_SHIFT)) /*!< TSI analog modes setup and status bits (mask) */
610#define TSIx_GENCS_MODE(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_MODE_SHIFT) & TSIx_GENCS_MODE_MASK)) /*!< TSI analog modes setup and status bits */
611#define TSIx_GENCS_REFCHRG_SHIFT 21 /*!< Reference oscillator charge/discharge current (shift) */
612#define TSIx_GENCS_REFCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_REFCHRG_SHIFT)) /*!< Reference oscillator charge/discharge current (mask) */
613#define TSIx_GENCS_REFCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_REFCHRG_SHIFT) & TSIx_GENCS_REFCHRG_MASK)) /*!< Reference oscillator charge/discharge current */
614#define TSIx_GENCS_DVOLT_SHIFT 19 /*!< Oscillator voltage rails (shift) */
615#define TSIx_GENCS_DVOLT_MASK ((uint32_t)((uint32_t)0x03 << TSIx_GENCS_DVOLT_SHIFT)) /*!< Oscillator voltage rails (mask) */
616#define TSIx_GENCS_DVOLT(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_DVOLT_SHIFT) & TSIx_GENCS_DVOLT_MASK)) /*!< Oscillator voltage rails */
617#define TSIx_GENCS_EXTCHRG_SHIFT 16 /*!< Electrode oscillator charge/discharge current (shift) */
618#define TSIx_GENCS_EXTCHRG_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_EXTCHRG_SHIFT)) /*!< Electrode oscillator charge/discharge current (mask) */
619#define TSIx_GENCS_EXTCHRG(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_EXTCHRG_SHIFT) & TSIx_GENCS_EXTCHRG_MASK)) /*!< Electrode oscillator charge/discharge current */
620#define TSIx_GENCS_PS_SHIFT 13 /*!< Electrode oscillator prescaler (shift) */
621#define TSIx_GENCS_PS_MASK ((uint32_t)((uint32_t)0x07 << TSIx_GENCS_PS_SHIFT)) /*!< Electrode oscillator prescaler (mask) */
622#define TSIx_GENCS_PS(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_PS_SHIFT) & TSIx_GENCS_PS_MASK)) /*!< Electrode oscillator prescaler */
623#define TSIx_GENCS_NSCN_SHIFT 8 /*!< Number of scans per electrode minus 1 (shift) */
624#define TSIx_GENCS_NSCN_MASK ((uint32_t)((uint32_t)0x1F << TSIx_GENCS_NSCN_SHIFT)) /*!< Number of scans per electrode minus 1 (mask) */
625#define TSIx_GENCS_NSCN(x) ((uint32_t)(((uint32_t)(x) << TSIx_GENCS_NSCN_SHIFT) & TSIx_GENCS_NSCN_MASK)) /*!< Number of scans per electrode minus 1 */
626#define TSIx_GENCS_TSIEN ((uint32_t)((uint32_t)1 << 7)) /*!< TSI Module Enable */
627#define TSIx_GENCS_TSIIEN ((uint32_t)((uint32_t)1 << 6)) /*!< TSI Interrupt Enable */
628#define TSIx_GENCS_STPE ((uint32_t)((uint32_t)1 << 5)) /*!< TSI STOP Enable */
629#define TSIx_GENCS_STM ((uint32_t)((uint32_t)1 << 4)) /*!< Scan Trigger Mode (0=software; 1=hardware) */
630#define TSIx_GENCS_SCNIP ((uint32_t)((uint32_t)1 << 3)) /*!< Scan in Progress Status */
631#define TSIx_GENCS_EOSF ((uint32_t)((uint32_t)1 << 2)) /*!< End of Scan Flag */
632#define TSIx_GENCS_CURSW ((uint32_t)((uint32_t)1 << 1)) /*!< Swap electrode and reference current sources */
633
634/********** Bits definition for TSIx_DATA register ************/
635#define TSIx_DATA_TSICH_SHIFT 28 /*!< Specify channel to be measured (shift) */
636#define TSIx_DATA_TSICH_MASK ((uint32_t)((uint32_t)0x0F << TSIx_DATA_TSICH_SHIFT)) /*!< Specify channel to be measured (mask) */
637#define TSIx_DATA_TSICH(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICH_SHIFT) & TSIx_DATA_TSICH_MASK)) /*!< Specify channel to be measured */
638#define TSIx_DATA_DMAEN ((uint32_t)((uint32_t)1 << 23)) /*!< DMA Transfer Enabled */
639#define TSIx_DATA_SWTS ((uint32_t)((uint32_t)1 << 22)) /*!< Software Trigger Start */
640#define TSIx_DATA_TSICNT_SHIFT 0 /*!< TSI Conversion Counter Value (shift) */
641#define TSIx_DATA_TSICNT_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_DATA_TSICNT_SHIFT)) /*!< TSI Conversion Counter Value (mask) */
642#define TSIx_DATA_TSICNT(x) ((uint32_t)(((uint32_t)(x) << TSIx_DATA_TSICNT_SHIFT) & TSIx_DATA_TSICNT_MASK)) /*!< TSI Conversion Counter Value */
643
644/********** Bits definition for TSIx_TSHD register ************/
645#define TSIx_TSHD_THRESH_SHIFT 16 /*!< TSI Wakeup Channel High-Threshold (shift) */
646#define TSIx_TSHD_THRESH_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESH_SHIFT)) /*!< TSI Wakeup Channel High-Threshold (mask) */
647#define TSIx_TSHD_THRESH(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESH_SHIFT) & TSIx_TSHD_THRESH_MASK)) /*!< TSI Wakeup Channel High-Threshold */
648#define TSIx_TSHD_THRESL_SHIFT 0 /*!< TSI Wakeup Channel Low-Threshold (shift) */
649#define TSIx_TSHD_THRESL_MASK ((uint32_t)((uint32_t)0xFFFF << TSIx_TSHD_THRESL_SHIFT)) /*!< TSI Wakeup Channel Low-Threshold (mask) */
650#define TSIx_TSHD_THRESL(x) ((uint32_t)(((uint32_t)(x) << TSIx_TSHD_THRESL_SHIFT) & TSIx_TSHD_THRESL_MASK)) /*!< TSI Wakeup Channel Low-Threshold */
651
652/****************************************************************/
653/* */
654/* Multipurpose Clock Generator (MCG) */
655/* */
656/****************************************************************/
657/*********** Bits definition for MCG_C1 register **************/
658#define MCG_C1_CLKS_SHIFT 6 /*!< Clock source select (shift) */
659#define MCG_C1_CLKS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C1_CLKS_SHIFT)) /*!< Clock source select (mask) */
660#define MCG_C1_CLKS(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_CLKS_SHIFT) & MCG_C1_CLKS_MASK)) /*!< Clock source select */
661#define MCG_C1_CLKS_FLLPLL MCG_C1_CLKS(0) /*!< Select output of FLL or PLL, depending on PLLS control bit */
662#define MCG_C1_CLKS_IRCLK MCG_C1_CLKS(1) /*!< Select internal reference clock */
663#define MCG_C1_CLKS_ERCLK MCG_C1_CLKS(2) /*!< Select external reference clock */
664#define MCG_C1_FRDIV_SHIFT 3 /*!< FLL External Reference Divider (shift) */
665#define MCG_C1_FRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_C1_FRDIV_SHIFT)) /*!< FLL External Reference Divider (mask) */
666#define MCG_C1_FRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_C1_FRDIV_SHIFT) & MCG_C1_FRDIV_MASK)) /*!< FLL External Reference Divider */
667#define MCG_C1_IREFS ((uint8_t)((uint8_t)1 << 2)) /*!< Internal Reference Select (0=ERCLK; 1=slow IRCLK) */
668#define MCG_C1_IRCLKEN ((uint8_t)((uint8_t)1 << 1)) /*!< Internal Reference Clock Enable */
669#define MCG_C1_IREFSTEN ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Stop Enable */
670
671/*********** Bits definition for MCG_C2 register **************/
672#define MCG_C2_LOCRE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Clock Reset Enable */
673#define MCG_C2_FCFTRIM ((uint8_t)((uint8_t)1 << 6)) /*!< Loss of Clock Reset Enable */
674#define MCG_C2_RANGE0_SHIFT 4 /*!< Frequency Range Select (shift) */
675#define MCG_C2_RANGE0_MASK ((uint8_t)((uint8_t)0x03 << MCG_C2_RANGE0_SHIFT)) /*!< Frequency Range Select (mask) */
676#define MCG_C2_RANGE0(x) ((uint8_t)(((uint8_t)(x) << MCG_C2_RANGE0_SHIFT) & MCG_C2_RANGE0_MASK)) /*!< Frequency Range Select */
677#define MCG_C2_HGO0 ((uint8_t)((uint8_t)1 << 3)) /*!< High Gain Oscillator Select (0=low power; 1=high gain) */
678#define MCG_C2_EREFS0 ((uint8_t)((uint8_t)1 << 2)) /*!< External Reference Select (0=clock; 1=oscillator) */
679#define MCG_C2_LP ((uint8_t)((uint8_t)1 << 1)) /*!< Low Power Select (1=FLL/PLL disabled in bypass modes) */
680#define MCG_C2_IRCS ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Select (0=slow; 1=fast) */
681
682/*********** Bits definition for MCG_C3 register **************/
683#define MCG_C3_SCTRIM_SHIFT 0 /*!< Slow Internal Reference Clock Trim Setting (shift) */
684#define MCG_C3_SCTRIM_MASK ((uint8_t)((uint8_t)0xFF << MCG_C3_SCTRIM_SHIFT)) /*!< Slow Internal Reference Clock Trim Setting (mask) */
685#define MCG_C3_SCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C3_SCTRIM_SHIFT) & MCG_C3_SCTRIM_MASK)) /*!< Slow Internal Reference Clock Trim Setting */
686
687/*********** Bits definition for MCG_C4 register **************/
688#define MCG_C4_DMX32 ((uint8_t)((uint8_t)1 << 7)) /*!< DCO Maximum Frequency with 32.768 kHz Reference */
689#define MCG_C4_DRST_DRS_SHIFT 5 /*!< DCO Range Select (shift) */
690#define MCG_C4_DRST_DRS_MASK ((uint8_t)((uint8_t)0x03 << MCG_C4_DRST_DRS_SHIFT)) /*!< DCO Range Select (mask) */
691#define MCG_C4_DRST_DRS(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_DRST_DRS_SHIFT) & MCG_C4_DRST_DRS_MASK)) /*!< DCO Range Select */
692#define MCG_C4_FCTRIM_SHIFT 1 /*!< Fast Internal Reference Clock Trim Setting (shift) */
693#define MCG_C4_FCTRIM_MASK ((uint8_t)((uint8_t)0x0F << MCG_C4_FCTRIM_SHIFT)) /*!< Fast Internal Reference Clock Trim Setting (mask) */
694#define MCG_C4_FCTRIM(x) ((uint8_t)(((uint8_t)(x) << MCG_C4_FCTRIM_SHIFT) & MCG_C4_FCTRIM_MASK)) /*!< Fast Internal Reference Clock Trim Setting */
695#define MCG_C4_SCFTRIM ((uint8_t)((uint8_t)1 << 0)) /*!< Slow Internal Reference Clock Fine Trim */
696
697/*********** Bits definition for MCG_C5 register **************/
698#define MCG_C5_PLLCLKEN0 ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Clock Enable */
699#define MCG_C5_PLLSTEN0 ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Stop Enable */
700#define MCG_C5_PRDIV0_SHIFT 0 /*!< PLL External Reference Divider (shift) */
701#define MCG_C5_PRDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C5_PRDIV0_SHIFT)) /*!< PLL External Reference Divider (mask) */
702#define MCG_C5_PRDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C5_PRDIV0_SHIFT) & MCG_C5_PRDIV0_MASK)) /*!< PLL External Reference Divider */
703
704/*********** Bits definition for MCG_C6 register **************/
705#define MCG_C6_LOLIE0 ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Interrupt Enable */
706#define MCG_C6_PLLS ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Select */
707#define MCG_C6_CME0 ((uint8_t)((uint8_t)1 << 5)) /*!< Clock Monitor Enable */
708#define MCG_C6_VDIV0_SHIFT 0 /*!< VCO 0 Divider (shift) */
709#define MCG_C6_VDIV0_MASK ((uint8_t)((uint8_t)0x1F << MCG_C6_VDIV0_SHIFT)) /*!< VCO 0 Divider (mask) */
710#define MCG_C6_VDIV0(x) ((uint8_t)(((uint8_t)(x) << MCG_C6_VDIV0_SHIFT) & MCG_C6_VDIV0_MASK)) /*!< VCO 0 Divider */
711
712/************ Bits definition for MCG_S register **************/
713#define MCG_S_LOLS ((uint8_t)((uint8_t)1 << 7)) /*!< Loss of Lock Status */
714#define MCG_S_LOCK0 ((uint8_t)((uint8_t)1 << 6)) /*!< Lock Status */
715#define MCG_S_PLLST ((uint8_t)((uint8_t)1 << 5)) /*!< PLL Select Status */
716#define MCG_S_IREFST ((uint8_t)((uint8_t)1 << 4)) /*!< Internal Reference Status */
717#define MCG_S_CLKST_SHIFT 2 /*!< Clock Mode Status (shift) */
718#define MCG_S_CLKST_MASK ((uint8_t)((uint8_t)0x03 << MCG_S_CLKST_SHIFT)) /*!< Clock Mode Status (mask) */
719#define MCG_S_CLKST(x) ((uint8_t)(((uint8_t)(x) << MCG_S_CLKST_SHIFT) & MCG_S_CLKST_MASK)) /*!< Clock Mode Status */
720#define MCG_S_CLKST_FLL MCG_S_CLKST(0) /*!< Output of the FLL is selected */
721#define MCG_S_CLKST_IRCLK MCG_S_CLKST(1) /*!< Internal reference clock is selected */
722#define MCG_S_CLKST_ERCLK MCG_S_CLKST(2) /*!< External reference clock is selected */
723#define MCG_S_CLKST_PLL MCG_S_CLKST(3) /*!< Output of the PLL is selected */
724#define MCG_S_OSCINIT0 ((uint8_t)((uint8_t)1 << 1)) /*!< OSC Initialization */
725#define MCG_S_IRCST ((uint8_t)((uint8_t)1 << 0)) /*!< Internal Reference Clock Status */
726
727/************ Bits definition for MCG_SC register **************/
728#define MCG_SC_ATME ((uint8_t)((uint8_t)1 << 7)) /*!< Automatic Trim Machine Enable */
729#define MCG_SC_ATMS ((uint8_t)((uint8_t)1 << 6)) /*!< Automatic Trim Machine Select */
730#define MCG_SC_ATMF ((uint8_t)((uint8_t)1 << 5)) /*!< Automatic Trim Machine Fail Flag */
731#define MCG_SC_FLTPRSRV ((uint8_t)((uint8_t)1 << 4) /*!< FLL Filter Preserve Enable */
732#define MCG_SC_FCRDIV_SHIFT 1 /*!< Fast Clock Internal Reference Divider (shift) */
733#define MCG_SC_FCRDIV_MASK ((uint8_t)((uint8_t)0x07 << MCG_SC_FCRDIV_SHIFT)) /*!< Fast Clock Internal Reference Divider (mask) */
734#define MCG_SC_FCRDIV(x) ((uint8_t)(((uint8_t)(x) << MCG_SC_FCRDIV_SHIFT) & MCG_SC_FCRDIV_MASK)) /*!< Fast Clock Internal Reference Divider */
735#define MCG_SC_FCRDIV_DIV1 MCG_SC_FCRDIV(0) /*!< Divide Factor is 1 */
736#define MCG_SC_FCRDIV_DIV2 MCG_SC_FCRDIV(1) /*!< Divide Factor is 2 */
737#define MCG_SC_FCRDIV_DIV4 MCG_SC_FCRDIV(2) /*!< Divide Factor is 4 */
738#define MCG_SC_FCRDIV_DIV8 MCG_SC_FCRDIV(3) /*!< Divide Factor is 8 */
739#define MCG_SC_FCRDIV_DIV16 MCG_SC_FCRDIV(4) /*!< Divide Factor is 16 */
740#define MCG_SC_FCRDIV_DIV32 MCG_SC_FCRDIV(5) /*!< Divide Factor is 32 */
741#define MCG_SC_FCRDIV_DIV64 MCG_SC_FCRDIV(6) /*!< Divide Factor is 64 */
742#define MCG_SC_FCRDIV_DIV128 MCG_SC_FCRDIV(7) /*!< Divide Factor is 128 */
743#define MCG_SC_LOCS0 ((uint8_t)((uint8_t)1 << 0) /*!< OSC0 Loss of Clock Status */
744
745/*********** Bits definition for MCG_ATCVH register ************/
746#define MCG_ATCVH_ATCVH_SHIFT 0 /*!< MCG Auto Trim Compare Value High Register (shift) */
747#define MCG_ATCVH_ATCVH_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVH_ATCVH_SHIFT)) /*!< MCG Auto Trim Compare Value High Register (mask) */
748#define MCG_ATCVH_ATCVH(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVH_ATCVH_SHIFT) & MCG_ATCVH_ATCVH_MASK)) /*!< MCG Auto Trim Compare Value High Register */
749
750/*********** Bits definition for MCG_ATCVL register ************/
751#define MCG_ATCVL_ATCVL_SHIFT 0 /*!< MCG Auto Trim Compare Value Low Register (shift) */
752#define MCG_ATCVL_ATCVL_MASK ((uint8_t)((uint8_t)0xFF << MCG_ATCVL_ATCVL_SHIFT)) /*!< MCG Auto Trim Compare Value Low Register (mask) */
753#define MCG_ATCVL_ATCVL(x) ((uint8_t)(((uint8_t)(x) << MCG_ATCVL_ATCVL_SHIFT) & MCG_ATCVL_ATCVL_MASK)) /*!< MCG Auto Trim Compare Value Low Register */
754
755/************ Bits definition for MCG_C7 register **************/
756#define MCG_C7_OSCSEL ((uint8_t)((uint8_t)1 << 0)
757
758/************ Bits definition for MCG_C8 register **************/
759#define MCG_C8_LOLRE ((uint8_t)((uint8_t)1 << 6)) /*!< PLL Loss of Lock Reset Enable */
760
761/************ Bits definition for MCG_C9 register **************/
762/* All MCG_C9 bits are reserved on the KL26Z. */
763
764/************ Bits definition for MCG_C10 register *************/
765/* All MCG_C10 bits are reserved on the KL26Z. */
766
767
768/****************************************************************/
769/* */
770/* Serial Peripheral Interface (SPI) */
771/* */
772/****************************************************************/
773
774/*********** Bits definition for SPIx_S register **************/
775#define SPIx_S_SPRF ((uint8_t)0x80) /*!< SPI Read Buffer Full Flag */
776#define SPIx_S_SPMF ((uint8_t)0x40) /*!< SPI Match Flag */
777#define SPIx_S_SPTEF ((uint8_t)0x20) /*!< SPI Transmit Buffer Empty Flag */
778#define SPIx_S_MODF ((uint8_t)0x10) /*!< Master Mode Fault Flag */
779#define SPIx_S_RNFULLF ((uint8_t)0x08) /*!< Receive FIFO nearly full flag */
780#define SPIx_S_TNEAREF ((uint8_t)0x04) /*!< Transmit FIFO nearly empty flag */
781#define SPIx_S_TXFULLF ((uint8_t)0x02) /*!< Transmit FIFO full flag */
782#define SPIx_S_RFIFOEF ((uint8_t)0x01) /*!< SPI read FIFO empty flag */
783
784/*********** Bits definition for SPIx_BR register *************/
785#define SPIx_BR_SPPR_SHIFT 4 /*!< SPI Baud rate Prescaler Divisor */
786#define SPIx_BR_SPPR_MASK ((uint8_t)((uint8_t)0x7 << SPIx_BR_SPPR_SHIFT))
787#define SPIx_BR_SPPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPPR_SHIFT) & SPIx_BR_SPPR_MASK))
788#define SPIx_BR_SPR_SHIFT 0 /*!< SPI Baud rate Divisor */
789#define SPIx_BR_SPR_MASK ((uint8_t)((uint8_t)0x0F << SPIx_BR_SPR_SHIFT))
790#define SPIx_BR_SPR(x) ((uint8_t)(((uint8_t)(x) << SPIx_BR_SPR_SHIFT) & SPIx_BR_SPR_MASK))
791
792/*********** Bits definition for SPIx_C2 register *************/
793#define SPIx_C2_SPMIE ((uint8_t)0x80) /*!< SPI Match Interrupt Enable */
794#define SPIx_C2_SPIMODE ((uint8_t)0x40) /*!< SPI 8-bit or 16-bit mode */
795#define SPIx_C2_TXDMAE ((uint8_t)0x20) /*!< Transmit DMA Enable */
796#define SPIx_C2_MODFEN ((uint8_t)0x10) /*!< Master Mode-Fault Function Enable */
797#define SPIx_C2_BIDIROE ((uint8_t)0x08) /*!< Bidirectional Mode Output Enable */
798#define SPIx_C2_RXDMAE ((uint8_t)0x04) /*!< Receive DMA Enable */
799#define SPIx_C2_SPISWAI ((uint8_t)0x02) /*!< SPI Stop in Wait Mode */
800#define SPIx_C2_SPC0 ((uint8_t)0x01) /*!< SPI Pin Control 0 */
801
802/*********** Bits definition for SPIx_C1 register *************/
803#define SPIx_C1_SPIE ((uint8_t)0x80) /*!< SPI Interrupt Enable */
804#define SPIx_C1_SPE ((uint8_t)0x40) /*!< SPI System Enable */
805#define SPIx_C1_SPTIE ((uint8_t)0x20) /*!< SPI Transmit Interrupt Enable */
806#define SPIx_C1_MSTR ((uint8_t)0x10) /*!< Master/Slave Mode Select */
807#define SPIx_C1_CPOL ((uint8_t)0x08) /*!< Clock Polarity */
808#define SPIx_C1_CPHA ((uint8_t)0x04) /*!< Clock Phase */
809#define SPIx_C1_SSOE ((uint8_t)0x02) /*!< Slave Select Output Enable */
810#define SPIx_C1_LSBFE ((uint8_t)0x01) /*!< LSB First */
811
812/*********** Bits definition for SPIx_ML register *************/
813#define SPIx_ML_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - low byte */
814#define SPIx_ML_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_ML_DATA_SHIFT))
815#define SPIx_ML_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_ML_DATA_SHIFT) & SPIx_ML_DATA_MASK))
816
817/*********** Bits definition for SPIx_MH register *************/
818#define SPIx_MH_DATA_SHIFT 0 /*!< SPI HW Compare value for Match - high byte */
819#define SPIx_MH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_MH_DATA_SHIFT))
820#define SPIx_MH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_MH_DATA_SHIFT) & SPIx_MH_DATA_MASK))
821
822/*********** Bits definition for SPIx_DL register *************/
823#define SPIx_DL_DATA_SHIFT 0 /*!< Data - low byte */
824#define SPIx_DL_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DL_DATA_SHIFT))
825#define SPIx_DL_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DL_DATA_SHIFT) & SPIx_DL_DATA_MASK))
826
827/*********** Bits definition for SPIx_DH register *************/
828#define SPIx_DH_DATA_SHIFT 0 /*!< Data - high byte */
829#define SPIx_DH_DATA_MASK ((uint8_t)((uint8_t)0xFF << SPIx_DH_DATA_SHIFT))
830#define SPIx_DH_DATA(x) ((uint8_t)(((uint8_t)(x) << SPIx_DH_DATA_SHIFT) & SPIx_DH_DATA_MASK))
831
832/*********** Bits definition for SPIx_CI register *************/
833#define SPIx_CI_TXFERR ((uint8_t)0x80) /*!< Transmit FIFO error flag */
834#define SPIx_CI_RXFERR ((uint8_t)0x40) /*!< Receive FIFO error flag */
835#define SPIx_CI_TXFOF ((uint8_t)0x20) /*!< Transmit FIFO overflow flag */
836#define SPIx_CI_RXFOF ((uint8_t)0x10) /*!< Receive FIFO overflow flag */
837#define SPIx_CI_TNEAREFCI ((uint8_t)0x08) /*!< Transmit FIFO nearly empty flag clear interrupt */
838#define SPIx_CI_RNFULLFCI ((uint8_t)0x04) /*!< Receive FIFO nearly full flag clear interrupt */
839#define SPIx_CI_SPTEFCI ((uint8_t)0x02) /*!< Transmit FIFO empty flag clear interrupt */
840#define SPIx_CI_SPRFCI ((uint8_t)0x01) /*!< Receive FIFO full flag clear interrupt */
841
842/*********** Bits definition for SPIx_C3 register *************/
843#define SPIx_C3_TNEAREF_MARK ((uint8_t)0x20) /*!< Transmit FIFO nearly empty watermark */
844#define SPIx_C3_RNFULLF_MARK ((uint8_t)0x10) /*!< Receive FIFO nearly full watermark */
845#define SPIx_C3_INTCLR ((uint8_t)0x08) /*!< Interrupt clearing mechanism select */
846#define SPIx_C3_TNEARIEN ((uint8_t)0x04) /*!< Transmit FIFO nearly empty interrupt enable */
847#define SPIx_C3_RNFULLIEN ((uint8_t)0x02) /*!< Receive FIFO nearly full interrupt enable */
848#define SPIx_C3_FIFOMODE ((uint8_t)0x01) /*!< FIFO mode enable */
849
850/****************************************************************/
851/* */
852/* Inter-Integrated Circuit (I2C): Device dependent part */
853/* */
854/****************************************************************/
855/*********** Bits definition for I2Cx_FLT register ************/
856#define I2Cx_FLT_SHEN ((uint8_t)0x80) /*!< Stop Hold Enable */
857#define I2Cx_FLT_STOPF ((uint8_t)0x40) /*!< I2C Bus Stop Detect Flag */
858#define I2Cx_FLT_STOPIE ((uint8_t)0x20) /*!< I2C Bus Stop Interrupt Enable */
859#define I2Cx_FLT_FLT_SHIFT 0 /*!< I2C Programmable Filter Factor */
860#define I2Cx_FLT_FLT_MASK ((uint8_t)((uint8_t)0x1F << I2Cx_FLT_FLT_SHIFT))
861#define I2Cx_FLT_FLT(x) ((uint8_t)(((uint8_t)(x) << I2Cx_FLT_FLT_SHIFT) & I2Cx_FLT_FLT_MASK))
862
863/****************************************************************/
864/* */
865/* Universal Asynchronous Receiver/Transmitter (UART) */
866/* */
867/****************************************************************/
868/********* Bits definition for UARTx_BDH register *************/
869#define UARTx_BDH_LBKDIE ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Enable */
870#define UARTx_BDH_RXEDGIE ((uint8_t)0x40) /*!< RX Input Active Edge Interrupt Enable */
871#define UARTx_BDH_SBNS ((uint8_t)0x20) /*!< Stop Bit Number Select */
872#define UARTx_BDH_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */
873#define UARTx_BDH_SBR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_BDH_SBR_SHIFT))
874#define UARTx_BDH_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDH_SBR_SHIFT) & UARTx_BDH_SBR_MASK))
875
876/********* Bits definition for UARTx_BDL register *************/
877#define UARTx_BDL_SBR_SHIFT 0 /*!< Baud Rate Modulo Divisor */
878#define UARTx_BDL_SBR_MASK ((uint8_t)((uint8_t)0xFF << UARTx_BDL_SBR_SHIFT))
879#define UARTx_BDL_SBR(x) ((uint8_t)(((uint8_t)(x) << UARTx_BDL_SBR_SHIFT) & UARTx_BDL_SBR_MASK))
880
881/********* Bits definition for UARTx_C1 register **************/
882#define UARTx_C1_LOOPS ((uint8_t)0x80) /*!< Loop Mode Select */
883#define UARTx_C1_DOZEEN ((uint8_t)0x40) /*!< Doze Enable */
884#define UARTx_C1_UARTSWAI ((uint8_t)0x40) /*!< UART Stops in Wait Mode */
885#define UARTx_C1_RSRC ((uint8_t)0x20) /*!< Receiver Source Select */
886#define UARTx_C1_M ((uint8_t)0x10) /*!< 9-Bit or 8-Bit Mode Select */
887#define UARTx_C1_WAKE ((uint8_t)0x08) /*!< Receiver Wakeup Method Select */
888#define UARTx_C1_ILT ((uint8_t)0x04) /*!< Idle Line Type Select */
889#define UARTx_C1_PE ((uint8_t)0x02) /*!< Parity Enable */
890#define UARTx_C1_PT ((uint8_t)0x01) /*!< Parity Type */
891
892/********* Bits definition for UARTx_C2 register **************/
893#define UARTx_C2_TIE ((uint8_t)0x80) /*!< Transmit Interrupt Enable for TDRE */
894#define UARTx_C2_TCIE ((uint8_t)0x40) /*!< Transmission Complete Interrupt Enable for TC */
895#define UARTx_C2_RIE ((uint8_t)0x20) /*!< Receiver Interrupt Enable for RDRF */
896#define UARTx_C2_ILIE ((uint8_t)0x10) /*!< Idle Line Interrupt Enable for IDLE */
897#define UARTx_C2_TE ((uint8_t)0x08) /*!< Transmitter Enable */
898#define UARTx_C2_RE ((uint8_t)0x04) /*!< Receiver Enable */
899#define UARTx_C2_RWU ((uint8_t)0x02) /*!< Receiver Wakeup Control */
900#define UARTx_C2_SBK ((uint8_t)0x01) /*!< Send Break */
901
902/********* Bits definition for UARTx_S1 register **************/
903#define UARTx_S1_TDRE ((uint8_t)0x80) /*!< Transmit Data Register Empty Flag */
904#define UARTx_S1_TC ((uint8_t)0x40) /*!< Transmission Complete Flag */
905#define UARTx_S1_RDRF ((uint8_t)0x20) /*!< Receiver Data Register Full Flag */
906#define UARTx_S1_IDLE ((uint8_t)0x10) /*!< Idle Line Flag */
907#define UARTx_S1_OR ((uint8_t)0x08) /*!< Receiver Overrun Flag */
908#define UARTx_S1_NF ((uint8_t)0x04) /*!< Noise Flag */
909#define UARTx_S1_FE ((uint8_t)0x02) /*!< Framing Error Flag */
910#define UARTx_S1_PF ((uint8_t)0x01) /*!< Parity Error Flag */
911
912/********* Bits definition for UARTx_S2 register **************/
913#define UARTx_S2_LBKDIF ((uint8_t)0x80) /*!< LIN Break Detect Interrupt Flag */
914#define UARTx_S2_RXEDGIF ((uint8_t)0x40) /*!< UART_RX Pin Active Edge Interrupt Flag */
915#define UARTx_S2_MSBF ((uint8_t)0x20) /*!< MSB First */
916#define UARTx_S2_RXINV ((uint8_t)0x10) /*!< Receive Data Inversion */
917#define UARTx_S2_RWUID ((uint8_t)0x08) /*!< Receive Wake Up Idle Detect */
918#define UARTx_S2_BRK13 ((uint8_t)0x04) /*!< Break Character Generation Length */
919#define UARTx_S2_LBKDE ((uint8_t)0x02) /*!< LIN Break Detect Enable */
920#define UARTx_S2_RAF ((uint8_t)0x01) /*!< Receiver Active Flag */
921
922/********* Bits definition for UARTx_C3 register **************/
923#define UARTx_C3_R8T9 ((uint8_t)0x80) /*!< Receive Bit 8 / Transmit Bit 9 */
924#define UARTx_C3_R8 ((uint8_t)0x80) /*!< Ninth Data Bit for Receiver */
925#define UARTx_C3_R9T8 ((uint8_t)0x40) /*!< Receive Bit 9 / Transmit Bit 8 */
926#define UARTx_C3_T8 ((uint8_t)0x40) /*!< Ninth Data Bit for Transmitter */
927#define UARTx_C3_TXDIR ((uint8_t)0x20) /*!< UART_TX Pin Direction in Single-Wire Mode */
928#define UARTx_C3_TXINV ((uint8_t)0x10) /*!< Transmit Data Inversion */
929#define UARTx_C3_ORIE ((uint8_t)0x08) /*!< Overrun Interrupt Enable */
930#define UARTx_C3_NEIE ((uint8_t)0x04) /*!< Noise Error Interrupt Enable */
931#define UARTx_C3_FEIE ((uint8_t)0x02) /*!< Framing Error Interrupt Enable */
932#define UARTx_C3_PEIE ((uint8_t)0x01) /*!< Parity Error Interrupt Enable */
933
934/********* Bits definition for UARTx_D register ***************/
935#define UARTx_D_R7T7 ((uint8_t)0x80) /*!< Read receive data buffer 7 or write transmit data buffer 7 */
936#define UARTx_D_R6T6 ((uint8_t)0x40) /*!< Read receive data buffer 6 or write transmit data buffer 6 */
937#define UARTx_D_R5T5 ((uint8_t)0x20) /*!< Read receive data buffer 5 or write transmit data buffer 5 */
938#define UARTx_D_R4T4 ((uint8_t)0x10) /*!< Read receive data buffer 4 or write transmit data buffer 4 */
939#define UARTx_D_R3T3 ((uint8_t)0x08) /*!< Read receive data buffer 3 or write transmit data buffer 3 */
940#define UARTx_D_R2T2 ((uint8_t)0x04) /*!< Read receive data buffer 2 or write transmit data buffer 2 */
941#define UARTx_D_R1T1 ((uint8_t)0x02) /*!< Read receive data buffer 1 or write transmit data buffer 1 */
942#define UARTx_D_R0T0 ((uint8_t)0x01) /*!< Read receive data buffer 0 or write transmit data buffer 0 */
943#define UARTx_D_RT_SHIFT 0
944#define UARTx_D_RT_MASK ((uint8_t)0xFF)
945
946/********* Bits definition for UARTx_MA1 register *************/
947#define UARTx_MA1_MA_SHIFT 0 /*!< Match Address */
948#define UARTx_MA1_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA1_MA_SHIFT))
949#define UARTx_MA1_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA1_MA_SHIFT) & UARTx_MA1_MA_MASK))
950
951/********* Bits definition for UARTx_MA2 register *************/
952#define UARTx_MA2_MA_SHIFT 0 /*!< Match Address */
953#define UARTx_MA2_MA_MASK ((uint8_t)((uint8_t)0xFF << UARTx_MA2_MA_SHIFT))
954#define UARTx_MA2_MA(x) ((uint8_t)(((uint8_t)(x) << UARTx_MA2_MA_SHIFT) & UARTx_MA2_MA_MASK))
955
956/********* Bits definition for UARTx_C4 register **************/
957#define UARTx_C4_TDMAS ((uint8_t)0x80) /*!< Transmitter DMA Select */
958#define UARTx_C4_RDMAS ((uint8_t)0x20) /*!< Receiver Full DMA Select */
959#define UARTx_C4_MAEN1 ((uint8_t)0x80) /*!< Match Address Mode Enable 1 */
960#define UARTx_C4_MAEN2 ((uint8_t)0x40) /*!< Match Address Mode Enable 2 */
961#define UARTx_C4_M10 ((uint8_t)0x20) /*!< 10-bit Mode Select */
962#define UARTx_C4_OSR_SHIFT 0 /*!< Over Sampling Ratio */
963#define UARTx_C4_OSR_MASK ((uint8_t)((uint8_t)0x1F << UARTx_C4_OSR_SHIFT))
964#define UARTx_C4_OSR(x) ((uint8_t)(((uint8_t)(x) << UARTx_C4_OSR_SHIFT) & UARTx_C4_OSR_MASK))
965
966/********* Bits definition for UARTx_C5 register **************/
967#define UARTx_C5_TDMAE ((uint8_t)0x80) /*!< Transmitter DMA Enable */
968#define UARTx_C5_RDMAE ((uint8_t)0x20) /*!< Receiver Full DMA Enable */
969#define UARTx_C5_BOTHEDGE ((uint8_t)0x02) /*!< Both Edge Sampling */
970#define UARTx_C5_RESYNCDIS ((uint8_t)0x01) /*!< Resynchronization Disable */
971
972/****************************************************************/
973/* */
974/* Power Management Controller (PMC) */
975/* */
976/****************************************************************/
977
978/* Device independent */
979
980/****************************************************************/
981/* */
982/* Timer/PWM Module (TPM) */
983/* */
984/****************************************************************/
985/********** Bits definition for TPMx_SC register ***************/
986#define TPMx_SC_DMA ((uint32_t)0x100) /*!< DMA Enable */
987#define TPMx_SC_TOF ((uint32_t)0x80) /*!< Timer Overflow Flag */
988#define TPMx_SC_TOIE ((uint32_t)0x40) /*!< Timer Overflow Interrupt Enable */
989#define TPMx_SC_CPWMS ((uint32_t)0x20) /*!< Center-aligned PWM Select */
990#define TPMx_SC_CMOD_SHIFT 3 /*!< Clock Mode Selection */
991#define TPMx_SC_CMOD_MASK ((uint32_t)((uint32_t)0x3 << TPMx_SC_CMOD_SHIFT))
992#define TPMx_SC_CMOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_CMOD_SHIFT) & TPMx_SC_CMOD_MASK))
993#define TPMx_SC_PS_SHIFT 0 /*!< Prescale Factor Selection */
994#define TPMx_SC_PS_MASK ((uint32_t)((uint32_t)0x7 << TPMx_SC_PS_SHIFT))
995#define TPMx_SC_PS(x) ((uint32_t)(((uint32_t)(x) << TPMx_SC_PS_SHIFT) & TPMx_SC_PS_MASK))
996
997#define TPMx_SC_CMOD_DISABLE TPMx_SC_CMOD(0)
998#define TPMx_SC_CMOD_LPTPM_CLK TPMx_SC_CMOD(1)
999#define TPMx_SC_CMOD_LPTPM_EXTCLK TPMx_SC_CMOD(2)
1000
1001/********** Bits definition for TPMx_CNT register **************/
1002#define TPMx_CNT_COUNT_SHIFT 0 /*!< Counter Value */
1003#define TPMx_CNT_COUNT_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CNT_COUNT_SHIFT))
1004#define TPMx_CNT_COUNT(x) ((uint32_t)(((uint32_t)(x) << TPMx_CNT_COUNT_SHIFT) & TPMx_CNT_COUNT_MASK))
1005
1006/********** Bits definition for TPMx_MOD register **************/
1007#define TPMx_MOD_MOD_SHIFT 0 /*!< Modulo Value */
1008#define TPMx_MOD_MOD_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_MOD_MOD_SHIFT))
1009#define TPMx_MOD_MOD(x) ((uint32_t)(((uint32_t)(x) << TPMx_MOD_MOD_SHIFT) & TPMx_MOD_MOD_MASK))
1010
1011/********** Bits definition for TPMx_CnSC register *************/
1012#define TPMx_CnSC_CHF ((uint32_t)0x80) /*!< Channel Flag */
1013#define TPMx_CnSC_CHIE ((uint32_t)0x40) /*!< Channel Interrupt Enable */
1014#define TPMx_CnSC_MSB ((uint32_t)0x20) /*!< Channel Mode Select */
1015#define TPMx_CnSC_MSA ((uint32_t)0x10) /*!< Channel Mode Select */
1016#define TPMx_CnSC_ELSB ((uint32_t)0x8) /*!< Edge or Level Select */
1017#define TPMx_CnSC_ELSA ((uint32_t)0x4) /*!< Edge or Level Select */
1018#define TPMx_CnSC_DMA ((uint32_t)0x1) /*!< DMA Enable */
1019
1020/********** Bits definition for TPMx_CnV register **************/
1021#define TPMx_CnV_VAL_SHIFT 0 /*!< Channel Value */
1022#define TPMx_CnV_VAL_MASK ((uint32_t)((uint32_t)0xFFFF << TPMx_CnV_VAL_SHIFT))
1023#define TPMx_CnV_VAL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CnV_VAL_SHIFT) & TPMx_CnV_VAL_MASK))
1024
1025/********* Bits definition for TPMx_STATUS register ************/
1026#define TPMx_STATUS_TOF ((uint32_t)0x100) /*!< Timer Overflow Flag */
1027#define TPMx_STATUS_CH5F ((uint32_t)0x20) /*!< Channel 5 Flag */
1028#define TPMx_STATUS_CH4F ((uint32_t)0x10) /*!< Channel 4 Flag */
1029#define TPMx_STATUS_CH3F ((uint32_t)0x8) /*!< Channel 3 Flag */
1030#define TPMx_STATUS_CH2F ((uint32_t)0x4) /*!< Channel 2 Flag */
1031#define TPMx_STATUS_CH1F ((uint32_t)0x2) /*!< Channel 1 Flag */
1032#define TPMx_STATUS_CH0F ((uint32_t)0x1) /*!< Channel 0 Flag */
1033
1034/********** Bits definition for TPMx_CONF register *************/
1035#define TPMx_CONF_TRGSEL_SHIFT 24 /*!< Trigger Select */
1036#define TPMx_CONF_TRGSEL_MASK ((uint32_t)((uint32_t)0xF << TPMx_CONF_TRGSEL_SHIFT))
1037#define TPMx_CONF_TRGSEL(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_TRGSEL_SHIFT) & TPMx_CONF_TRGSEL_MASK))
1038#define TPMx_CONF_CROT ((uint32_t)0x40000) /*!< Counter Reload On Trigger */
1039#define TPMx_CONF_CSOO ((uint32_t)0x20000) /*!< Counter Stop On Overflow */
1040#define TPMx_CONF_CSOT ((uint32_t)0x10000) /*!< Counter Start on Trigger */
1041#define TPMx_CONF_GTBEEN ((uint32_t)0x200) /*!< Global time base enable */
1042#define TPMx_CONF_DBGMODE_SHIFT 6 /*!< Debug Mode */
1043#define TPMx_CONF_DBGMODE_MASK ((uint32_t)((uint32_t)0x3 << TPMx_CONF_DBGMODE_SHIFT))
1044#define TPMx_CONF_DBGMODE(x) ((uint32_t)(((uint32_t)(x) << TPMx_CONF_DBGMODE_SHIFT) & TPMx_CONF_DBGMODE_MASK))
1045#define TPMx_CONF_DOZEEN ((uint32_t)0x20) /*!< Doze Enable */
1046
1047/****************************************************************/
1048/* */
1049/* USB OTG: device dependent parts */
1050/* */
1051/****************************************************************/
1052/******** Bits definition for USBx_ADDINFO register ***********/
1053#define USBx_ADDINFO_IRQNUM_SHIFT 6 /*!< Assigned Interrupt Request Number */
1054#define USBx_ADDINFO_IRQNUM_MASK ((uint8_t)((uint8_t)0x1F << USBx_ADDINFO_IRQNUM_SHIFT))
1055
1056/******** Bits definition for USBx_OTGISTAT register **********/
1057#define USBx_OTGISTAT_IDCHG ((uint8_t)0x80) /*!< Change in the ID Signal from the USB connector is sensed. */
1058#define USBx_OTGISTAT_ONEMSEC ((uint8_t)0x40) /*!< Set when the 1 millisecond timer expires. */
1059#define USBx_OTGISTAT_LINE_STATE_CHG ((uint8_t)0x20) /*!< Set when the USB line state changes. */
1060#define USBx_OTGISTAT_SESSVLDCHG ((uint8_t)0x08) /*!< Set when a change in VBUS is detected indicating a session valid or a session no longer valid. */
1061#define USBx_OTGISTAT_B_SESS_CHG ((uint8_t)0x04) /*!< Set when a change in VBUS is detected on a B device. */
1062#define USBx_OTGISTAT_AVBUSCHG ((uint8_t)0x01) /*!< Set when a change in VBUS is detected on an A device. */
1063
1064/******** Bits definition for USBx_OTGICR register ************/
1065#define USBx_OTGICR_IDEN ((uint8_t)0x80) /*!< ID Interrupt Enable */
1066#define USBx_OTGICR_ONEMSECEN ((uint8_t)0x40) /*!< One Millisecond Interrupt Enable */
1067#define USBx_OTGICR_LINESTATEEN ((uint8_t)0x20) /*!< Line State Change Interrupt Enable */
1068#define USBx_OTGICR_SESSVLDEN ((uint8_t)0x08) /*!< Session Valid Interrupt Enable */
1069#define USBx_OTGICR_BSESSEN ((uint8_t)0x04) /*!< B Session END Interrupt Enable */
1070#define USBx_OTGICR_AVBUSEN ((uint8_t)0x01) /*!< A VBUS Valid Interrupt Enable */
1071
1072/******** Bits definition for USBx_OTGSTAT register ***********/
1073#define USBx_OTGSTAT_ID ((uint8_t)0x80) /*!< Indicates the current state of the ID pin on the USB connector */
1074#define USBx_OTGSTAT_ONEMSECEN ((uint8_t)0x40) /*!< This bit is reserved for the 1ms count, but it is not useful to software. */
1075#define USBx_OTGSTAT_LINESTATESTABLE ((uint8_t)0x20) /*!< Indicates that the internal signals that control the LINE_STATE_CHG field of OTGISTAT are stable for at least 1 millisecond. */
1076#define USBx_OTGSTAT_SESS_VLD ((uint8_t)0x08) /*!< Session Valid */
1077#define USBx_OTGSTAT_BSESSEND ((uint8_t)0x04) /*!< B Session End */
1078#define USBx_OTGSTAT_AVBUSVLD ((uint8_t)0x01) /*!< A VBUS Valid */
1079
1080/******** Bits definition for USBx_OTGCTL register ************/
1081#define USBx_OTGCTL_DPLOW ((uint8_t)0x20) /*!< D+ Data Line pull-down resistor enable */
1082#define USBx_OTGCTL_DMLOW ((uint8_t)0x10) /*!< D– Data Line pull-down resistor enable */
1083#define USBx_OTGCTL_OTGEN ((uint8_t)0x04) /*!< On-The-Go pullup/pulldown resistor enable */
1084
1085/******** Bits definition for USBx_ISTAT register *************/
1086#define USBx_ISTAT_ATTACH ((uint8_t)0x40) /*!< Attach interrupt */
1087
1088/******** Bits definition for USBx_INTEN register ***************/
1089#define USBx_INTEN_ATTACHEN ((uint8_t)0x40) /*!< ATTACH interrupt enable */
1090
1091/******** Bits definition for USBx_CTL register *****************/
1092#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */
1093#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */
1094#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */
1095
1096/******** Bits definition for USBx_ADDR register ****************/
1097#define USBx_ADDR_LSEN ((uint8_t)0x80) /*!< Low Speed Enable bit */
1098
1099/******** Bits definition for USBx_TOKEN register ***************/
1100#define USBx_TOKEN_TOKENPID_SHIFT 4 /*!< Contains the token type executed by the USB module. */
1101#define USBx_TOKEN_TOKENPID_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENPID_SHIFT))
1102#define USBx_TOKEN_TOKENPID(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENPID_SHIFT) & USBx_TOKEN_TOKENPID_MASK))
1103#define USBx_TOKEN_TOKENENDPT_SHIFT 0 /*!< Holds the Endpoint address for the token command. */
1104#define USBx_TOKEN_TOKENENDPT_MASK ((uint8_t)((uint8_t)0x0F << USBx_TOKEN_TOKENENDPT_SHIFT))
1105#define USBx_TOKEN_TOKENENDPT(x) ((uint8_t)(((uint8_t)(x) << USBx_TOKEN_TOKENENDPT_SHIFT) & USBx_TOKEN_TOKENENDPT_MASK))
1106#define USBx_TOKEN_TOKENPID_OUT 0x1
1107#define USBx_TOKEN_TOKENPID_IN 0x9
1108#define USBx_TOKEN_TOKENPID_SETUP 0xD
1109
1110/******** Bits definition for USBx_ENDPTn register **************/
1111#define USBx_ENDPTn_HOSTWOHUB ((uint8_t)0x80)
1112#define USBx_ENDPTn_RETRYDIS ((uint8_t)0x40)
1113
1114/****************************************************************/
1115/* */
1116/* Reset Control Module (RCM) */
1117/* */
1118/****************************************************************/
1119
1120/* Only device independent parts */
1121
1122/****************************************************************/
1123/* */
1124/* System Mode Controller (SMC) */
1125/* */
1126/****************************************************************/
1127
1128/* Device independent */
1129
1130/****************************************************************/
1131/* */
1132/* Digital-to-Analog Converter (DAC) */
1133/* */
1134/****************************************************************/
1135
1136/* Mostly Device independent */
1137
1138#define DACx_C1_DACBFMD_SHIFT 2 /*!< DAC Buffer Work Mode Select */
1139#define DACx_C1_DACBFMD_MASK ((uint8_t)((uint8_t)0x01 << DACx_C1_DACBFMD_ SHIFT))
1140#define DACx_C1_DACBFMD(x) ((uint8_t)(((uint8_t)(x) << DACx_C1_DACBFMD_SHIFT) & DACx_C1_DACBFMD_MASK))
1141
1142#define DACx_C1_DACBFMD_MODE_NORMAL 0
1143#define DACx_C1_DACBFMD_MODE_OTS 1
1144
1145/****************************************************************/
1146/* */
1147/* Real Time Clock (RTC) */
1148/* */
1149/****************************************************************/
1150
1151/* Device independent */
1152
1153/****************************************************************/
1154/* */
1155/* Comparator (CMP) */
1156/* */
1157/****************************************************************/
1158
1159/* Device independent */
1160
1161/****************************************************************/
1162/* */
1163/* Flash Memory Module (FTFA) */
1164/* */
1165/****************************************************************/
1166
1167/* Device independent */
1168
1169#endif /* _KL26Z_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2025-08-30 18:02:47 +0100