initHEADmaster

792 files changed, 328310 insertions, 0 deletions

diff --git a/lib/chibios-contrib/os/.keep b/lib/chibios-contrib/os/.keep
new file mode 100644
index 000000000..e69de29bb
--- /dev/null
+++ b/lib/chibios-contrib/os/.keep
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h
new file mode 100644
index 000000000..e16d32412
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x.h
@@ -0,0 +1,254 @@
+/*
+ * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#ifndef _HT32F165x_H_
+#define _HT32F165x_H_
+
+#if defined(HT32F1653) || defined(HT32F1654)
+    #define HT32F1653_4
+#elif defined(HT32F1655) || defined(HT32F1656)
+    #define HT32F1655_6
+#else
+    #error "Unknown HT32 device"
+#endif
+
+#if defined(HT32F1653_4) || defined(HT32F1655_6)
+    #define HT32
+    #define HT32F165x
+#endif
+
+/*
+ * ==============================================================
+ * ---------- Interrupt Number Definition -----------------------
+ * ==============================================================
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ****************/
+    InitialSP_IRQn                = -16,
+    InitialPC_IRQn                = -15,
+    NonMaskableInt_IRQn           = -14,
+    HardFault_IRQn                = -13,
+    MemoryManagement_IRQn         = -12,
+    BusFault_IRQn                 = -11,
+    UsageFault_IRQn               = -10,
+
+    SVCall_IRQn                   = -5,
+    DebugMonitor_IRQn             = -4,
+
+    PendSV_IRQn                   = -2,
+    SysTick_IRQn                  = -1,
+
+/******  HT32F165x Specific Interrupt Numbers ***********************/
+    CKRDY_IRQn                    = 0,
+    LVD_IRQn                      = 1,
+    BOD_IRQn                      = 2,
+    WDT_IRQn                      = 3,
+    RTC_IRQn                      = 4,
+    FMC_IRQn                      = 5,
+    EVWUP_IRQn                    = 6,
+    LPWUP_IRQn                    = 7,
+    EXTI0_IRQn                    = 8,
+    EXTI1_IRQn                    = 9,
+    EXTI2_IRQn                    = 10,
+    EXTI3_IRQn                    = 11,
+    EXTI4_IRQn                    = 12,
+    EXTI5_IRQn                    = 13,
+    EXTI6_IRQn                    = 14,
+    EXTI7_IRQn                    = 15,
+    EXTI8_IRQn                    = 16,
+    EXTI9_IRQn                    = 17,
+    EXTI10_IRQn                   = 18,
+    EXTI11_IRQn                   = 19,
+    EXTI12_IRQn                   = 20,
+    EXTI13_IRQn                   = 21,
+    EXTI14_IRQn                   = 22,
+    EXTI15_IRQn                   = 23,
+    COMP_IRQn                     = 24,
+    ADC_IRQn                      = 25,
+
+    MCTM0_BRK_IRQn                = 27,
+    MCTM0_UP_IRQn                 = 28,
+    MCTM0_TR_UP2_IRQn             = 29,
+    MCTM0_CC_IRQn                 = 30,
+    MCTM1_BRK_IRQn                = 31,
+    MCTM1_UP_IRQn                 = 32,
+    MCTM1_TR_UP2_IRQn             = 33,
+    MCTM1_CC_IRQn                 = 34,
+    GPTM0_IRQn                    = 35,
+    GPTM1_IRQn                    = 36,
+
+    BFTM0_IRQn                    = 41,
+    BFTM1_IRQn                    = 42,
+    I2C0_IRQn                     = 43,
+    I2C1_IRQn                     = 44,
+    SPI0_IRQn                     = 45,
+    SPI1_IRQn                     = 46,
+    USART0_IRQn                   = 47,
+    USART1_IRQn                   = 48,
+    UART0_IRQn                    = 49,
+    UART1_IRQn                    = 50,
+    SCI_IRQn                      = 51,
+    I2C_IRQn                      = 52,
+    USB_IRQn                      = 53,
+
+    PDMA_CH0_IRQn                 = 55,
+    PDMA_CH1_IRQn                 = 56,
+    PDMA_CH2_IRQn                 = 57,
+    PDMA_CH3_IRQn                 = 58,
+    PDMA_CH4_IRQn                 = 59,
+    PDMA_CH5_IRQn                 = 60,
+    PDMA_CH6_IRQn                 = 61,
+    PDMA_CH7_IRQn                 = 62,
+
+    EBI_IRQn                      = 68,
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @brief HT32F165x Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __FPU_PRESENT           0
+#define __MPU_PRESENT           0
+#define __NVIC_PRIO_BITS        4
+#define __Vendor_SysTickConfig  0
+#define __CM3_REV               0x0201
+
+#include "core_cm3.h"           /* Cortex-M3 processor and core peripherals */
+
+/****************************************************************/
+/*                  Peripheral memory map                       */
+/****************************************************************/
+#define USART0_BASE             ((uint32_t)0x40000000)
+#define UART0_BASE              ((uint32_t)0x40001000)
+#define SPI0_BASE               ((uint32_t)0x40004000)
+#define ADC_BASE                ((uint32_t)0x40010000)
+#if defined(HT32F1655_6)
+#define OPACMP0_BASE            ((uint32_t)0x40018000)
+#define OPACMP1_BASE            ((uint32_t)0x40018100)
+#endif
+#define AFIO_BASE               ((uint32_t)0x40022000)
+#define EXTI_BASE               ((uint32_t)0x40024000)
+#define I2S_BASE                ((uint32_t)0x40026000)
+#define MCTM0_BASE              ((uint32_t)0x4002C000)
+#define MCTM1_BASE              ((uint32_t)0x4002D000)
+
+#define USART1_BASE             ((uint32_t)0x40040000)
+#define UART1_BASE              ((uint32_t)0x40041000)
+#define SCI_BASE                ((uint32_t)0x40043000)
+#define SPI1_BASE               ((uint32_t)0x40044000)
+#define I2C0_BASE               ((uint32_t)0x40048000)
+#define I2C1_BASE               ((uint32_t)0x40049000)
+#if defined(HT32F1653_4)
+#define CMP0_BASE               ((uint32_t)0x40058000)
+#define CMP1_BASE               ((uint32_t)0x40058100)
+#endif
+#define WDT_BASE                ((uint32_t)0x40068000)
+#define RTC_BASE                ((uint32_t)0x4006A000)
+#define PWRCU_BASE              ((uint32_t)0x4006A000)
+#define GPTM0_BASE              ((uint32_t)0x4006E000)
+#define GPTM1_BASE              ((uint32_t)0x4006F000)
+#define BFTM0_BASE              ((uint32_t)0x40076000)
+#define BFTM1_BASE              ((uint32_t)0x40077000)
+
+#define FMC_BASE                ((uint32_t)0x40080000)
+#define CKCU_BASE               ((uint32_t)0x40088000)
+#define RSTCU_BASE              ((uint32_t)0x40088000)
+#define CRC_BASE                ((uint32_t)0x4008A000)
+#define PDMA_BASE               ((uint32_t)0x40090000)
+#define EBI_BASE                ((uint32_t)0x40098000)
+#define USB_BASE                ((uint32_t)0x400A8000)
+#define USB_SRAM_BASE           ((uint32_t)0x400AA000)
+#define GPIO_A_BASE             ((uint32_t)0x400B0000)
+#define GPIO_B_BASE             ((uint32_t)0x400B2000)
+#define GPIO_C_BASE             ((uint32_t)0x400B4000)
+#define GPIO_D_BASE             ((uint32_t)0x400B6000)
+#if defined(HT32F1655_6)
+#define GPIO_E_BASE             ((uint32_t)0x400B8000)
+#endif
+
+// Registers Headers
+#include "ht32f165x_reg.h"
+
+/****************************************************************/
+/*                 Peripheral declaration                       */
+/****************************************************************/
+#define USART0                  ((USART_TypeDef *)  USART0_BASE)
+#define UART0                   ((USART_TypeDef *)  UART0_BASE)
+#define SPI0                    ((SPI_TypeDef *)    SPI0_BASE)
+#define ADC                     ((ADC_TypeDef *)    ADC_BASE)
+#if defined(HT32F1655_6)
+#define OPACMP0                 ((OPACMP_TypeDef *) OPACMP0_BASE)
+#define OPACMP1                 ((OPACMP_TypeDef *) OPACMP1_BASE)
+#endif
+#define AFIO                    ((AFIO_TypeDef *)   AFIO_BASE)
+#define EXTI                    ((EXTI_TypeDef *)   EXTI_BASE)
+#define I2S                     ((I2S_TypeDef *)    I2S_BASE)
+#define MCTM0                   ((TM_TypeDef *)     MCTM0_BASE)
+#define MCTM1                   ((TM_TypeDef *)     MCTM1_BASE)
+
+#define USART1                  ((USART_TypeDef *)  USART1_BASE)
+#define UART1                   ((USART_TypeDef *)  UART1_BASE)
+#define SCI                     ((SCI_TypeDef *)    SCI_BASE)
+#define SPI1                    ((SPI_TypeDef *)    SPI1_BASE)
+#define I2C0                    ((I2C_TypeDef *)    I2C0_BASE)
+#define I2C1                    ((I2C_TypeDef *)    I2C1_BASE)
+#if defined(HT32F1653_4)
+#define CMP0                    ((CMP_TypeDef *)    CMP0_BASE)
+#define CMP1                    ((CMP_TypeDef *)    CMP1_BASE)
+#endif
+#define WDT                     ((WDT_TypeDef *)    WDT_BASE)
+#define RTC                     ((RTC_TypeDef *)    RTC_BASE)
+#define PWRCU                   ((PWRCU_TypeDef *)  PWRCU_BASE)
+#define GPTM0                   ((TM_TypeDef *)     GPTM0_BASE)
+#define GPTM1                   ((TM_TypeDef *)     GPTM1_BASE)
+#define BFTM0                   ((BFTM_TypeDef *)   BFTM0_BASE)
+#define BFTM1                   ((BFTM_TypeDef *)   BFTM1_BASE)
+
+#define FMC                     ((FMC_TypeDef *)    FMC_BASE)
+#define CKCU                    ((CKCU_TypeDef *)   CKCU_BASE)
+#define RSTCU                   ((RSTCU_TypeDef *)  RSTCU_BASE)
+#define CRC                     ((CRC_TypeDef *)    CRC_BASE)
+#define PDMA                    ((PDMA_TypeDef *)   PDMA_BASE)
+#define EBI                     ((EBI_TypeDef *)    EBI_BASE)
+#define USB                     ((USB_TypeDef *)    USB_BASE)
+
+#define GPIOA                   ((GPIO_TypeDef *)   GPIO_A_BASE)
+#define GPIO_A GPIOA
+#define GPIOB                   ((GPIO_TypeDef *)   GPIO_B_BASE)
+#define GPIO_B GPIOB
+#define GPIOC                   ((GPIO_TypeDef *)   GPIO_C_BASE)
+#define GPIO_C GPIOC
+#define GPIOD                   ((GPIO_TypeDef *)   GPIO_D_BASE)
+#define GPIO_D GPIOD
+#if defined(HT32F1655_6)
+#define GPIOE                   ((GPIO_TypeDef *)   GPIO_E_BASE)
+#define GPIO_E GPIOE
+#endif
+
+#endif
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h
new file mode 100644
index 000000000..b47416b56
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F165x/ht32f165x_reg.h
@@ -0,0 +1,679 @@
+#ifndef HT32F165x_REG_H
+#define HT32F165x_REG_H
+
+#ifndef __IO
+    #define __IO volatile
+#endif
+
+// Constants
+// /////////////////////////////////////////////////////////////////////////////
+#define AFIO_DEFAULT    0
+#define AFIO_GPIO       1
+#define AFIO_ADC        2
+#define AFIO_CMP        3
+#define AFIO_TM         4
+#define AFIO_SPI        5
+#define AFIO_USART      6
+#define AFIO_I2C        7
+#define AFIO_SMC        8
+#define AFIO_EBI        9
+#define AFIO_I2S        10
+#define AFIO_OTHER      15
+
+// Flash Memory Controller
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t TADR;           //!< 0x000          Flash Target Address Register
+  __IO uint32_t WRDR;           //!< 0x004          Flash Write Data Register
+       uint32_t RESERVED0[1];   //!< 0x008          Reserved
+  __IO uint32_t OCMR;           //!< 0x00C          Flash Operation Command Register
+  __IO uint32_t OPCR;           //!< 0x010          Flash Operation Control Register
+  __IO uint32_t OIER;           //!< 0x014          Flash Operation Interrupt Enable Register
+  __IO uint32_t OISR;           //!< 0x018          Flash Operation Interrupt and Status Register
+       uint32_t RESERVED1[1];   //!< 0x01C          Reserved
+  __IO uint32_t PPSR[4];        //!< 0x020 ~ 0x02C  Flash Page Erase/Program Protection Status Register
+  __IO uint32_t CPSR;           //!< 0x030          Flash Security Protection Status Register
+       uint32_t RESERVED2[51];  //!< 0x034 ~ 0x0FC  Reserved
+  __IO uint32_t VMCR;           //!< 0x100          Flash Vector Mapping Control Register
+       uint32_t RESERVED3[31];  //!< 0x104 ~ 0x17C  Reserved
+  __IO uint32_t MDID;           //!< 0x180          Manufacturer and Device ID Register
+  __IO uint32_t PNSR;           //!< 0x184          Flash Page Number Status Register
+  __IO uint32_t PSSR;           //!< 0x188          Flash Page Size Status Register
+#if defined(HT32F165x)
+       uint32_t RESERVED4[29];  //!< 0x18C ~ 0x1FC  Reserved
+#else
+  __IO uint32_t DID;            //!< 0x18C          Device ID Register
+       uint32_t RESERVED4[28];  //!< 0x190 ~ 0x1FC  Reserved
+#endif
+  __IO uint32_t CFCR;           //!< 0x200          Flash Cache and Pre-fetch Control Register
+       uint32_t RESERVED5[63];  //!< 0x204 ~ 0x2FC  Reserved
+  __IO uint32_t SBVT[4];        //!< 0x300 ~ 0x30C  SRAM Booting Vector (4x32Bit)
+#if defined(HT32F165x)
+#else
+  __IO uint32_t CID[4];         //!< 0x310 ~ 0x31C  Custom ID Register
+#endif
+} FMC_TypeDef;
+
+#define FMC_OCMR_CMD_MASK           (0xF << 0)
+#define FMC_OCMR_CMD_IDLE           (0x0 << 0)
+#define FMC_OCMR_CMD_WORD_PROGRAM   (0x4 << 0)
+#define FMC_OCMR_CMD_PAGE_ERASE     (0x8 << 0)
+#define FMC_OCMR_CMD_MASS_ERASE     (0xA << 0)
+#define FMC_OPCR_OPM_MASK           (0xF << 1)
+#define FMC_OPCR_OPM_IDLE           (0x6 << 1)
+#define FMC_OPCR_OPM_COMMIT         (0xA << 1)
+#define FMC_OPCR_OPM_FINISHED       (0xE << 1)
+#define FMC_CFCR_CE                 (1U << 12)
+#define FMC_CFCR_WAIT_MASK          (7U << 0)
+#define FMC_CFCR_WAIT_0             (1U)
+#define FMC_CFCR_WAIT_1             (2U)
+#define FMC_CFCR_WAIT_2             (3U)
+
+// Power Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+       uint32_t RESERVE0[64];
+  __IO uint32_t BAKSR;          //!< 0x000          Status Register
+  __IO uint32_t BAKCR;          //!< 0x004          Control Register
+  __IO uint32_t BAKTEST;        //!< 0x008          Test Register
+  __IO uint32_t HSIRCR;         //!< 0x00C          HSI Ready Counter Control Register
+  __IO uint32_t LVDCSR;         //!< 0x010          Low Voltage/Brown Out Detect Control and Status Register
+       uint32_t RESERVE1[59];   //!< 0x014 ~ 0x0FC  Reserved
+  __IO uint32_t BAKREG[10];     //!< 0x100 ~ 0x124  Backup Register 0 ~ 9
+} PWRCU_TypeDef;
+
+// Clock Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t GCFGR;          //!< 0x000          Global Clock Configuration Register
+  __IO uint32_t GCCR;           //!< 0x004          Global Clock Control Register
+  __IO uint32_t GCSR;           //!< 0x008          Global Clock Status Register
+  __IO uint32_t GCIR;           //!< 0x00C          Global Clock Interrupt Register
+       uint32_t RESERVED0[2];   //!< 0x010 ~ 0x014  Reserved
+  __IO uint32_t PLLCFGR;        //!< 0x018          PLL Configuration Register
+  __IO uint32_t PLLCR;          //!< 0x01C          PLL Control Register
+  __IO uint32_t AHBCFGR;        //!< 0x020          AHB Configuration Register
+  __IO uint32_t AHBCCR;         //!< 0x024          AHB Clock Control Register
+  __IO uint32_t APBCFGR;        //!< 0x028          APB Configuration Register
+  __IO uint32_t APBCCR0;        //!< 0x02C          APB Clock Control Register 0
+  __IO uint32_t APBCCR1;        //!< 0x030          APB Clock Control Register 1
+  __IO uint32_t CKST;           //!< 0x034          Clock source status Register
+#if defined(HT32F1653_4)
+  __IO uint32_t APBPCSR0;       //!< 0x038          APB Peripheral Clock Selection Register 0
+  __IO uint32_t APBPCSR1;       //!< 0x03C          APB Peripheral Clock Selection Register 1
+  __IO uint32_t HSICR;          //!< 0x040          HSI Control Register
+  __IO uint32_t HSIATCR;        //!< 0x044          HSI Auto Trimming Counter Register
+#else
+       uint32_t RESERVED1[4];   //!< 0x038 ~ 0x044  Reserved
+#endif
+       uint32_t RESERVED2[174]; //!< 0x048 ~ 0x2FC  Reserved
+  __IO uint32_t LPCR;           //!< 0x300          Low Power Control Register
+  __IO uint32_t MCUDBGCR;       //!< 0x304          MCU Debug Control Register
+} CKCU_TypeDef;
+
+#define CKCU_GCFGR_LPMOD_MASK       (7U << 29)
+#define CKCU_GCFGR_USBPRE_MASK      (3U << 22)
+#define CKCU_GCFGR_URPRE_MASK       (3U << 20)
+#define CKCU_GCFGR_PLLSRC           (1U << 8)
+#define CKCU_GCFGR_CKOUTSRC_MASK    (7U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_REF  (0U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_AHB  (1U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_SYS  (2U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_HSE  (3U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_HSI  (4U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_LSE  (5U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_LSI  (6U << 0)
+#define CKCU_GCCR_PSRCEN            (1U << 17)
+#define CKCU_GCCR_CKMEN             (1U << 16)
+#define CKCU_GCCR_HSIEN             (1U << 11)
+#define CKCU_GCCR_HSEEN             (1U << 10)
+#define CKCU_GCCR_PLLEN             (1U << 9)
+#define CKCU_GCCR_SW_MASK           (3U << 0)
+#define CKCU_GCCR_SW_PLL            (1U << 0)
+#define CKCU_GCCR_SW_HSE            (2U << 0)
+#define CKCU_GCCR_SW_HSI            (3U << 0)
+#define CKCU_GCSR_LSIRDY            (1U << 5)
+#define CKCU_GCSR_LSERDY            (1U << 4)
+#define CKCU_GCSR_HSIRDY            (1U << 3)
+#define CKCU_GCSR_HSERDY            (1U << 2)
+#define CKCU_GCSR_PLLRDY            (1U << 1)
+#define CKCU_PLLCFGR_PFBD_MASK      (0x3fU << 23)
+#define CKCU_PLLCFGR_POTD_MASK      (3U << 21)
+#define CKCU_PLLCR_PLLBPS           (1U << 31)
+#define CKCU_AHBCFGR_AHBPRE_MASK    (3U << 0)
+#define CKCU_AHBCCR_PAEN            (1U << 16)
+#define CKCU_AHBCCR_CRCEN           (1U << 13)
+#define CKCU_AHBCCR_EBIEN           (1U << 12)
+#define CKCU_AHBCCR_CKREFEN         (1U << 11)
+#define CKCU_AHBCCR_USBEN           (1U << 10)
+#define CKCU_APBCFGR_ADCDIV_MASK    (7U << 16)
+#define CKCU_APBCCR0_I2SEN          (1U << 25)
+#define CKCU_APBCCR0_SCIEN          (1U << 24)
+#define CKCU_APBCCR0_EXTIEN         (1U << 15)
+#define CKCU_APBCCR0_AFIOEN         (1U << 14)
+#define CKCU_APBCCR0_UR1EN          (1U << 11)
+#define CKCU_APBCCR0_UR0EN          (1U << 10)
+#define CKCU_APBCCR0_USR1EN         (1U << 9)
+#define CKCU_APBCCR0_USR0EN         (1U << 8)
+#define CKCU_APBCCR0_SPI1EN         (1U << 5)
+#define CKCU_APBCCR0_SPI0EN         (1U << 4)
+#define CKCU_APBCCR0_I2C1EN         (1U << 1)
+#define CKCU_APBCCR0_I2C0EN         (1U << 0)
+#define CKCU_APBCCR1_ADCEN          (1U << 24)
+#define CKCU_APBCCR1_OPA1EN         (1U << 23)
+#define CKCU_APBCCR1_OPA0EN         (1U << 22)
+#define CKCU_APBCCR1_BFTM1EN        (1U << 17)
+#define CKCU_APBCCR1_BFTM0EN        (1U << 16)
+#define CKCU_APBCCR1_GPTM1EN        (1U << 9)
+#define CKCU_APBCCR1_GPTM0EN        (1U << 8)
+#define CKCU_APBCCR1_BKPREN         (1U << 6)
+#define CKCU_APBCCR1_WDTREN         (1U << 4)
+#define CKCU_APBCCR1_MCTM1EN        (1U << 1)
+#define CKCU_APBCCR1_MCTM0EN        (1U << 0)
+#define CKCU_CKST_CKSWST_MASK       (3U << 30)
+#define CKCU_CKST_HSIST_MASK        (7U << 24)
+#define CKCU_CKST_HSEST_MASK        (3U << 16)
+#define CKCU_CKST_PLLST_MASK        (0xfU << 8)
+#define CKCU_LPCR_USBSLEEP          (1U << 8)
+#define CKCU_LPCR_BKISO             (1U << 0)
+
+// Reset Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t GRSR;           //!< 0x000          Global Reset Status Register
+  __IO uint32_t AHBPRSTR;       //!< 0x004          AHB Peripheral Reset Register
+  __IO uint32_t APBPRSTR0;      //!< 0x008          APB Peripheral Reset Register 0
+  __IO uint32_t APBPRSTR1;      //!< 0x00C          APB Peripheral Reset Register 1
+} RSTCU_TypeDef;
+
+#define RSTCU_GRSR_PORSTF           (1U << 3)
+#define RSTCU_GRSR_WDTRSTF          (1U << 2)
+#define RSTCU_GRSR_EXTRSTF          (1U << 1)
+#define RSTCU_GRSR_SYSRSTF          (1U << 0)
+#define RSTCU_AHBPRSTR_PxRST(n)     ((1U << 8) << (n))
+#define RSTCU_AHBPRSTR_CRCRST       (1U << 7)
+#define RSTCU_AHBPRSTR_EBIRST       (1U << 6)
+#define RSTCU_AHBPRSTR_USBRST       (1U << 5)
+#define RSTCU_AHBPRSTR_DMARST       (1U << 0)
+#define RSTCU_APBPRSTR0_I2SRST      (1U << 25)
+#define RSTCU_APBPRSTR0_SCIRST      (1U << 24)
+#define RSTCU_APBPRSTR0_EXTIRST     (1U << 15)
+#define RSTCU_APBPRSTR0_AFIORST     (1U << 14)
+#define RSTCU_APBPRSTR0_UR1RST      (1U << 11)
+#define RSTCU_APBPRSTR0_UR0RST      (1U << 10)
+#define RSTCU_APBPRSTR0_USR1RST     (1U << 9)
+#define RSTCU_APBPRSTR0_USR0RST     (1U << 8)
+#define RSTCU_APBPRSTR0_SPI1RST     (1U << 5)
+#define RSTCU_APBPRSTR0_SPI0RST     (1U << 4)
+#define RSTCU_APBPRSTR0_I2C1RST     (1U << 1)
+#define RSTCU_APBPRSTR0_I2C0RST     (1U << 0)
+#define RSTCU_APBPRSTR1_ADCRST      (1U << 24)
+#define RSTCU_APBPRSTR1_OPA1RST     (1U << 23)
+#define RSTCU_APBPRSTR1_OPA0RST     (1U << 22)
+#define RSTCU_APBPRSTR1_BFTM1RST    (1U << 17)
+#define RSTCU_APBPRSTR1_BFTM0RST    (1U << 16)
+#define RSTCU_APBPRSTR1_GPTM1RST    (1U << 9)
+#define RSTCU_APBPRSTR1_GPTM0RST    (1U << 8)
+#define RSTCU_APBPRSTR1_WDTRST      (1U << 4)
+#define RSTCU_APBPRSTR1_MCTM1RST    (1U << 1)
+#define RSTCU_APBPRSTR1_MCTM0RST    (1U << 0)
+
+// General Purpose I/O
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t DIRCR;          //!< 0x000          Data Direction Control Register
+  __IO uint32_t INER;           //!< 0x004          Input function enable register
+  __IO uint32_t PUR;            //!< 0x008          Pull-Up Selection Register
+  __IO uint32_t PDR;            //!< 0x00C          Pull-Down Selection Register
+  __IO uint32_t ODR;            //!< 0x010          Open Drain Selection Register
+  __IO uint32_t DRVR;           //!< 0x014          Drive Current Selection Register
+  __IO uint32_t LOCKR;          //!< 0x018          Lock Register
+  __IO uint32_t DINR;           //!< 0x01c          Data Input Register
+  __IO uint32_t DOUTR;          //!< 0x020          Data Output Register
+  __IO uint32_t SRR;            //!< 0x024          Output Set and Reset Control Register
+  __IO uint32_t RR;             //!< 0x028          Output Reset Control Register
+} GPIO_TypeDef;
+
+// Alternate Function Input/Output
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t ESSR[2];        //!< 0x000 ~ 0x004  EXTI Source Selection Register 0 ~ 1
+       uint32_t RESERVE0[6];    //!< 0x008 ~ 0x01C  Reserved
+  union {
+    struct {
+  __IO uint32_t GPACFGR[2];     //!< 0x020 ~ 0x024  GPIO Port A Configuration Register 0 ~ 1
+  __IO uint32_t GPBCFGR[2];     //!< 0x028 ~ 0x02C  GPIO Port B Configuration Register 0 ~ 1
+  __IO uint32_t GPCCFGR[2];     //!< 0x030 ~ 0x034  GPIO Port C Configuration Register 0 ~ 1
+  __IO uint32_t GPDCFGR[2];     //!< 0x038 ~ 0x03C  GPIO Port D Configuration Register 0 ~ 1
+#if defined(HT32F1655_6)
+  __IO uint32_t GPECFGR[2];     //!< 0x040 ~ 0x044  GPIO Port E Configuration Register 0 ~ 1
+#endif
+    };
+    // alternate mapping
+    struct {
+  __IO uint32_t GPxCFGR[0][2];  //!< 0x020 ~ 0x044  GPIO Port x Configuration Register 0 ~ 1
+    };
+  };
+} AFIO_TypeDef;
+
+// Nested Vectored Interrupt Controller
+// /////////////////////////////////////////////////////////////////////////////
+// Implemented in Cortex-M3 Headers
+
+// External Interrupt/Event Controller
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CFGR0;          //!< 0x000         EXTI Interrupt 0 Configuration Register
+  __IO uint32_t CFGR1;          //!< 0x004         EXTI Interrupt 1 Configuration Register
+  __IO uint32_t CFGR2;          //!< 0x008         EXTI Interrupt 2 Configuration Register
+  __IO uint32_t CFGR3;          //!< 0x00C         EXTI Interrupt 3 Configuration Register
+  __IO uint32_t CFGR4;          //!< 0x010         EXTI Interrupt 4 Configuration Register
+  __IO uint32_t CFGR5;          //!< 0x014         EXTI Interrupt 5 Configuration Register
+  __IO uint32_t CFGR6;          //!< 0x018         EXTI Interrupt 6 Configuration Register
+  __IO uint32_t CFGR7;          //!< 0x01C         EXTI Interrupt 7 Configuration Register
+  __IO uint32_t CFGR8;          //!< 0x020         EXTI Interrupt 8 Configuration Register
+  __IO uint32_t CFGR9;          //!< 0x024         EXTI Interrupt 9 Configuration Register
+  __IO uint32_t CFGR10;         //!< 0x028         EXTI Interrupt 10 Configuration Register
+  __IO uint32_t CFGR11;         //!< 0x02C         EXTI Interrupt 11 Configuration Register
+  __IO uint32_t CFGR12;         //!< 0x030         EXTI Interrupt 12 Configuration Register
+  __IO uint32_t CFGR13;         //!< 0x034         EXTI Interrupt 13 Configuration Register
+  __IO uint32_t CFGR14;         //!< 0x038         EXTI Interrupt 14 Configuration Register
+  __IO uint32_t CFGR15;         //!< 0x03C         EXTI Interrupt 15 Configuration Register
+  __IO uint32_t CR;             //!< 0x040         EXTI Interrupt Control Register
+  __IO uint32_t EDGEFLGR;       //!< 0x044         EXTI Interrupt Edge Flag Register
+  __IO uint32_t EDGESR;         //!< 0x048         EXTI Interrupt Edge Status Register
+  __IO uint32_t SSCR;           //!< 0x04C         EXTI Interrupt Software Set Command Register
+  __IO uint32_t WAKUPCR;        //!< 0x050         EXTI Interrupt Wakeup Control Register
+  __IO uint32_t WAKUPPOLR;      //!< 0x054         EXTI Interrupt Wakeup Polarity Register
+  __IO uint32_t WAKUPFLG;       //!< 0x058         EXTI Interrupt Wakeup Flag Register
+} EXTI_TypeDef;
+
+// Analog To Digital Converter
+// /////////////////////////////////////////////////////////////////////////////
+
+// Operational Amplifier / Comparator
+// /////////////////////////////////////////////////////////////////////////////
+#if defined(HT32F1653_4)
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Comparator Control Register
+  __IO uint32_t VALR;           //!< 0x004          Comparator Voltage Reference Register
+  __IO uint32_t IER;            //!< 0x008          Comparator Interrupt Enable Register
+  __IO uint32_t TFR;            //!< 0x00C          Comparator Transition Flag Register
+} CMP_TypeDef;
+#else
+typedef struct {
+  __IO uint32_t OPACR;          //!< 0x000          Operational Amplifier Control Register
+  __IO uint32_t OFVCR;          //!< 0x004          Comparator Input Offset Voltage Cancellation Register
+  __IO uint32_t CMPIER;         //!< 0x008          Comparator Interrupt Enable Register
+  __IO uint32_t CMPRSR;         //!< 0x00C          Comparator Raw Status Register
+  __IO uint32_t CMPISR;         //!< 0x010          Comparator Masked Interrupt Status Register
+  __IO uint32_t CMPICLR;        //!< 0x014          Comparator Interrupt Clear Register
+} OPACMP_TypeDef;
+#endif
+
+// Basic Function Timers
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Control Register
+  __IO uint32_t SR;             //!< 0x004          Status Register
+  __IO uint32_t CNTR;           //!< 0x008          Counter Value Register
+  __IO uint32_t CMP;            //!< 0x00C          Compare Value Register
+} BFTM_TypeDef;
+
+#define BFTM_CR_CEN                 (1U << 2)
+#define BFTM_CR_OSM                 (1U << 1)
+#define BFTM_CR_MIEN                (1U << 0)
+#define BFTM_SR_MIF                 (1U << 0)
+
+// General Purpose Timers
+// Motor Control Timers
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CNTCFR;         //!< 0x000          Timer Counter Configuaration Register
+  __IO uint32_t MDCFR;          //!< 0x004          Timer Mode Configuration Register
+  __IO uint32_t TRCFR;          //!< 0x008          Timer Trigger Configuration Register
+       uint32_t RESERVED0[1];   //!< 0x00C          Reserved
+  __IO uint32_t CTR;            //!< 0x010          Timer Counter Register
+       uint32_t RESERVED1[3];   //!< 0x014 ~ 0x01C  Reserved
+  __IO uint32_t CHnICFR[4];     //!< 0x020 ~ 0x02C  Channel n Input Configuration Register
+       uint32_t RESERVED2[4];   //!< 0x030 ~ 0x03C  Reserved
+  __IO uint32_t CHnOCFR[4];     //!< 0x040 ~ 0x04C  Channel n Output Configuration Register
+  __IO uint32_t CHCTR;          //!< 0x050          Channel Control Register
+  __IO uint32_t CHPOLR;         //!< 0x054          Channel Polarity Control Register
+       uint32_t RESERVED3[5];   //!< 0x058 ~ 0x068  Reserved
+  // note: only available as MCTM
+  __IO uint32_t CHBRKCFR;       //!< 0x06C          Channel Break Configuration Register
+  __IO uint32_t CHBRKCTR;       //!< 0x070          Channel Break Control Register
+  // end note
+  __IO uint32_t DICTR;          //!< 0x074          Timer PDMA/Interrupt Control Register
+  __IO uint32_t EVGR;           //!< 0x078          Timer Event Generator Register
+  __IO uint32_t INTSR;          //!< 0x07C          Timer Interrupt Status Register
+  __IO uint32_t CNTR;           //!< 0x080          Timer Counter Register
+  __IO uint32_t PSCR;           //!< 0x084          Timer Prescaler Register
+  __IO uint32_t CRR;            //!< 0x088          Timer Counter Reload Register
+  // note: only available as MCTM
+  __IO uint32_t REPR;           //!< 0x08C          Timer Repetition Register
+  // end note
+  __IO uint32_t CHnCCR[4];      //!< 0x090 ~ 0x09C  Channel n Capture/Compare Register
+  __IO uint32_t CHnACR[4];      //!< 0x0A0 ~ 0x0AC  Channel n Asymmentric Compare Register
+} TM_TypeDef;
+
+#define TM_CNTCFR_CMSEL_MASK        (3U << 16)
+#define TM_CNTCFR_CMSEL_MODE_3      (3U << 16)
+#define TM_CNTCFR_CMSEL_MODE_2      (2U << 16)
+#define TM_CNTCFR_CMSEL_MODE_1      (1U << 16)
+#define TM_CNTCFR_CMSEL_MODE_0      (0U << 16)
+#define TM_CTR_CHCCDS               (1U << 16)
+#define TM_CTR_COMUS                (1U << 9)
+#define TM_CTR_COMPRE               (1U << 8)
+#define TM_CTR_CRBE                 (1U << 1)
+#define TM_CTR_TME                  (1U << 0)
+#define TM_CHnOCFR_CHnPRE           (1U << 4)
+#define TM_CHnOCFR_REFnCE           (1U << 3)
+#define TM_CHnOCFR_CHnOM(n)         ((((n)>>0)&7)|((((n)>>3)&1)<<8))
+#define TM_CHBRKCTR_CHMOE           (1U << 4)
+
+// Real Time Clock
+// /////////////////////////////////////////////////////////////////////////////
+
+// Watchdog Timer
+// /////////////////////////////////////////////////////////////////////////////
+
+// I2C
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Control Register
+  __IO uint32_t IER;            //!< 0x004          Interrupt Enable Register
+  __IO uint32_t ADDR;           //!< 0x008          Address Register
+  __IO uint32_t SR;             //!< 0x00C          Status Register
+  __IO uint32_t SHPGR;          //!< 0x010          SCL High Period Generation Register
+  __IO uint32_t SLPGR;          //!< 0x014          SCL Low Period Generation Register
+  __IO uint32_t DR;             //!< 0x018          Data Register
+  __IO uint32_t TAR;            //!< 0x01C          Target Register
+  __IO uint32_t ADDMR;          //!< 0x020          Address Mask Register
+  __IO uint32_t ADDSR;          //!< 0x024          Address Snoop Register
+  __IO uint32_t TOUT;           //!< 0x028          Timeout Register
+} I2C_TypeDef;
+
+#define I2C_CR_SEQ_FILTER_MASK      (3U << 14)
+#define I2C_CR_SEQ_FILTER_2_PCLK    (2U << 14)
+#define I2C_CR_SEQ_FILTER_1_PCLK    (1U << 14)
+#define I2C_CR_SEQ_FILTER_DISABLE   (0U << 14)
+#define I2C_CR_COMB_FILTER_En       (1U << 13)
+#define I2C_CR_ENTOUT               (1U << 12)
+#define I2C_CR_DMANACK              (1U << 10)
+#define I2C_CR_RXDMAE               (1U << 9)
+#define I2C_CR_TXDMAE               (1U << 8)
+#define I2C_CR_ADRM                 (1U << 7)
+#define I2C_CR_I2CEN                (1U << 3)
+#define I2C_CR_GCEN                 (1U << 2)
+#define I2C_CR_STOP                 (1U << 1)
+#define I2C_CR_AA                   (1U << 0)
+#define I2C_IER_RXBFIE              (1U << 18)
+#define I2C_IER_TXDEIE              (1U << 17)
+#define I2C_IER_RXDNEIE             (1U << 16)
+#define I2C_IER_TOUTIE              (1U << 11)
+#define I2C_IER_BUSERRIE            (1U << 10)
+#define I2C_IER_RXNACKIE            (1U << 9)
+#define I2C_IER_ARBLOSIE            (1U << 8)
+#define I2C_IER_GCSIE               (1U << 3)
+#define I2C_IER_ADRSIE              (1U << 2)
+#define I2C_IER_STOIE               (1U << 1)
+#define I2C_IER_STAIE               (1U << 0)
+#define I2C_SR_TXNRX                (1U << 21)
+#define I2C_SR_MASTER               (1U << 20)
+#define I2C_SR_BUSBUSY              (1U << 19)
+#define I2C_SR_RXBF                 (1U << 18)
+#define I2C_SR_TXDE                 (1U << 17)
+#define I2C_SR_RXDNE                (1U << 16)
+#define I2C_SR_TOUTF                (1U << 11)
+#define I2C_SR_BUSERR               (1U << 10)
+#define I2C_SR_RXNACK               (1U << 9)
+#define I2C_SR_ARBLOS               (1U << 8)
+#define I2C_SR_GCS                  (1U << 3)
+#define I2C_SR_ADRS                 (1U << 2)
+#define I2C_SR_STO                  (1U << 1)
+#define I2C_SR_STA                  (1U << 0)
+#define I2C_TAR_RWD                 (1U << 10)
+
+// SPI
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR0;            //!< 0x000          Control Register 0
+  __IO uint32_t CR1;            //!< 0x004          Control Register 1
+  __IO uint32_t IER;            //!< 0x008          Interrupt Enable Register
+  __IO uint32_t CPR;            //!< 0x00C          Clock Prescaler Register
+  __IO uint32_t DR;             //!< 0x010          Data Register
+  __IO uint32_t SR;             //!< 0x014          Status Register
+  __IO uint32_t FCR;            //!< 0x018          FIFO Control Register
+  __IO uint32_t FSR;            //!< 0x01C          FIFO Status Register
+  __IO uint32_t FTOCR;          //!< 0x020          FIFO Time Out Counter Register
+} SPI_TypeDef;
+
+#define SPI_CR0_GUADTEN             (1U << 7)
+#define SPI_CR0_DUALEN              (1U << 6)
+#define SPI_CR0_SSELC               (1U << 4)
+#define SPI_CR0_SELOEN              (1U << 3)
+#define SPI_CR0_SPIEN               (1U << 0)
+#define SPI_CR1_MODE                (1U << 14)
+#define SPI_CR1_SELM                (1U << 13)
+#define SPI_CR1_FIRSTBIT            (1U << 12)
+#define SPI_CR1_SELAP               (1U << 11)
+#define SPI_CR1_FORMAT_MASK         (7U << 8)
+#define SPI_CR1_FORMAT_MODE0        (0x1U << 8)
+#define SPI_CR1_FORMAT_MODE1        (0x2U << 8)
+#define SPI_CR1_FORMAT_MODE2        (0x6U << 8)
+#define SPI_CR1_FORMAT_MODE3        (0x5U << 8)
+#define SPI_IER_RXBNEIEN            (1U << 2)
+#define SPI_IER_TXBEIEN             (1U << 0)
+#define SPI_SR_RXBNE                (1U << 2)
+#define SPI_SR_TXE                  (1U << 1)
+#define SPI_SR_TXBE                 (1U << 0)
+#define SPI_FCR_FIFOEN              (1U << 10)
+#define SPI_FSR_TXFS_MASK           (0xfU << 0)
+#define SPI_FSR_RXFS_MASK           (0xfU << 4)
+
+// USART
+// UART
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  union {
+  __IO uint32_t RBR;            //!< 0x000          Receive Buffer Register
+  __IO uint32_t TBR;            //!< 0x000          Transmit Holding Register
+  __IO uint32_t DR;             //!< 0x000          Data Register
+  };
+  __IO uint32_t IER;            //!< 0x004          Interrupt Enable Register
+  __IO uint32_t IIR;            //!< 0x008          Interrupt Identification Register/FIFO Control Register
+  __IO uint32_t FCR;            //!< 0x00C          FIFO Control Register
+  __IO uint32_t LCR;            //!< 0x010          Line Control Register
+  // note: only available as USART
+  __IO uint32_t MODCR;          //!< 0x014          Modem Control Register
+  // end note
+  __IO uint32_t LSR;            //!< 0x018          Line Status Register
+  // note: only available as USART
+  __IO uint32_t MODSR;          //!< 0x01C          Modem Status Register
+  // end note
+  __IO uint32_t TPR;            //!< 0x020          Timing Parameter Register
+  __IO uint32_t MDR;            //!< 0x024          Mode Register
+  // note: only available as USART
+  __IO uint32_t IrDACR;         //!< 0x028          IrDA Control Register
+  __IO uint32_t RS485CR;        //!< 0x02C          RS485 Control Register
+  __IO uint32_t SYNCR;          //!< 0x030          Synchronous Control Register
+  // end note
+  __IO uint32_t FSR;            //!< 0x034          FIFO Status Register
+  __IO uint32_t DLR;            //!< 0x038          Divisor Latch Register
+       uint32_t RESERVED0;      //!< 0x03C          Reserved
+  __IO uint32_t DEGTSTR;        //!< 0x040          Debug/Test Register
+} USART_TypeDef;
+
+#define USART_FCR_FME               (1 << 0)
+#define USART_FCR_RFR               (1 << 1)
+#define USART_FCR_TFR               (1 << 2)
+#define USART_FCR_TFTL_MASK         (0x3 << 4)
+#define USART_FCR_TFTL_0BYTE        (0x0 << 4)
+#define USART_FCR_TFTL_2BYTE        (0x1 << 4)
+#define USART_FCR_TFTL_4BYTE        (0x2 << 4)
+#define USART_FCR_TFTL_8BYTE        (0x3 << 4)
+#define USART_FCR_RFTL_MASK         (0x3 << 6)
+#define USART_FCR_RFTL_1BYTE        (0x0 << 6)
+#define USART_FCR_RFTL_4BYTE        (0x1 << 6)
+#define USART_FCR_RFTL_8BYTE        (0x2 << 6)
+#define USART_FCR_RFTL_14BYTE       (0x3 << 6)
+#define USART_FCR_URTXEN            (1 << 8)
+#define USART_FCR_URRXEN            (1 << 9)
+#define USART_LCR_WLS_MASK          (0x3 << 0)
+#define USART_LCR_WLS_7BIT          (0x0 << 0)
+#define USART_LCR_WLS_8BIT          (0x1 << 0)
+#define USART_LCR_WLS_9BIT          (0x2 << 0)
+#define USART_LCR_NSB               (1 << 2)
+#define USART_LCR_PBE               (1 << 3)
+#define USART_LCR_EPE               (1 << 4)
+#define USART_LCR_SPE               (1 << 5)
+#define USART_LCR_BCB               (1 << 6)
+#define USART_LSR_RFDR              (1 << 0)
+#define USART_LSR_OEI               (1 << 1)
+#define USART_LSR_PEI               (1 << 2)
+#define USART_LSR_FEI               (1 << 3)
+#define USART_LSR_BII               (1 << 4)
+#define USART_LSR_TXFEMPT           (1 << 5)
+#define USART_LSR_TXEMPT            (1 << 6)
+#define USART_LSR_ERRRX             (1 << 7)
+#define USART_LSR_RSADDEF           (1 << 8)
+#define USART_MDR_MODE_MASK         (0x3 << 0)
+#define USART_MDR_MODE_NORMAL       (0x0 << 0)
+#define USART_MDR_MODE_IRDA         (0x1 << 0)
+#define USART_MDR_MODE_RS485        (0x2 << 0)
+#define USART_MDR_MODE_SYNCHRONOUS  (0x3 << 0)
+#define USART_MDR_TRSM              (1 << 2)
+#define USART_MDR_TXDMAEN           (1 << 4)
+#define USART_MDR_RXDMAEN           (1 << 5)
+
+// Smart Card Interface
+// /////////////////////////////////////////////////////////////////////////////
+
+// USB
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CSR;            //!< 0x000          USB Control and Status Register
+  __IO uint32_t IER;            //!< 0x004          USB Interrupt Enable Register
+  __IO uint32_t ISR;            //!< 0x008          USB Interrupt Status Register
+  __IO uint32_t FCR;            //!< 0x00C          USB Frame Count Register
+  __IO uint32_t DEVAR;          //!< 0x010          USB Device Address Register
+  struct {
+    __IO uint32_t CSR;          //!< 0x014          USB Endpoint n Control and Status Register
+    __IO uint32_t IER;          //!< 0x018          USB Endpoint n Interrupt Enable Register
+    __IO uint32_t ISR;          //!< 0x01C          USB Endpoint n Interrupt Status Register
+    __IO uint32_t TCR;          //!< 0x020          USB Endpoint n Transfer Count Register
+    __IO uint32_t CFGR;         //!< 0x024          USB Endpoint n Configuration Register
+  } EP[8];
+} USB_TypeDef;
+
+// USBCSR
+#define USBCSR_FRES         (0x002)        // Force USB Reset Control
+#define USBCSR_PDWN         (0x004)        // Power Down Mode Control
+#define USBCSR_LPMODE       (0x008)        // Low-Power Mode Control
+#define USBCSR_GENRSM       (0x020)        // Resume Request Generation Control
+#define USBCSR_RXDP         (0x040)        // Received DP Line Status
+#define USBCSR_RXDM         (0x080)        // Received DM Line Status
+#define USBCSR_ADRSET       (0x100)        // Device Address Setting Control
+#define USBCSR_SRAMRSTC     (0x200)        // USB SRAM Reset Condition
+#define USBCSR_DPPUEN       (0x400)        // DP Pull Up Enable
+#define USBCSR_DPWKEN       (0x800)        // DP Wake Up Enable
+
+// USBIER
+#define USBIER_UGIE         (0x0001)       // USB global Interrupt Enable
+#define USBIER_SOFIE        (0x0002)       // Start Of Frame Interrupt Enable
+#define USBIER_URSTIE       (0x0004)       // USB Reset Interrupt Enable
+#define USBIER_RSMIE        (0x0008)       // Resume Interrupt Enable
+#define USBIER_SUSPIE       (0x0010)       // Suspend Interrupt Enable
+#define USBIER_ESOFIE       (0x0020)       // Expected Start Of Frame Enable
+#define USBIER_EP0IE        (0x0100)       // Endpoint 0 Interrupt Enable
+#define USBIER_EP1IE        (0x0200)       // Endpoint 1 Interrupt Enable
+#define USBIER_EP2IE        (0x0400)       // Endpoint 2 Interrupt Enable
+#define USBIER_EP3IE        (0x0800)       // Endpoint 3 Interrupt Enable
+#define USBIER_EP4IE        (0x1000)       // Endpoint 4 Interrupt Enable
+#define USBIER_EP5IE        (0x2000)       // Endpoint 5 Interrupt Enable
+#define USBIER_EP6IE        (0x4000)       // Endpoint 6 Interrupt Enable
+#define USBIER_EP7IE        (0x8000)       // Endpoint 7 Interrupt Enable
+
+// USBISR
+#define USBISR_SOFIF        (0x0002)       // Start Of Frame Interrupt Flag
+#define USBISR_URSTIF       (0x0004)       // USB Reset Interrupt Flag
+#define USBISR_RSMIF        (0x0008)       // Resume Interrupt Flag
+#define USBISR_SUSPIF       (0x0010)       // Suspend Interrupt Flag
+#define USBISR_ESOFIF       (0x0020)       // Expected Start Of Frame Interrupt
+#define USBISR_EP0IF        (1U << 8)      // Endpoint 0 Interrupt Flag
+#define USBISR_EP1IF        (1U << 9)      // Endpoint 1 Interrupt Flag
+#define USBISR_EP2IF        (1U << 10)     // Endpoint 2 Interrupt Flag
+#define USBISR_EP3IF        (1U << 11)     // Endpoint 3 Interrupt Flag
+#define USBISR_EP4IF        (1U << 12)     // Endpoint 4 Interrupt Flag
+#define USBISR_EP5IF        (1U << 13)     // Endpoint 5 Interrupt Flag
+#define USBISR_EP6IF        (1U << 14)     // Endpoint 6 Interrupt Flag
+#define USBISR_EP7IF        (1U << 15)     // Endpoint 7 Interrupt Flag
+#define USBISR_EPnIF        (0xFF00)       // Endpoint Interrupt Mask
+
+// USBFCR
+#define USBFCR_FRNUM        (0x7FF)        // Frame Number
+#define USBFCR_SOFLCK       (1U << 16)     // Start-of-Frame Lock Flag
+#define USBFCR_LSOF         (0x3U << 17)   // Lost Start-of-Frame Number
+
+// USBEPnCSR
+#define USBEPnCSR_DTGTX     (0x01)         // Data Toggle Status, for IN transfer
+#define USBEPnCSR_NAKTX     (0x02)         // NAK Status, for IN transfer
+#define USBEPnCSR_STLTX     (0x04)         // STALL Status, for IN transfer
+#define USBEPnCSR_DTGRX     (0x08)         // Data Toggle Status, for OUT transfer
+#define USBEPnCSR_NAKRX     (0x10)         // NAK Status, for OUT transfer
+#define USBEPnCSR_STLRX     (0x20)         // STALL Status, for OUT transfer
+
+// USBEPnIER
+#define USBEPnIER_OTRXIE    (0x001)        // OUT Token Received Interrupt Enable
+#define USBEPnIER_ODRXIE    (0x002)        // OUT Data Received Interrupt Enable
+#define USBEPnIER_ODOVIE    (0x004)        // OUT Data Buffer Overrun Interrupt Enable
+#define USBEPnIER_ITRXIE    (0x008)        // IN Token Received Interrupt Enable
+#define USBEPnIER_IDTXIE    (0x010)        // IN Data Transmitted Interrupt Enable
+#define USBEPnIER_NAKIE     (0x020)        // NAK Transmitted Interrupt Enable
+#define USBEPnIER_STLIE     (0x040)        // STALL Transmitted Interrupt Enable
+#define USBEPnIER_UERIE     (0x080)        // USB Error Interrupt Enable
+#define USBEPnIER_STRXIE    (0x100)        // SETUP Token Received Interrupt Enable
+#define USBEPnIER_SDRXIE    (0x200)        // SETUP Data Received Interrupt Enable
+#define USBEPnIER_SDERIE    (0x400)        // SETUP Data Error Interrupt Enable
+#define USBEPnIER_ZLRXIE    (0x800)        // Zero Length Data Received Interrupt Enable
+
+// USBEPnISR
+#define USBEPnISR_OTRXIF    (0x001)        // OUT Token Received Interrupt Flag
+#define USBEPnISR_ODRXIF    (0x002)        // OUT Data Received Interrupt Flag
+#define USBEPnISR_ODOVIF    (0x004)        // OUT Data Buffer Overrun Interrupt Flag
+#define USBEPnISR_ITRXIF    (0x008)        // IN Token Received Interrupt Flag
+#define USBEPnISR_IDTXIF    (0x010)        // IN Data Transmitted Interrupt Flag
+#define USBEPnISR_NAKIF     (0x020)        // NAK Transmitted Interrupt Flag
+#define USBEPnISR_STLIF     (0x040)        // STALL Transmitted Interrupt Flag
+#define USBEPnISR_UERIF     (0x080)        // USB Error Interrupt Flag
+#define USBEPnISR_STRXIF    (0x100)        // SETUP Token Received Interrupt Flag
+#define USBEPnISR_SDRXIF    (0x200)        // SETUP Data Received Interrupt Flag
+#define USBEPnISR_SDERIF    (0x400)        // SETUP Data Error Interrupt Flag
+#define USBEPnISR_ZLRXIF    (0x800)        // Zero Length Data Received Interrupt Flag
+
+// USBEPnTCR
+#define USBEPnTCR_TCNT      (0x1FF)        // Transfer Byte Count
+
+// USBEPnCFGR
+#define USBEPnCFGR_EPEN     (1U << 31)     // Endpoint Enable
+#define USBEPnCFGR_EPTYPE   (1U << 29)     // Transfer Type
+#define USBEPnCFGR_EPDIR    (1U << 28)     // Transfer Direction
+#define USBEPnCFGR_EPADR    (0xFU << 24)   // Endpoint Address
+#define USBEPnCFGR_EPLEN    (0x7FU << 10)  // Buffer Length
+#define USBEPnCFGR_EPBUFA   (0x3FF)        // Endpoint Buffer Address
+
+// Peripheral Direct Memory Access
+// /////////////////////////////////////////////////////////////////////////////
+
+// Extend Bus Interface
+// /////////////////////////////////////////////////////////////////////////////
+
+// Inter-IC Sound
+// /////////////////////////////////////////////////////////////////////////////
+
+// CRC
+// /////////////////////////////////////////////////////////////////////////////
+
+#endif // HT32F165x_REG_H
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h
new file mode 100644
index 000000000..ba4871636
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2.h
@@ -0,0 +1,199 @@
+/*
+ * Copyright (C) 2020 Codetector <[email protected]>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+#pragma once
+
+#if defined(HT32F52342) || defined(HT32F52352)
+    #define HT32F523x2
+#else
+    #error "Unknown HT32 device"
+#endif
+
+#if defined(HT32F523x2)
+    #define HT32
+#endif
+
+/*
+ * ==============================================================
+ * ---------- Interrupt Number Definition -----------------------
+ * ==============================================================
+ */
+typedef enum IRQn
+{
+/******  Cortex-M3 Processor Exceptions Numbers ****************/
+    InitialSP_IRQn                = -16,
+    InitialPC_IRQn                = -15,
+    NonMaskableInt_IRQn           = -14,
+    HardFault_IRQn                = -13,
+    SVCall_IRQn                   = -5,
+    PendSV_IRQn                   = -2,
+    SysTick_IRQn                  = -1,
+
+/******  HT32F165x Specific Interrupt Numbers ***********************/
+    LVD_IRQn                      = 0,
+    RTC_IRQn                      = 1,
+    FMC_IRQn                      = 2,
+    WKUP_IRQn                     = 3,
+    EXTI0_1_IRQn                  = 4,
+    EXTI2_3_IRQn                  = 5,
+    EXTI4_15_IRQn                 = 6,
+    CMP_IRQn                      = 7,
+    ADC_IRQn                      = 8,
+
+    MCTM_IRQn                     = 10,
+    GPTM1_IRQn                    = 11,
+    GPTM0_IRQn                    = 12,
+    SCTM0_IRQn                    = 13,
+    SCTM1_IRQn                    = 14,
+
+    BFTM0_IRQn                    = 17,
+    BFTM1_IRQn                    = 18,
+    I2C0_IRQn                     = 19,
+    I2C1_IRQn                     = 20,
+    SPI0_IRQn                     = 21,
+    SPI1_IRQn                     = 22,
+    USART0_IRQn                   = 23,
+    USART1_IRQn                   = 24,
+    UART0_IRQn                    = 25,
+    UART1_IRQn                    = 26,
+    SCI_IRQn                      = 27,
+    I2S_IRQn                      = 28,
+    USB_IRQn                      = 29,
+    PDMA_CH0_1_IRQn               = 30,
+    PDMA_CH2_5_IRQn               = 31
+} IRQn_Type;
+
+/*
+ * ==========================================================================
+ * ----------- Processor and Core Peripheral Section ------------------------
+ * ==========================================================================
+ */
+
+/**
+ * @brief HT32F165x Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+#define __FPU_PRESENT           0
+#define __MPU_PRESENT           0
+#define __NVIC_PRIO_BITS        8
+#define __Vendor_SysTickConfig  0
+
+#include "core_cm0plus.h"           /* Cortex-M0+ processor and core peripherals */
+
+/****************************************************************/
+/*                  Peripheral memory map                       */
+/****************************************************************/
+#define USART0_BASE             ((uint32_t)0x40000000)
+#define UART0_BASE              ((uint32_t)0x40001000)
+#define SPI0_BASE               ((uint32_t)0x40004000)
+#define ADC_BASE                ((uint32_t)0x40010000)
+
+#define AFIO_BASE               ((uint32_t)0x40022000)
+#define EXTI_BASE               ((uint32_t)0x40024000)
+#define I2S_BASE                ((uint32_t)0x40026000)
+#define MCTM0_BASE              ((uint32_t)0x4002C000)
+#define MCTM1_BASE              ((uint32_t)0x4002D000)
+
+#define USART1_BASE             ((uint32_t)0x40040000)
+#define UART1_BASE              ((uint32_t)0x40041000)
+#define SCI_BASE                ((uint32_t)0x40043000)
+#define SPI1_BASE               ((uint32_t)0x40044000)
+#define I2C0_BASE               ((uint32_t)0x40048000)
+#define I2C1_BASE               ((uint32_t)0x40049000)
+
+#define CMP0_BASE               ((uint32_t)0x40058000)
+#define CMP1_BASE               ((uint32_t)0x40058100)
+
+#define WDT_BASE                ((uint32_t)0x40068000)
+#define RTC_BASE                ((uint32_t)0x4006A000)
+#define PWRCU_BASE              ((uint32_t)0x4006A000)
+#define GPTM0_BASE              ((uint32_t)0x4006E000)
+#define GPTM1_BASE              ((uint32_t)0x4006F000)
+#define BFTM0_BASE              ((uint32_t)0x40076000)
+#define BFTM1_BASE              ((uint32_t)0x40077000)
+
+#define FMC_BASE                ((uint32_t)0x40080000)
+#define CKCU_BASE               ((uint32_t)0x40088000)
+#define RSTCU_BASE              ((uint32_t)0x40088000)
+#define CRC_BASE                ((uint32_t)0x4008A000)
+#define PDMA_BASE               ((uint32_t)0x40090000)
+#define EBI_BASE                ((uint32_t)0x40098000)
+#define USB_BASE                ((uint32_t)0x400A8000)
+#define USB_SRAM_BASE           ((uint32_t)0x400AA000)
+#define GPIO_A_BASE             ((uint32_t)0x400B0000)
+#define GPIO_B_BASE             ((uint32_t)0x400B2000)
+#define GPIO_C_BASE             ((uint32_t)0x400B4000)
+#define GPIO_D_BASE             ((uint32_t)0x400B6000)
+
+
+// Registers Headers
+#include "ht32f523x2_reg.h"
+
+/****************************************************************/
+/*                 Peripheral declaration                       */
+/****************************************************************/
+#define USART0                  ((USART_TypeDef *)  USART0_BASE)
+#define UART0                   ((USART_TypeDef *)  UART0_BASE)
+#define SPI0                    ((SPI_TypeDef *)    SPI0_BASE)
+#define ADC                     ((ADC_TypeDef *)    ADC_BASE)
+
+#define AFIO                    ((AFIO_TypeDef *)   AFIO_BASE)
+#define EXTI                    ((EXTI_TypeDef *)   EXTI_BASE)
+#define I2S                     ((I2S_TypeDef *)    I2S_BASE)
+#define MCTM0                   ((TM_TypeDef *)     MCTM0_BASE)
+#define MCTM1                   ((TM_TypeDef *)     MCTM1_BASE)
+
+#define USART1                  ((USART_TypeDef *)  USART1_BASE)
+#define UART1                   ((USART_TypeDef *)  UART1_BASE)
+#define SCI                     ((SCI_TypeDef *)    SCI_BASE)
+#define SPI1                    ((SPI_TypeDef *)    SPI1_BASE)
+#define I2C0                    ((I2C_TypeDef *)    I2C0_BASE)
+#define I2C1                    ((I2C_TypeDef *)    I2C1_BASE)
+
+#define CMP0                    ((CMP_TypeDef *)    CMP0_BASE)
+#define CMP1                    ((CMP_TypeDef *)    CMP1_BASE)
+
+#define WDT                     ((WDT_TypeDef *)    WDT_BASE)
+#define RTC                     ((RTC_TypeDef *)    RTC_BASE)
+#define PWRCU                   ((PWRCU_TypeDef *)  PWRCU_BASE)
+#define GPTM0                   ((TM_TypeDef *)     GPTM0_BASE)
+#define GPTM1                   ((TM_TypeDef *)     GPTM1_BASE)
+#define BFTM0                   ((BFTM_TypeDef *)   BFTM0_BASE)
+#define BFTM1                   ((BFTM_TypeDef *)   BFTM1_BASE)
+
+#define FMC                     ((FMC_TypeDef *)    FMC_BASE)
+#define CKCU                    ((CKCU_TypeDef *)   CKCU_BASE)
+#define RSTCU                   ((RSTCU_TypeDef *)  RSTCU_BASE)
+#define CRC                     ((CRC_TypeDef *)    CRC_BASE)
+#define PDMA                    ((PDMA_TypeDef *)   PDMA_BASE)
+#define EBI                     ((EBI_TypeDef *)    EBI_BASE)
+#define USB                     ((USB_TypeDef *)    USB_BASE)
+
+#define GPIOA                   ((GPIO_TypeDef *)   GPIO_A_BASE)
+#define GPIO_A GPIOA
+#define GPIOB                   ((GPIO_TypeDef *)   GPIO_B_BASE)
+#define GPIO_B GPIOB
+#define GPIOC                   ((GPIO_TypeDef *)   GPIO_C_BASE)
+#define GPIO_C GPIOC
+#define GPIOD                   ((GPIO_TypeDef *)   GPIO_D_BASE)
+#define GPIO_D GPIOD
+
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h
new file mode 100644
index 000000000..d8aad785d
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/HT32/HT32F523xx/ht32f523x2_reg.h
@@ -0,0 +1,657 @@
+#pragma once
+
+#ifndef __IO
+    #define __IO volatile
+#endif
+
+// Constants
+// /////////////////////////////////////////////////////////////////////////////
+#define AFIO_DEFAULT    0
+#define AFIO_GPIO       1
+#define AFIO_ADC        2
+#define AFIO_CMP        3
+#define AFIO_TM         4
+#define AFIO_SPI        5
+#define AFIO_USART      6
+#define AFIO_I2C        7
+#define AFIO_SMC        8
+#define AFIO_EBI        9
+#define AFIO_I2S        10
+#define AFIO_OTHER      15
+
+// Flash Memory Controller
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t TADR;           //!< 0x000          Flash Target Address Register
+  __IO uint32_t WRDR;           //!< 0x004          Flash Write Data Register
+       uint32_t RESERVED0[1];   //!< 0x008          Reserved
+  __IO uint32_t OCMR;           //!< 0x00C          Flash Operation Command Register
+  __IO uint32_t OPCR;           //!< 0x010          Flash Operation Control Register
+  __IO uint32_t OIER;           //!< 0x014          Flash Operation Interrupt Enable Register
+  __IO uint32_t OISR;           //!< 0x018          Flash Operation Interrupt and Status Register
+       uint32_t RESERVED1[1];   //!< 0x01C          Reserved
+  __IO uint32_t PPSR[4];        //!< 0x020 ~ 0x02C  Flash Page Erase/Program Protection Status Register
+  __IO uint32_t CPSR;           //!< 0x030          Flash Security Protection Status Register
+       uint32_t RESERVED2[51];  //!< 0x034 ~ 0x0FC  Reserved
+  __IO uint32_t VMCR;           //!< 0x100          Flash Vector Mapping Control Register
+       uint32_t RESERVED3[31];  //!< 0x104 ~ 0x17C  Reserved
+  __IO uint32_t MDID;           //!< 0x180          Manufacturer and Device ID Register
+  __IO uint32_t PNSR;           //!< 0x184          Flash Page Number Status Register
+  __IO uint32_t PSSR;           //!< 0x188          Flash Page Size Status Register
+#if defined(HT32F165x)
+       uint32_t RESERVED4[29];  //!< 0x18C ~ 0x1FC  Reserved
+#else
+  __IO uint32_t DID;            //!< 0x18C          Device ID Register
+       uint32_t RESERVED4[28];  //!< 0x190 ~ 0x1FC  Reserved
+#endif
+  __IO uint32_t CFCR;           //!< 0x200          Flash Cache and Pre-fetch Control Register
+       uint32_t RESERVED5[63];  //!< 0x204 ~ 0x2FC  Reserved
+  __IO uint32_t SBVT[4];        //!< 0x300 ~ 0x30C  SRAM Booting Vector (4x32Bit)
+#if defined(HT32F165x)
+#else
+  __IO uint32_t CID[4];         //!< 0x310 ~ 0x31C  Custom ID Register
+#endif
+} FMC_TypeDef;
+
+#define FMC_OCMR_CMD_MASK           (0xF << 0)
+#define FMC_OCMR_CMD_IDLE           (0x0 << 0)
+#define FMC_OCMR_CMD_WORD_PROGRAM   (0x4 << 0)
+#define FMC_OCMR_CMD_PAGE_ERASE     (0x8 << 0)
+#define FMC_OCMR_CMD_MASS_ERASE     (0xA << 0)
+#define FMC_OPCR_OPM_MASK           (0xF << 1)
+#define FMC_OPCR_OPM_IDLE           (0x6 << 1)
+#define FMC_OPCR_OPM_COMMIT         (0xA << 1)
+#define FMC_OPCR_OPM_FINISHED       (0xE << 1)
+#define FMC_CFCR_CE                 (1U << 12)
+#define FMC_CFCR_WAIT_MASK          (7U << 0)
+#define FMC_CFCR_WAIT_0             (1U)
+#define FMC_CFCR_WAIT_1             (2U)
+
+// Power Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+       uint32_t RESERVE0[64];
+  __IO uint32_t BAKSR;          //!< 0x000          Status Register
+  __IO uint32_t BAKCR;          //!< 0x004          Control Register
+  __IO uint32_t BAKTEST;        //!< 0x008          Test Register
+  __IO uint32_t HSIRCR;         //!< 0x00C          HSI Ready Counter Control Register
+  __IO uint32_t LVDCSR;         //!< 0x010          Low Voltage/Brown Out Detect Control and Status Register
+       uint32_t RESERVE1[59];   //!< 0x014 ~ 0x0FC  Reserved
+  __IO uint32_t BAKREG[10];     //!< 0x100 ~ 0x124  Backup Register 0 ~ 9
+} PWRCU_TypeDef;
+
+// Clock Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t GCFGR;          //!< 0x000          Global Clock Configuration Register
+  __IO uint32_t GCCR;           //!< 0x004          Global Clock Control Register
+  __IO uint32_t GCSR;           //!< 0x008          Global Clock Status Register
+  __IO uint32_t GCIR;           //!< 0x00C          Global Clock Interrupt Register
+       uint32_t RESERVED0[2];   //!< 0x010 ~ 0x014  Reserved
+  __IO uint32_t PLLCFGR;        //!< 0x018          PLL Configuration Register
+  __IO uint32_t PLLCR;          //!< 0x01C          PLL Control Register
+  __IO uint32_t AHBCFGR;        //!< 0x020          AHB Configuration Register
+  __IO uint32_t AHBCCR;         //!< 0x024          AHB Clock Control Register
+  __IO uint32_t APBCFGR;        //!< 0x028          APB Configuration Register
+  __IO uint32_t APBCCR0;        //!< 0x02C          APB Clock Control Register 0
+  __IO uint32_t APBCCR1;        //!< 0x030          APB Clock Control Register 1
+  __IO uint32_t CKST;           //!< 0x034          Clock source status Register
+
+  __IO uint32_t APBPCSR0;       //!< 0x038          APB Peripheral Clock Selection Register 0
+  __IO uint32_t APBPCSR1;       //!< 0x03C          APB Peripheral Clock Selection Register 1
+  __IO uint32_t HSICR;          //!< 0x040          HSI Control Register
+  __IO uint32_t HSIATCR;        //!< 0x044          HSI Auto Trimming Counter Register
+
+       uint32_t RESERVED2[174]; //!< 0x048 ~ 0x2FC  Reserved
+  __IO uint32_t LPCR;           //!< 0x300          Low Power Control Register
+  __IO uint32_t MCUDBGCR;       //!< 0x304          MCU Debug Control Register
+} CKCU_TypeDef;
+
+#define CKCU_GCFGR_LPMOD_MASK       (7U << 29)
+#define CKCU_GCFGR_USBPRE_MASK      (3U << 22)
+#define CKCU_GCFGR_PLLSRC           (1U << 8)
+#define CKCU_GCFGR_CKOUTSRC_MASK    (7U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_REF  (0U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_AHB  (1U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_SYS  (2U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_HSE  (3U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_HSI  (4U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_LSE  (5U << 0)
+#define CKCU_GCFGR_CKOUTSRC_CK_LSI  (6U << 0)
+#define CKCU_GCCR_PSRCEN            (1U << 17)
+#define CKCU_GCCR_CKMEN             (1U << 16)
+#define CKCU_GCCR_HSIEN             (1U << 11)
+#define CKCU_GCCR_HSEEN             (1U << 10)
+#define CKCU_GCCR_PLLEN             (1U << 9)
+#define CKCU_GCCR_SW_MASK           (3U << 0)
+#define CKCU_GCCR_SW_PLL            (1U << 0)
+#define CKCU_GCCR_SW_HSE            (2U << 0)
+#define CKCU_GCCR_SW_HSI            (3U << 0)
+#define CKCU_GCSR_LSIRDY            (1U << 5)
+#define CKCU_GCSR_LSERDY            (1U << 4)
+#define CKCU_GCSR_HSIRDY            (1U << 3)
+#define CKCU_GCSR_HSERDY            (1U << 2)
+#define CKCU_GCSR_PLLRDY            (1U << 1)
+#define CKCU_PLLCFGR_PFBD_MASK      (0x3fU << 23)
+#define CKCU_PLLCFGR_POTD_MASK      (3U << 21)
+#define CKCU_PLLCR_PLLBPS           (1U << 31)
+#define CKCU_AHBCFGR_AHBPRE_MASK    (3U << 0)
+#define CKCU_AHBCCR_PAEN            (1U << 16)
+#define CKCU_AHBCCR_CRCEN           (1U << 13)
+#define CKCU_AHBCCR_EBIEN           (1U << 12)
+#define CKCU_AHBCCR_CKREFEN         (1U << 11)
+#define CKCU_AHBCCR_USBEN           (1U << 10)
+#define CKCU_APBCFGR_ADCDIV_MASK    (7U << 16)
+#define CKCU_APBCCR0_I2SEN          (1U << 25)
+#define CKCU_APBCCR0_SCIEN          (1U << 24)
+#define CKCU_APBCCR0_EXTIEN         (1U << 15)
+#define CKCU_APBCCR0_AFIOEN         (1U << 14)
+#define CKCU_APBCCR0_UR1EN          (1U << 11)
+#define CKCU_APBCCR0_UR0EN          (1U << 10)
+#define CKCU_APBCCR0_USR1EN         (1U << 9)
+#define CKCU_APBCCR0_USR0EN         (1U << 8)
+#define CKCU_APBCCR0_SPI1EN         (1U << 5)
+#define CKCU_APBCCR0_SPI0EN         (1U << 4)
+#define CKCU_APBCCR0_I2C1EN         (1U << 1)
+#define CKCU_APBCCR0_I2C0EN         (1U << 0)
+#define CKCU_APBCCR1_ADCEN          (1U << 24)
+#define CKCU_APBCCR1_OPA1EN         (1U << 23)
+#define CKCU_APBCCR1_OPA0EN         (1U << 22)
+#define CKCU_APBCCR1_BFTM1EN        (1U << 17)
+#define CKCU_APBCCR1_BFTM0EN        (1U << 16)
+#define CKCU_APBCCR1_GPTM1EN        (1U << 9)
+#define CKCU_APBCCR1_GPTM0EN        (1U << 8)
+#define CKCU_APBCCR1_BKPREN         (1U << 6)
+#define CKCU_APBCCR1_WDTREN         (1U << 4)
+#define CKCU_APBCCR1_MCTM1EN        (1U << 1)
+#define CKCU_APBCCR1_MCTM0EN        (1U << 0)
+#define CKCU_CKST_CKSWST_MASK       (3U << 30)
+#define CKCU_CKST_HSIST_MASK        (7U << 24)
+#define CKCU_CKST_HSEST_MASK        (3U << 16)
+#define CKCU_CKST_PLLST_MASK        (0xfU << 8)
+#define CKCU_LPCR_USBSLEEP          (1U << 8)
+#define CKCU_LPCR_BKISO             (1U << 0)
+
+// Reset Control Unit
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t GRSR;           //!< 0x000          Global Reset Status Register
+  __IO uint32_t AHBPRSTR;       //!< 0x004          AHB Peripheral Reset Register
+  __IO uint32_t APBPRSTR0;      //!< 0x008          APB Peripheral Reset Register 0
+  __IO uint32_t APBPRSTR1;      //!< 0x00C          APB Peripheral Reset Register 1
+} RSTCU_TypeDef;
+
+#define RSTCU_GRSR_PORSTF           (1U << 3)
+#define RSTCU_GRSR_WDTRSTF          (1U << 2)
+#define RSTCU_GRSR_EXTRSTF          (1U << 1)
+#define RSTCU_GRSR_SYSRSTF          (1U << 0)
+#define RSTCU_AHBPRSTR_PxRST(n)     ((1U << 8) << (n))
+#define RSTCU_AHBPRSTR_CRCRST       (1U << 7)
+#define RSTCU_AHBPRSTR_EBIRST       (1U << 6)
+#define RSTCU_AHBPRSTR_USBRST       (1U << 5)
+#define RSTCU_AHBPRSTR_DMARST       (1U << 0)
+#define RSTCU_APBPRSTR0_I2SRST      (1U << 25)
+#define RSTCU_APBPRSTR0_SCIRST      (1U << 24)
+#define RSTCU_APBPRSTR0_EXTIRST     (1U << 15)
+#define RSTCU_APBPRSTR0_AFIORST     (1U << 14)
+#define RSTCU_APBPRSTR0_UR1RST      (1U << 11)
+#define RSTCU_APBPRSTR0_UR0RST      (1U << 10)
+#define RSTCU_APBPRSTR0_USR1RST     (1U << 9)
+#define RSTCU_APBPRSTR0_USR0RST     (1U << 8)
+#define RSTCU_APBPRSTR0_SPI1RST     (1U << 5)
+#define RSTCU_APBPRSTR0_SPI0RST     (1U << 4)
+#define RSTCU_APBPRSTR0_I2C1RST     (1U << 1)
+#define RSTCU_APBPRSTR0_I2C0RST     (1U << 0)
+#define RSTCU_APBPRSTR1_ADCRST      (1U << 24)
+#define RSTCU_APBPRSTR1_OPA1RST     (1U << 23)
+#define RSTCU_APBPRSTR1_OPA0RST     (1U << 22)
+#define RSTCU_APBPRSTR1_BFTM1RST    (1U << 17)
+#define RSTCU_APBPRSTR1_BFTM0RST    (1U << 16)
+#define RSTCU_APBPRSTR1_GPTM1RST    (1U << 9)
+#define RSTCU_APBPRSTR1_GPTM0RST    (1U << 8)
+#define RSTCU_APBPRSTR1_WDTRST      (1U << 4)
+#define RSTCU_APBPRSTR1_MCTM1RST    (1U << 1)
+#define RSTCU_APBPRSTR1_MCTM0RST    (1U << 0)
+
+// General Purpose I/O
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t DIRCR;          //!< 0x000          Data Direction Control Register
+  __IO uint32_t INER;           //!< 0x004          Input function enable register
+  __IO uint32_t PUR;            //!< 0x008          Pull-Up Selection Register
+  __IO uint32_t PDR;            //!< 0x00C          Pull-Down Selection Register
+  __IO uint32_t ODR;            //!< 0x010          Open Drain Selection Register
+  __IO uint32_t DRVR;           //!< 0x014          Drive Current Selection Register
+  __IO uint32_t LOCKR;          //!< 0x018          Lock Register
+  __IO uint32_t DINR;           //!< 0x01c          Data Input Register
+  __IO uint32_t DOUTR;          //!< 0x020          Data Output Register
+  __IO uint32_t SRR;            //!< 0x024          Output Set and Reset Control Register
+  __IO uint32_t RR;             //!< 0x028          Output Reset Control Register
+} GPIO_TypeDef;
+
+// Alternate Function Input/Output
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t ESSR[2];        //!< 0x000 ~ 0x004  EXTI Source Selection Register 0 ~ 1
+       uint32_t RESERVE0[6];    //!< 0x008 ~ 0x01C  Reserved
+  union {
+    struct {
+  __IO uint32_t GPACFGR[2];     //!< 0x020 ~ 0x024  GPIO Port A Configuration Register 0 ~ 1
+  __IO uint32_t GPBCFGR[2];     //!< 0x028 ~ 0x02C  GPIO Port B Configuration Register 0 ~ 1
+  __IO uint32_t GPCCFGR[2];     //!< 0x030 ~ 0x034  GPIO Port C Configuration Register 0 ~ 1
+  __IO uint32_t GPDCFGR[2];     //!< 0x038 ~ 0x03C  GPIO Port D Configuration Register 0 ~ 1
+    };
+    // alternate mapping
+    struct {
+  __IO uint32_t GPxCFGR[0][2];  //!< 0x020 ~ 0x03C  GPIO Port x Configuration Register 0 ~ 1
+    };
+  };
+} AFIO_TypeDef;
+
+// Nested Vectored Interrupt Controller
+// /////////////////////////////////////////////////////////////////////////////
+// Implemented in Cortex-M3 Headers
+
+// External Interrupt/Event Controller
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CFGR0;          //!< 0x000         EXTI Interrupt 0 Configuration Register
+  __IO uint32_t CFGR1;          //!< 0x004         EXTI Interrupt 1 Configuration Register
+  __IO uint32_t CFGR2;          //!< 0x008         EXTI Interrupt 2 Configuration Register
+  __IO uint32_t CFGR3;          //!< 0x00C         EXTI Interrupt 3 Configuration Register
+  __IO uint32_t CFGR4;          //!< 0x010         EXTI Interrupt 4 Configuration Register
+  __IO uint32_t CFGR5;          //!< 0x014         EXTI Interrupt 5 Configuration Register
+  __IO uint32_t CFGR6;          //!< 0x018         EXTI Interrupt 6 Configuration Register
+  __IO uint32_t CFGR7;          //!< 0x01C         EXTI Interrupt 7 Configuration Register
+  __IO uint32_t CFGR8;          //!< 0x020         EXTI Interrupt 8 Configuration Register
+  __IO uint32_t CFGR9;          //!< 0x024         EXTI Interrupt 9 Configuration Register
+  __IO uint32_t CFGR10;         //!< 0x028         EXTI Interrupt 10 Configuration Register
+  __IO uint32_t CFGR11;         //!< 0x02C         EXTI Interrupt 11 Configuration Register
+  __IO uint32_t CFGR12;         //!< 0x030         EXTI Interrupt 12 Configuration Register
+  __IO uint32_t CFGR13;         //!< 0x034         EXTI Interrupt 13 Configuration Register
+  __IO uint32_t CFGR14;         //!< 0x038         EXTI Interrupt 14 Configuration Register
+  __IO uint32_t CFGR15;         //!< 0x03C         EXTI Interrupt 15 Configuration Register
+  __IO uint32_t CR;             //!< 0x040         EXTI Interrupt Control Register
+  __IO uint32_t EDGEFLGR;       //!< 0x044         EXTI Interrupt Edge Flag Register
+  __IO uint32_t EDGESR;         //!< 0x048         EXTI Interrupt Edge Status Register
+  __IO uint32_t SSCR;           //!< 0x04C         EXTI Interrupt Software Set Command Register
+  __IO uint32_t WAKUPCR;        //!< 0x050         EXTI Interrupt Wakeup Control Register
+  __IO uint32_t WAKUPPOLR;      //!< 0x054         EXTI Interrupt Wakeup Polarity Register
+  __IO uint32_t WAKUPFLG;       //!< 0x058         EXTI Interrupt Wakeup Flag Register
+} EXTI_TypeDef;
+
+// Analog To Digital Converter
+// /////////////////////////////////////////////////////////////////////////////
+
+// Operational Amplifier / Comparator
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Comparator Control Register
+  __IO uint32_t VALR;           //!< 0x004          Comparator Voltage Reference Register
+  __IO uint32_t IER;            //!< 0x008          Comparator Interrupt Enable Register
+  __IO uint32_t TFR;            //!< 0x00C          Comparator Transition Flag Register
+} CMP_TypeDef;
+
+
+// Basic Function Timers
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Control Register
+  __IO uint32_t SR;             //!< 0x004          Status Register
+  __IO uint32_t CNTR;           //!< 0x008          Counter Value Register
+  __IO uint32_t CMP;            //!< 0x00C          Compare Value Register
+} BFTM_TypeDef;
+
+#define BFTM_CR_CEN                 (1U << 2)
+#define BFTM_CR_OSM                 (1U << 1)
+#define BFTM_CR_MIEN                (1U << 0)
+#define BFTM_SR_MIF                 (1U << 0)
+
+// General Purpose Timers
+// Motor Control Timers
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CNTCFR;         //!< 0x000          Timer Counter Configuaration Register
+  __IO uint32_t MDCFR;          //!< 0x004          Timer Mode Configuration Register
+  __IO uint32_t TRCFR;          //!< 0x008          Timer Trigger Configuration Register
+       uint32_t RESERVED0[1];   //!< 0x00C          Reserved
+  __IO uint32_t CTR;            //!< 0x010          Timer Counter Register
+       uint32_t RESERVED1[3];   //!< 0x014 ~ 0x01C  Reserved
+  __IO uint32_t CHnICFR[4];     //!< 0x020 ~ 0x02C  Channel n Input Configuration Register
+       uint32_t RESERVED2[4];   //!< 0x030 ~ 0x03C  Reserved
+  __IO uint32_t CHnOCFR[4];     //!< 0x040 ~ 0x04C  Channel n Output Configuration Register
+  __IO uint32_t CHCTR;          //!< 0x050          Channel Control Register
+  __IO uint32_t CHPOLR;         //!< 0x054          Channel Polarity Control Register
+       uint32_t RESERVED3[5];   //!< 0x058 ~ 0x068  Reserved
+  // note: only available as MCTM
+  __IO uint32_t CHBRKCFR;       //!< 0x06C          Channel Break Configuration Register
+  __IO uint32_t CHBRKCTR;       //!< 0x070          Channel Break Control Register
+  // end note
+  __IO uint32_t DICTR;          //!< 0x074          Timer PDMA/Interrupt Control Register
+  __IO uint32_t EVGR;           //!< 0x078          Timer Event Generator Register
+  __IO uint32_t INTSR;          //!< 0x07C          Timer Interrupt Status Register
+  __IO uint32_t CNTR;           //!< 0x080          Timer Counter Register
+  __IO uint32_t PSCR;           //!< 0x084          Timer Prescaler Register
+  __IO uint32_t CRR;            //!< 0x088          Timer Counter Reload Register
+  // note: only available as MCTM
+  __IO uint32_t REPR;           //!< 0x08C          Timer Repetition Register
+  // end note
+  __IO uint32_t CHnCCR[4];      //!< 0x090 ~ 0x09C  Channel n Capture/Compare Register
+  __IO uint32_t CHnACR[4];      //!< 0x0A0 ~ 0x0AC  Channel n Asymmentric Compare Register
+} TM_TypeDef;
+
+#define TM_CNTCFR_CMSEL_MASK        (3U << 16)
+#define TM_CNTCFR_CMSEL_MODE_3      (3U << 16)
+#define TM_CNTCFR_CMSEL_MODE_2      (2U << 16)
+#define TM_CNTCFR_CMSEL_MODE_1      (1U << 16)
+#define TM_CNTCFR_CMSEL_MODE_0      (0U << 16)
+#define TM_CTR_CHCCDS               (1U << 16)
+#define TM_CTR_COMUS                (1U << 9)
+#define TM_CTR_COMPRE               (1U << 8)
+#define TM_CTR_CRBE                 (1U << 1)
+#define TM_CTR_TME                  (1U << 0)
+#define TM_CHnOCFR_CHnPRE           (1U << 4)
+#define TM_CHnOCFR_REFnCE           (1U << 3)
+#define TM_CHnOCFR_CHnOM(n)         ((((n)>>0)&7)|((((n)>>3)&1)<<8))
+#define TM_CHBRKCTR_CHMOE           (1U << 4)
+
+// Real Time Clock
+// /////////////////////////////////////////////////////////////////////////////
+
+// Watchdog Timer
+// /////////////////////////////////////////////////////////////////////////////
+
+// I2C
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR;             //!< 0x000          Control Register
+  __IO uint32_t IER;            //!< 0x004          Interrupt Enable Register
+  __IO uint32_t ADDR;           //!< 0x008          Address Register
+  __IO uint32_t SR;             //!< 0x00C          Status Register
+  __IO uint32_t SHPGR;          //!< 0x010          SCL High Period Generation Register
+  __IO uint32_t SLPGR;          //!< 0x014          SCL Low Period Generation Register
+  __IO uint32_t DR;             //!< 0x018          Data Register
+  __IO uint32_t TAR;            //!< 0x01C          Target Register
+  __IO uint32_t ADDMR;          //!< 0x020          Address Mask Register
+  __IO uint32_t ADDSR;          //!< 0x024          Address Snoop Register
+  __IO uint32_t TOUT;           //!< 0x028          Timeout Register
+} I2C_TypeDef;
+
+#define I2C_CR_SEQ_FILTER_MASK      (3U << 14)
+#define I2C_CR_SEQ_FILTER_2_PCLK    (2U << 14)
+#define I2C_CR_SEQ_FILTER_1_PCLK    (1U << 14)
+#define I2C_CR_SEQ_FILTER_DISABLE   (0U << 14)
+#define I2C_CR_COMB_FILTER_En       (1U << 13)
+#define I2C_CR_ENTOUT               (1U << 12)
+#define I2C_CR_DMANACK              (1U << 10)
+#define I2C_CR_RXDMAE               (1U << 9)
+#define I2C_CR_TXDMAE               (1U << 8)
+#define I2C_CR_ADRM                 (1U << 7)
+#define I2C_CR_I2CEN                (1U << 3)
+#define I2C_CR_GCEN                 (1U << 2)
+#define I2C_CR_STOP                 (1U << 1)
+#define I2C_CR_AA                   (1U << 0)
+#define I2C_IER_RXBFIE              (1U << 18)
+#define I2C_IER_TXDEIE              (1U << 17)
+#define I2C_IER_RXDNEIE             (1U << 16)
+#define I2C_IER_TOUTIE              (1U << 11)
+#define I2C_IER_BUSERRIE            (1U << 10)
+#define I2C_IER_RXNACKIE            (1U << 9)
+#define I2C_IER_ARBLOSIE            (1U << 8)
+#define I2C_IER_GCSIE               (1U << 3)
+#define I2C_IER_ADRSIE              (1U << 2)
+#define I2C_IER_STOIE               (1U << 1)
+#define I2C_IER_STAIE               (1U << 0)
+#define I2C_SR_TXNRX                (1U << 21)
+#define I2C_SR_MASTER               (1U << 20)
+#define I2C_SR_BUSBUSY              (1U << 19)
+#define I2C_SR_RXBF                 (1U << 18)
+#define I2C_SR_TXDE                 (1U << 17)
+#define I2C_SR_RXDNE                (1U << 16)
+#define I2C_SR_TOUTF                (1U << 11)
+#define I2C_SR_BUSERR               (1U << 10)
+#define I2C_SR_RXNACK               (1U << 9)
+#define I2C_SR_ARBLOS               (1U << 8)
+#define I2C_SR_GCS                  (1U << 3)
+#define I2C_SR_ADRS                 (1U << 2)
+#define I2C_SR_STO                  (1U << 1)
+#define I2C_SR_STA                  (1U << 0)
+#define I2C_TAR_RWD                 (1U << 10)
+
+// SPI
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CR0;            //!< 0x000          Control Register 0
+  __IO uint32_t CR1;            //!< 0x004          Control Register 1
+  __IO uint32_t IER;            //!< 0x008          Interrupt Enable Register
+  __IO uint32_t CPR;            //!< 0x00C          Clock Prescaler Register
+  __IO uint32_t DR;             //!< 0x010          Data Register
+  __IO uint32_t SR;             //!< 0x014          Status Register
+  __IO uint32_t FCR;            //!< 0x018          FIFO Control Register
+  __IO uint32_t FSR;            //!< 0x01C          FIFO Status Register
+  __IO uint32_t FTOCR;          //!< 0x020          FIFO Time Out Counter Register
+} SPI_TypeDef;
+
+#define SPI_CR0_GUADTEN             (1U << 7)
+#define SPI_CR0_DUALEN              (1U << 6)
+#define SPI_CR0_SSELC               (1U << 4)
+#define SPI_CR0_SELOEN              (1U << 3)
+#define SPI_CR0_SPIEN               (1U << 0)
+#define SPI_CR1_MODE                (1U << 14)
+#define SPI_CR1_SELM                (1U << 13)
+#define SPI_CR1_FIRSTBIT            (1U << 12)
+#define SPI_CR1_SELAP               (1U << 11)
+#define SPI_CR1_FORMAT_MASK         (7U << 8)
+#define SPI_CR1_FORMAT_MODE0        (0x1U << 8)
+#define SPI_CR1_FORMAT_MODE1        (0x2U << 8)
+#define SPI_CR1_FORMAT_MODE2        (0x6U << 8)
+#define SPI_CR1_FORMAT_MODE3        (0x5U << 8)
+#define SPI_IER_RXBNEIEN            (1U << 2)
+#define SPI_IER_TXBEIEN             (1U << 0)
+#define SPI_SR_RXBNE                (1U << 2)
+#define SPI_SR_TXE                  (1U << 1)
+#define SPI_SR_TXBE                 (1U << 0)
+#define SPI_FCR_FIFOEN              (1U << 10)
+#define SPI_FSR_TXFS_MASK           (0xfU << 0)
+#define SPI_FSR_RXFS_MASK           (0xfU << 4)
+
+// USART
+// UART
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t DR;             //!< 0x000          Data Register
+  __IO uint32_t CR;             //!< 0x004          Control Register
+  // Only USART
+  __IO uint32_t FCR;            //!< 0x008          FIFO Control Register
+  __IO uint32_t IER;            //!< 0x00C          Interrupt Enable Register
+  __IO uint32_t SIFR;           //!< 0x010          Status & Interrupt Flag Register
+
+  __IO uint32_t TPR;            //!< 0x014          Timing Parameter Register
+
+  __IO uint32_t IrDACR;         //!< 0x018          IrDA Control Register
+  __IO uint32_t RS485CR;        //!< 0x01C          RS485 Control Register
+  __IO uint32_t SYNCR;          //!< 0x020          Synchronous Control Register
+  // end note
+  __IO uint32_t DLR;            //!< 0x024          Divider Latch Register
+  __IO uint32_t TSTR;           //!< 0x028          Debug/Test Register
+} USART_TypeDef;
+
+// USART CR
+#define UART_CR_MODE_MASK                 (0b11 << 0)
+#define UART_CR_MODE_NORMAL               (0 << 0)
+#define UART_CR_TRSM                      (1 << 2)
+#define UART_CR_HFCEN                     (1 << 3)
+#define UART_CR_URTXEN                    (1 << 4)
+#define UART_CR_URRXEN                    (1 << 5)
+#define UART_CR_TXDMAEN                   (1 << 6)
+#define UART_CR_RXDMAEN                   (1 << 7)
+#define UART_CR_WLS_MASK                  (0b11 << 8)
+#define UART_CR_WLS_7B                    (0b00 << 8)
+#define UART_CR_WLS_8B                    (0b01 << 8)
+#define UART_CR_WLS_9B                    (0b10 << 8)
+#define UART_CR_NSB                       (1 << 10)
+#define UART_CR_PBE                       (1 << 11)
+#define UART_CR_EPE                       (1 << 12)
+#define UART_CR_SPE                       (1 << 13)
+#define UART_CR_BCB                       (1 << 14)
+#define UART_CR_RTS                       (1 << 15)
+// USART FCR (FIFO CR)
+#define USART_FCR_TXR               (1 << 0)
+#define USART_FCR_RXR               (1 << 1)
+#define USART_FCR_TXTL_MASK         (0b11 << 4)
+#define USART_FCR_RXTL_MASK         (0b11 << 6)
+#define USART_FCR_TXFS_MASK         (0xF << 16)
+#define USART_FCR_RXFS_MASK         (0xF << 24)
+// USART SIFR Status and Interrupt Flag Register
+#define USART_SIFR_RXDNE        (1 << 0)
+#define USART_SIFR_OEI          (1 << 1)
+#define USART_SIFR_PEI          (1 << 2)
+#define USART_SIFR_FEI          (1 << 3)
+#define USART_SIFR_BII          (1 << 4)
+#define USART_SIFR_RXDR         (1 << 5)
+#define USART_SIFR_RXTOF        (1 << 6)
+#define USART_SIFR_TXDE         (1 << 7)
+#define USART_SIFR_TXC          (1 << 8)
+#define USART_SIFR_RSADDE       (1 << 9)
+#define USART_SIFR_CTSC         (1 << 10)
+#define USART_SIFR_CTSS         (1 << 11)
+// USART IER
+#define USART_IER_RXDRIE            (1 << 0)
+#define USART_IER_TXDEIE            (1 << 1)
+#define USART_IER_TXCIE             (1 << 2)
+#define USART_IER_OEIE              (1 << 3)
+#define USART_IER_PEIE              (1 << 4)
+#define USART_IER_FEIE              (1 << 5)
+#define USART_IER_BIE               (1 << 6)
+#define USART_IER_RSADDIE           (1 << 7)
+#define USART_IER_RXTOIE            (1 << 8)
+#define USART_IER_CTSIE             (1 << 9)
+
+
+// Smart Card Interface
+// /////////////////////////////////////////////////////////////////////////////
+
+// USB
+// /////////////////////////////////////////////////////////////////////////////
+typedef struct {
+  __IO uint32_t CSR;            //!< 0x000          USB Control and Status Register
+  __IO uint32_t IER;            //!< 0x004          USB Interrupt Enable Register
+  __IO uint32_t ISR;            //!< 0x008          USB Interrupt Status Register
+  __IO uint32_t FCR;            //!< 0x00C          USB Frame Count Register
+  __IO uint32_t DEVAR;          //!< 0x010          USB Device Address Register
+  struct {
+    __IO uint32_t CSR;          //!< 0x014          USB Endpoint n Control and Status Register
+    __IO uint32_t IER;          //!< 0x018          USB Endpoint n Interrupt Enable Register
+    __IO uint32_t ISR;          //!< 0x01C          USB Endpoint n Interrupt Status Register
+    __IO uint32_t TCR;          //!< 0x020          USB Endpoint n Transfer Count Register
+    __IO uint32_t CFGR;         //!< 0x024          USB Endpoint n Configuration Register
+  } EP[8];
+} USB_TypeDef;
+
+// USBCSR
+#define USBCSR_FRES         (0x002)        // Force USB Reset Control
+#define USBCSR_PDWN         (0x004)        // Power Down Mode Control
+#define USBCSR_LPMODE       (0x008)        // Low-Power Mode Control
+#define USBCSR_GENRSM       (0x020)        // Resume Request Generation Control
+#define USBCSR_RXDP         (0x040)        // Received DP Line Status
+#define USBCSR_RXDM         (0x080)        // Received DM Line Status
+#define USBCSR_ADRSET       (0x100)        // Device Address Setting Control
+#define USBCSR_SRAMRSTC     (0x200)        // USB SRAM Reset Condition
+#define USBCSR_DPPUEN       (0x400)        // DP Pull Up Enable
+#define USBCSR_DPWKEN       (0x800)        // DP Wake Up Enable
+
+// USBIER
+#define USBIER_UGIE         (0x0001)       // USB global Interrupt Enable
+#define USBIER_SOFIE        (0x0002)       // Start Of Frame Interrupt Enable
+#define USBIER_URSTIE       (0x0004)       // USB Reset Interrupt Enable
+#define USBIER_RSMIE        (0x0008)       // Resume Interrupt Enable
+#define USBIER_SUSPIE       (0x0010)       // Suspend Interrupt Enable
+#define USBIER_ESOFIE       (0x0020)       // Expected Start Of Frame Enable
+#define USBIER_EP0IE        (0x0100)       // Endpoint 0 Interrupt Enable
+#define USBIER_EP1IE        (0x0200)       // Endpoint 1 Interrupt Enable
+#define USBIER_EP2IE        (0x0400)       // Endpoint 2 Interrupt Enable
+#define USBIER_EP3IE        (0x0800)       // Endpoint 3 Interrupt Enable
+#define USBIER_EP4IE        (0x1000)       // Endpoint 4 Interrupt Enable
+#define USBIER_EP5IE        (0x2000)       // Endpoint 5 Interrupt Enable
+#define USBIER_EP6IE        (0x4000)       // Endpoint 6 Interrupt Enable
+#define USBIER_EP7IE        (0x8000)       // Endpoint 7 Interrupt Enable
+
+// USBISR
+#define USBISR_SOFIF        (0x0002)       // Start Of Frame Interrupt Flag
+#define USBISR_URSTIF       (0x0004)       // USB Reset Interrupt Flag
+#define USBISR_RSMIF        (0x0008)       // Resume Interrupt Flag
+#define USBISR_SUSPIF       (0x0010)       // Suspend Interrupt Flag
+#define USBISR_ESOFIF       (0x0020)       // Expected Start Of Frame Interrupt
+#define USBISR_EP0IF        (1U << 8)      // Endpoint 0 Interrupt Flag
+#define USBISR_EP1IF        (1U << 9)      // Endpoint 1 Interrupt Flag
+#define USBISR_EP2IF        (1U << 10)     // Endpoint 2 Interrupt Flag
+#define USBISR_EP3IF        (1U << 11)     // Endpoint 3 Interrupt Flag
+#define USBISR_EP4IF        (1U << 12)     // Endpoint 4 Interrupt Flag
+#define USBISR_EP5IF        (1U << 13)     // Endpoint 5 Interrupt Flag
+#define USBISR_EP6IF        (1U << 14)     // Endpoint 6 Interrupt Flag
+#define USBISR_EP7IF        (1U << 15)     // Endpoint 7 Interrupt Flag
+#define USBISR_EPnIF        (0xFF00)       // Endpoint Interrupt Mask
+
+// USBFCR
+#define USBFCR_FRNUM        (0x7FF)        // Frame Number
+#define USBFCR_SOFLCK       (1U << 16)     // Start-of-Frame Lock Flag
+#define USBFCR_LSOF         (0x3U << 17)   // Lost Start-of-Frame Number
+
+// USBEPnCSR
+#define USBEPnCSR_DTGTX     (0x01)         // Data Toggle Status, for IN transfer
+#define USBEPnCSR_NAKTX     (0x02)         // NAK Status, for IN transfer
+#define USBEPnCSR_STLTX     (0x04)         // STALL Status, for IN transfer
+#define USBEPnCSR_DTGRX     (0x08)         // Data Toggle Status, for OUT transfer
+#define USBEPnCSR_NAKRX     (0x10)         // NAK Status, for OUT transfer
+#define USBEPnCSR_STLRX     (0x20)         // STALL Status, for OUT transfer
+
+// USBEPnIER
+#define USBEPnIER_OTRXIE    (0x001)        // OUT Token Received Interrupt Enable
+#define USBEPnIER_ODRXIE    (0x002)        // OUT Data Received Interrupt Enable
+#define USBEPnIER_ODOVIE    (0x004)        // OUT Data Buffer Overrun Interrupt Enable
+#define USBEPnIER_ITRXIE    (0x008)        // IN Token Received Interrupt Enable
+#define USBEPnIER_IDTXIE    (0x010)        // IN Data Transmitted Interrupt Enable
+#define USBEPnIER_NAKIE     (0x020)        // NAK Transmitted Interrupt Enable
+#define USBEPnIER_STLIE     (0x040)        // STALL Transmitted Interrupt Enable
+#define USBEPnIER_UERIE     (0x080)        // USB Error Interrupt Enable
+#define USBEPnIER_STRXIE    (0x100)        // SETUP Token Received Interrupt Enable
+#define USBEPnIER_SDRXIE    (0x200)        // SETUP Data Received Interrupt Enable
+#define USBEPnIER_SDERIE    (0x400)        // SETUP Data Error Interrupt Enable
+#define USBEPnIER_ZLRXIE    (0x800)        // Zero Length Data Received Interrupt Enable
+
+// USBEPnISR
+#define USBEPnISR_OTRXIF    (0x001)        // OUT Token Received Interrupt Flag
+#define USBEPnISR_ODRXIF    (0x002)        // OUT Data Received Interrupt Flag
+#define USBEPnISR_ODOVIF    (0x004)        // OUT Data Buffer Overrun Interrupt Flag
+#define USBEPnISR_ITRXIF    (0x008)        // IN Token Received Interrupt Flag
+#define USBEPnISR_IDTXIF    (0x010)        // IN Data Transmitted Interrupt Flag
+#define USBEPnISR_NAKIF     (0x020)        // NAK Transmitted Interrupt Flag
+#define USBEPnISR_STLIF     (0x040)        // STALL Transmitted Interrupt Flag
+#define USBEPnISR_UERIF     (0x080)        // USB Error Interrupt Flag
+#define USBEPnISR_STRXIF    (0x100)        // SETUP Token Received Interrupt Flag
+#define USBEPnISR_SDRXIF    (0x200)        // SETUP Data Received Interrupt Flag
+#define USBEPnISR_SDERIF    (0x400)        // SETUP Data Error Interrupt Flag
+#define USBEPnISR_ZLRXIF    (0x800)        // Zero Length Data Received Interrupt Flag
+
+// USBEPnTCR
+#define USBEPnTCR_TCNT      (0x1FF)        // Transfer Byte Count
+
+// USBEPnCFGR
+#define USBEPnCFGR_EPEN     (1U << 31)     // Endpoint Enable
+#define USBEPnCFGR_EPTYPE   (1U << 29)     // Transfer Type
+#define USBEPnCFGR_EPDIR    (1U << 28)     // Transfer Direction
+#define USBEPnCFGR_EPADR    (0xFU << 24)   // Endpoint Address
+#define USBEPnCFGR_EPLEN    (0x7FU << 10)  // Buffer Length
+#define USBEPnCFGR_EPBUFA   (0x3FF)        // Endpoint Buffer Address
+
+// Peripheral Direct Memory Access
+// /////////////////////////////////////////////////////////////////////////////
+
+// Extend Bus Interface
+// /////////////////////////////////////////////////////////////////////////////
+
+// Inter-IC Sound
+// /////////////////////////////////////////////////////////////////////////////
+
+// CRC
+// /////////////////////////////////////////////////////////////////////////////
diff --git a/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h b/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h
new file mode 100644
index 000000000..237089e0c
--- /dev/null
+++ b/lib/chibios-contrib/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -0,0 +1,21214 @@
+/*
+** ###################################################################
+**     Processors:          MK66FN2M0VLQ18
+**                          MK66FN2M0VMD18
+**                          MK66FX1M0VLQ18
+**                          MK66FX1M0VMD18
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
+**     Version:             rev. 3.0, 2015-03-25
+**     Build:               b171205
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK66F18
+**
+**     The Clear BSD License
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 [email protected]
+**
+**     Revisions:
+**     - rev. 1.0 (2013-09-02)
+**         Initial version.
+**     - rev. 2.0 (2014-02-17)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**         Update according to reference manual rev. 2
+**     - rev. 2.1 (2014-04-16)
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.2 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.3 (2014-11-20)
+**         Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
+**         Update of SystemInit() to use 16MHz external crystal.
+**     - rev. 2.4 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 3.0 (2015-03-25)
+**         Registers updated according to the reference manual revision 1, March 2015
+**     - Revised 2018-05-04 by Michael Walker <[email protected]> to support ChibiOS LLD HAL
+**         Register names and other names updated to match other Kinetis definitions for other MCUs
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK66F18.h
+ * @version 3.0
+ * @date 2015-03-25
+ * @brief CMSIS Peripheral Access Layer for MK66F18
+ *
+ * CMSIS Peripheral Access Layer for MK66F18
+ */
+
+#ifndef _MK66F18_H_
+#define _MK66F18_H_                              /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0300U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 116                /**< Number of interrupts in the Vector table */
+
+#define DMA0_IRQn   DMA0_DMA16_IRQn
+#define DMA1_IRQn   DMA1_DMA17_IRQn
+#define DMA2_IRQn   DMA2_DMA18_IRQn
+#define DMA3_IRQn   DMA3_DMA19_IRQn
+#define DMA4_IRQn   DMA4_DMA20_IRQn
+#define DMA5_IRQn   DMA5_DMA21_IRQn
+#define DMA6_IRQn   DMA6_DMA22_IRQn
+#define DMA7_IRQn   DMA7_DMA23_IRQn
+#define DMA8_IRQn   DMA8_DMA24_IRQn
+#define DMA9_IRQn   DMA9_DMA25_IRQn
+#define DMA10_IRQn  DMA10_DMA26_IRQn
+#define DMA11_IRQn  DMA11_DMA27_IRQn
+#define DMA12_IRQn  DMA12_DMA28_IRQn
+#define DMA13_IRQn  DMA13_DMA29_IRQn
+#define DMA14_IRQn  DMA14_DMA30_IRQn
+#define DMA15_IRQn  DMA15_DMA21_IRQn
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_DMA16_IRQn              = 0,                /**< DMA Channel 0, 16 Transfer Complete */
+  DMA1_DMA17_IRQn              = 1,                /**< DMA Channel 1, 17 Transfer Complete */
+  DMA2_DMA18_IRQn              = 2,                /**< DMA Channel 2, 18 Transfer Complete */
+  DMA3_DMA19_IRQn              = 3,                /**< DMA Channel 3, 19 Transfer Complete */
+  DMA4_DMA20_IRQn              = 4,                /**< DMA Channel 4, 20 Transfer Complete */
+  DMA5_DMA21_IRQn              = 5,                /**< DMA Channel 5, 21 Transfer Complete */
+  DMA6_DMA22_IRQn              = 6,                /**< DMA Channel 6, 22 Transfer Complete */
+  DMA7_DMA23_IRQn              = 7,                /**< DMA Channel 7, 23 Transfer Complete */
+  DMA8_DMA24_IRQn              = 8,                /**< DMA Channel 8, 24 Transfer Complete */
+  DMA9_DMA25_IRQn              = 9,                /**< DMA Channel 9, 25 Transfer Complete */
+  DMA10_DMA26_IRQn             = 10,               /**< DMA Channel 10, 26 Transfer Complete */
+  DMA11_DMA27_IRQn             = 11,               /**< DMA Channel 11, 27 Transfer Complete */
+  DMA12_DMA28_IRQn             = 12,               /**< DMA Channel 12, 28 Transfer Complete */
+  DMA13_DMA29_IRQn             = 13,               /**< DMA Channel 13, 29 Transfer Complete */
+  DMA14_DMA30_IRQn             = 14,               /**< DMA Channel 14, 30 Transfer Complete */
+  DMA15_DMA31_IRQn             = 15,               /**< DMA Channel 15, 31 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
+  UART0Status_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0Error_IRQn              = 32,               /**< UART0 Error interrupt */
+  UART1Status_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1Error_IRQn              = 34,               /**< UART1 Error interrupt */
+  UART2Status_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2Error_IRQn              = 36,               /**< UART2 Error interrupt */
+  UART3Status_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3Error_IRQn              = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PITChannel0_IRQn             = 48,               /**< PIT timer channel 0 interrupt */
+  PITChannel1_IRQn             = 49,               /**< PIT timer channel 1 interrupt */
+  PITChannel2_IRQn             = 50,               /**< PIT timer channel 2 interrupt */
+  PITChannel3_IRQn             = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB_OTG_IRQn                 = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PINA_IRQn                    = 59,               /**< Port A interrupt */
+  PINB_IRQn                    = 60,               /**< Port B interrupt */
+  PINC_IRQn                    = 61,               /**< Port C interrupt */
+  PIND_IRQn                    = 62,               /**< Port D interrupt */
+  PINE_IRQn                    = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4Status_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4Error_IRQn              = 67,               /**< UART4 Error interrupt */
+  Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
+  Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85,               /**< Ethernet MAC Error and miscelaneous Interrupt */
+  LPUART0_IRQn                 = 86,               /**< LPUART0 status/error interrupt */
+  TSI0_IRQn                    = 87,               /**< TSI0 interrupt */
+  TPM1_IRQn                    = 88,               /**< TPM1 fault, overflow and channels interrupt */
+  TPM2_IRQn                    = 89,               /**< TPM2 fault, overflow and channels interrupt */
+  USBHSDCD_IRQn                = 90,               /**< USBHSDCD, USBHS Phy Interrupt */
+  I2C3_IRQn                    = 91,               /**< I2C3 interrupt */
+  CMP3_IRQn                    = 92,               /**< CMP3 interrupt */
+  USBHS_IRQn                   = 93,               /**< USB high speed OTG interrupt */
+  CAN1_ORed_Message_buffer_IRQn = 94,              /**< CAN1 OR'd message buffers interrupt */
+  CAN1_Bus_Off_IRQn            = 95,               /**< CAN1 bus off interrupt */
+  CAN1_Error_IRQn              = 96,               /**< CAN1 error interrupt */
+  CAN1_Tx_Warning_IRQn         = 97,               /**< CAN1 Tx warning interrupt */
+  CAN1_Rx_Warning_IRQn         = 98,               /**< CAN1 Rx warning interrupt */
+  CAN1_Wake_Up_IRQn            = 99                /**< CAN1 wake up interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK66F18.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0TSI0             = 1|0x100U,    /**< TSI0. */
+    kDmaRequestMux0UART0Rx          = 2|0x100U,    /**< UART0 Receive. */
+    kDmaRequestMux0UART0Tx          = 3|0x100U,    /**< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx          = 4|0x100U,    /**< UART1 Receive. */
+    kDmaRequestMux0UART1Tx          = 5|0x100U,    /**< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 Receive. */
+    kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx          = 8|0x100U,    /**< UART3 Receive. */
+    kDmaRequestMux0UART3Tx          = 9|0x100U,    /**< UART3 Transmit. */
+    kDmaRequestMux0UART4            = 10|0x100U,   /**< UART4 Transmit or Receive. */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0I2S0Rx           = 12|0x100U,   /**< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx           = 13|0x100U,   /**< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx           = 14|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 15|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 16|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 17|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0I2C0I2C3         = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C0             = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C3             = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C1I2C2         = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C1             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C2             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0     = 20|0x100U,   /**< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1     = 21|0x100U,   /**< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2     = 22|0x100U,   /**< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3     = 23|0x100U,   /**< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4     = 24|0x100U,   /**< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5     = 25|0x100U,   /**< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6     = 26|0x100U,   /**< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7     = 27|0x100U,   /**< FTM0 C7V. */
+    kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0FTM1Channel0     = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel0     = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0FTM1Channel1     = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0TPM1Channel1     = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0FTM2Channel0     = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel0     = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0FTM2Channel1     = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0TPM2Channel1     = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0FTM3Channel0     = 32|0x100U,   /**< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1     = 33|0x100U,   /**< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2     = 34|0x100U,   /**< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3     = 35|0x100U,   /**< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4     = 36|0x100U,   /**< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5     = 37|0x100U,   /**< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0FTM3Channel6     = 38|0x100U,   /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0SPI2Rx           = 38|0x100U,   /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0FTM3Channel7     = 39|0x100U,   /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0SPI2Tx           = 39|0x100U,   /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0ADC1             = 41|0x100U,   /**< ADC1. */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0CMP1             = 43|0x100U,   /**< CMP1. */
+    kDmaRequestMux0CMP2CMP3         = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0CMP2             = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0CMP3             = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0DAC1             = 46|0x100U,   /**< DAC1. */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0PDB              = 48|0x100U,   /**< PDB0. */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0PortD            = 52|0x100U,   /**< PTD. */
+    kDmaRequestMux0PortE            = 53|0x100U,   /**< PTE. */
+    kDmaRequestMux0IEEE1588Timer0   = 54|0x100U,   /**< ENET IEEE 1588 timer 0. */
+    kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0IEEE1588Timer1   = 55|0x100U,   /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0IEEE1588Timer2   = 56|0x100U,   /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0IEEE1588Timer3   = 57|0x100U,   /**< ENET IEEE 1588 timer 3. */
+    kDmaRequestMux0LPUART0Rx        = 58|0x100U,   /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 59|0x100U,   /**< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADCx_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1A;                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t SC1B;                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t RA;                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __I  uint32_t RB;                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADCx_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADCx_SC1n_ADCH_MASK                        (0x1FU)
+#define ADCx_SC1n_ADCH_SHIFT                       (0U)
+#define ADCx_SC1n_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_ADCH_SHIFT)) & ADCx_SC1n_ADCH_MASK)
+#define ADCx_SC1n_DIFF_MASK                        (0x20U)
+#define ADCx_SC1n_DIFF_SHIFT                       (5U)
+#define ADCx_SC1n_DIFF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_DIFF_SHIFT)) & ADCx_SC1n_DIFF_MASK)
+#define ADCx_SC1n_DIFF ADCx_SC1n_DIFF_MASK
+#define ADCx_SC1n_AIEN_MASK                        (0x40U)
+#define ADCx_SC1n_AIEN_SHIFT                       (6U)
+#define ADCx_SC1n_AIEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_AIEN_SHIFT)) & ADCx_SC1n_AIEN_MASK)
+#define ADCx_SC1n_AIEN ADCx_SC1n_AIEN_MASK
+#define ADCx_SC1n_COCO_MASK                        (0x80U)
+#define ADCx_SC1n_COCO_SHIFT                       (7U)
+#define ADCx_SC1n_COCO_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_COCO_SHIFT)) & ADCx_SC1n_COCO_MASK)
+#define ADCx_SC1n_COCO ADCx_SC1n_COCO_MASK
+
+/* The count of ADCx_SC1n */
+#define ADCx_SC1n_COUNT                            (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADCx_CFG1_ADICLK_MASK                     (0x3U)
+#define ADCx_CFG1_ADICLK_SHIFT                    (0U)
+#define ADCx_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADICLK_SHIFT)) & ADCx_CFG1_ADICLK_MASK)
+#define ADCx_CFG1_MODE_MASK                       (0xCU)
+#define ADCx_CFG1_MODE_SHIFT                      (2U)
+#define ADCx_CFG1_MODE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_MODE_SHIFT)) & ADCx_CFG1_MODE_MASK)
+#define ADCx_CFG1_MODE ADCx_CFG1_MODE_MASK
+#define ADCx_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADCx_CFG1_ADLSMP_SHIFT                    (4U)
+#define ADCx_CFG1_ADLSMP_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLSMP_SHIFT)) & ADCx_CFG1_ADLSMP_MASK)
+#define ADCx_CFG1_ADLSMP ADCx_CFG1_ADLSMP_MASK
+#define ADCx_CFG1_ADIV_MASK                       (0x60U)
+#define ADCx_CFG1_ADIV_SHIFT                      (5U)
+#define ADCx_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADIV_SHIFT)) & ADCx_CFG1_ADIV_MASK)
+#define ADCx_CFG1_ADLPC_MASK                      (0x80U)
+#define ADCx_CFG1_ADLPC_SHIFT                     (7U)
+#define ADCx_CFG1_ADLPC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLPC_SHIFT)) & ADCx_CFG1_ADLPC_MASK)
+#define ADCx_CFG1_ADLPC ADCx_CFG1_ADLPC_MASK
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADCx_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADCx_CFG2_ADLSTS_SHIFT                    (0U)
+#define ADCx_CFG2_ADLSTS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADLSTS_SHIFT)) & ADCx_CFG2_ADLSTS_MASK)
+#define ADCx_CFG2_ADLSTS ADCx_CFG2_ADLSTS_MASK
+#define ADCx_CFG2_ADHSC_MASK                      (0x4U)
+#define ADCx_CFG2_ADHSC_SHIFT                     (2U)
+#define ADCx_CFG2_ADHSC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADHSC_SHIFT)) & ADCx_CFG2_ADHSC_MASK)
+#define ADCx_CFG2_ADHSC ADCx_CFG2_ADHSC_MASK
+#define ADCx_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADCx_CFG2_ADACKEN_SHIFT                   (3U)
+#define ADCx_CFG2_ADACKEN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADACKEN_SHIFT)) & ADCx_CFG2_ADACKEN_MASK)
+#define ADCx_CFG2_ADACKEN ADCx_CFG2_ADACKEN_MASK
+#define ADCx_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADCx_CFG2_MUXSEL_SHIFT                    (4U)
+#define ADCx_CFG2_MUXSEL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_MUXSEL_SHIFT)) & ADCx_CFG2_MUXSEL_MASK)
+#define ADCx_CFG2_MUXSEL ADCx_CFG2_MUXSEL_MASK
+
+/*! @name R - ADC Data Result Register */
+#define ADCx_R_D_MASK                             (0xFFFFU)
+#define ADCx_R_D_SHIFT                            (0U)
+#define ADCx_R_D_SET(x)                           (((uint32_t)(((uint32_t)(x)) << ADCx_R_D_SHIFT)) & ADCx_R_D_MASK)
+#define ADCx_R_D ADCx_R_D_MASK
+
+/* The count of ADCx_R */
+#define ADCx_R_COUNT                              (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADCx_CV1_CV_MASK                          (0xFFFFU)
+#define ADCx_CV1_CV_SHIFT                         (0U)
+#define ADCx_CV1_CV_SET(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CV1_CV_SHIFT)) & ADCx_CV1_CV_MASK)
+#define ADCx_CV1_CV ADCx_CV1_CV_MASK
+
+/*! @name CV2 - Compare Value Registers */
+#define ADCx_CV2_CV_MASK                          (0xFFFFU)
+#define ADCx_CV2_CV_SHIFT                         (0U)
+#define ADCx_CV2_CV_SET(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CV2_CV_SHIFT)) & ADCx_CV2_CV_MASK)
+#define ADCx_CV2_CV ADCx_CV2_CV_MASK
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADCx_SC2_REFSEL_MASK                      (0x3U)
+#define ADCx_SC2_REFSEL_SHIFT                     (0U)
+#define ADCx_SC2_REFSEL_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_REFSEL_SHIFT)) & ADCx_SC2_REFSEL_MASK)
+#define ADCx_SC2_REFSEL ADCx_SC2_REFSEL_MASK
+#define ADCx_SC2_DMAEN_MASK                       (0x4U)
+#define ADCx_SC2_DMAEN_SHIFT                      (2U)
+#define ADCx_SC2_DMAEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_DMAEN_SHIFT)) & ADCx_SC2_DMAEN_MASK)
+#define ADCx_SC2_DMAEN ADCx_SC2_DMAEN_MASK
+#define ADCx_SC2_ACREN_MASK                       (0x8U)
+#define ADCx_SC2_ACREN_SHIFT                      (3U)
+#define ADCx_SC2_ACREN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACREN_SHIFT)) & ADCx_SC2_ACREN_MASK)
+#define ADCx_SC2_ACREN ADCx_SC2_ACREN_MASK
+#define ADCx_SC2_ACFGT_MASK                       (0x10U)
+#define ADCx_SC2_ACFGT_SHIFT                      (4U)
+#define ADCx_SC2_ACFGT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFGT_SHIFT)) & ADCx_SC2_ACFGT_MASK)
+#define ADCx_SC2_ACFGT ADCx_SC2_ACFGT_MASK
+#define ADCx_SC2_ACFE_MASK                        (0x20U)
+#define ADCx_SC2_ACFE_SHIFT                       (5U)
+#define ADCx_SC2_ACFE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFE_SHIFT)) & ADCx_SC2_ACFE_MASK)
+#define ADCx_SC2_ACFE ADCx_SC2_ACFE_MASK
+#define ADCx_SC2_ADTRG_MASK                       (0x40U)
+#define ADCx_SC2_ADTRG_SHIFT                      (6U)
+#define ADCx_SC2_ADTRG_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADTRG_SHIFT)) & ADCx_SC2_ADTRG_MASK)
+#define ADCx_SC2_ADTRG ADCx_SC2_ADTRG_MASK
+#define ADCx_SC2_ADACT_MASK                       (0x80U)
+#define ADCx_SC2_ADACT_SHIFT                      (7U)
+#define ADCx_SC2_ADACT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADACT_SHIFT)) & ADCx_SC2_ADACT_MASK)
+#define ADCx_SC2_ADACT ADCx_SC2_ADACT_MASK
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADCx_SC3_AVGS_MASK                        (0x3U)
+#define ADCx_SC3_AVGS_SHIFT                       (0U)
+#define ADCx_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGS_SHIFT)) & ADCx_SC3_AVGS_MASK)
+#define ADCx_SC3_AVGE_MASK                        (0x4U)
+#define ADCx_SC3_AVGE_SHIFT                       (2U)
+#define ADCx_SC3_AVGE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGE_SHIFT)) & ADCx_SC3_AVGE_MASK)
+#define ADCx_SC3_AVGE ADCx_SC3_AVGE_MASK
+#define ADCx_SC3_ADCO_MASK                        (0x8U)
+#define ADCx_SC3_ADCO_SHIFT                       (3U)
+#define ADCx_SC3_ADCO_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_ADCO_SHIFT)) & ADCx_SC3_ADCO_MASK)
+#define ADCx_SC3_ADCO ADCx_SC3_ADCO_MASK
+#define ADCx_SC3_CALF_MASK                        (0x40U)
+#define ADCx_SC3_CALF_SHIFT                       (6U)
+#define ADCx_SC3_CALF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CALF_SHIFT)) & ADCx_SC3_CALF_MASK)
+#define ADCx_SC3_CALF ADCx_SC3_CALF_MASK
+#define ADCx_SC3_CAL_MASK                         (0x80U)
+#define ADCx_SC3_CAL_SHIFT                        (7U)
+#define ADCx_SC3_CAL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CAL_SHIFT)) & ADCx_SC3_CAL_MASK)
+#define ADCx_SC3_CAL ADCx_SC3_CAL_MASK
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADCx_OFS_OFS_MASK                         (0xFFFFU)
+#define ADCx_OFS_OFS_SHIFT                        (0U)
+#define ADCx_OFS_OFS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_OFS_OFS_SHIFT)) & ADCx_OFS_OFS_MASK)
+#define ADCx_OFS_OFS ADCx_OFS_OFS_MASK
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADCx_PG_PG_MASK                           (0xFFFFU)
+#define ADCx_PG_PG_SHIFT                          (0U)
+#define ADCx_PG_PG_SET(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_PG_PG_SHIFT)) & ADCx_PG_PG_MASK)
+#define ADCx_PG_PG ADCx_PG_PG_MASK
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADCx_MG_MG_MASK                           (0xFFFFU)
+#define ADCx_MG_MG_SHIFT                          (0U)
+#define ADCx_MG_MG_SET(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_MG_MG_SHIFT)) & ADCx_MG_MG_MASK)
+#define ADCx_MG_MG ADCx_MG_MG_MASK
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLPD_CLPD_MASK                       (0x3FU)
+#define ADCx_CLPD_CLPD_SHIFT                      (0U)
+#define ADCx_CLPD_CLPD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLPD_CLPD_SHIFT)) & ADCx_CLPD_CLPD_MASK)
+#define ADCx_CLPD_CLPD ADCx_CLPD_CLPD_MASK
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLPS_CLPS_MASK                       (0x3FU)
+#define ADCx_CLPS_CLPS_SHIFT                      (0U)
+#define ADCx_CLPS_CLPS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLPS_CLPS_SHIFT)) & ADCx_CLPS_CLPS_MASK)
+#define ADCx_CLPS_CLPS ADCx_CLPS_CLPS_MASK
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADCx_CLP4_CLP4_SHIFT                      (0U)
+#define ADCx_CLP4_CLP4_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP4_CLP4_SHIFT)) & ADCx_CLP4_CLP4_MASK)
+#define ADCx_CLP4_CLP4 ADCx_CLP4_CLP4_MASK
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADCx_CLP3_CLP3_SHIFT                      (0U)
+#define ADCx_CLP3_CLP3_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP3_CLP3_SHIFT)) & ADCx_CLP3_CLP3_MASK)
+#define ADCx_CLP3_CLP3 ADCx_CLP3_CLP3_MASK
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP2_CLP2_MASK                       (0xFFU)
+#define ADCx_CLP2_CLP2_SHIFT                      (0U)
+#define ADCx_CLP2_CLP2_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP2_CLP2_SHIFT)) & ADCx_CLP2_CLP2_MASK)
+#define ADCx_CLP2_CLP2 ADCx_CLP2_CLP2_MASK
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP1_CLP1_MASK                       (0x7FU)
+#define ADCx_CLP1_CLP1_SHIFT                      (0U)
+#define ADCx_CLP1_CLP1_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP1_CLP1_SHIFT)) & ADCx_CLP1_CLP1_MASK)
+#define ADCx_CLP1_CLP1 ADCx_CLP1_CLP1_MASK
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP0_CLP0_MASK                       (0x3FU)
+#define ADCx_CLP0_CLP0_SHIFT                      (0U)
+#define ADCx_CLP0_CLP0_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP0_CLP0_SHIFT)) & ADCx_CLP0_CLP0_MASK)
+#define ADCx_CLP0_CLP0 ADCx_CLP0_CLP0_MASK
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLMD_CLMD_MASK                       (0x3FU)
+#define ADCx_CLMD_CLMD_SHIFT                      (0U)
+#define ADCx_CLMD_CLMD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLMD_CLMD_SHIFT)) & ADCx_CLMD_CLMD_MASK)
+#define ADCx_CLMD_CLMD ADCx_CLMD_CLMD_MASK
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLMS_CLMS_MASK                       (0x3FU)
+#define ADCx_CLMS_CLMS_SHIFT                      (0U)
+#define ADCx_CLMS_CLMS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLMS_CLMS_SHIFT)) & ADCx_CLMS_CLMS_MASK)
+#define ADCx_CLMS_CLMS ADCx_CLMS_CLMS_MASK
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADCx_CLM4_CLM4_SHIFT                      (0U)
+#define ADCx_CLM4_CLM4_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM4_CLM4_SHIFT)) & ADCx_CLM4_CLM4_MASK)
+#define ADCx_CLM4_CLM4 ADCx_CLM4_CLM4_MASK
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADCx_CLM3_CLM3_SHIFT                      (0U)
+#define ADCx_CLM3_CLM3_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM3_CLM3_SHIFT)) & ADCx_CLM3_CLM3_MASK)
+#define ADCx_CLM3_CLM3 ADCx_CLM3_CLM3_MASK
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM2_CLM2_MASK                       (0xFFU)
+#define ADCx_CLM2_CLM2_SHIFT                      (0U)
+#define ADCx_CLM2_CLM2_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM2_CLM2_SHIFT)) & ADCx_CLM2_CLM2_MASK)
+#define ADCx_CLM2_CLM2 ADCx_CLM2_CLM2_MASK
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM1_CLM1_MASK                       (0x7FU)
+#define ADCx_CLM1_CLM1_SHIFT                      (0U)
+#define ADCx_CLM1_CLM1_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM1_CLM1_SHIFT)) & ADCx_CLM1_CLM1_MASK)
+#define ADCx_CLM1_CLM1 ADCx_CLM1_CLM1_MASK
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM0_CLM0_MASK                       (0x3FU)
+#define ADCx_CLM0_CLM0_SHIFT                      (0U)
+#define ADCx_CLM0_CLM0_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM0_CLM0_SHIFT)) & ADCx_CLM0_CLM0_MASK)
+#define ADCx_CLM0_CLM0 ADCx_CLM0_CLM0_MASK
+
+
+/*!
+ * @}
+ */ /* end of group ADCx_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_TypeDef *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_TypeDef *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADCx_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADCx_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADCx_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADCx_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+} AIPS_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/*! @name MPRA - Master Privilege Register A */
+#define AIPS_MPRA_MPL6_MASK                      (0x10U)
+#define AIPS_MPRA_MPL6_SHIFT                     (4U)
+#define AIPS_MPRA_MPL6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
+#define AIPS_MPRA_MPL6 AIPS_MPRA_MPL6_MASK
+#define AIPS_MPRA_MTW6_MASK                      (0x20U)
+#define AIPS_MPRA_MTW6_SHIFT                     (5U)
+#define AIPS_MPRA_MTW6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
+#define AIPS_MPRA_MTW6 AIPS_MPRA_MTW6_MASK
+#define AIPS_MPRA_MTR6_MASK                      (0x40U)
+#define AIPS_MPRA_MTR6_SHIFT                     (6U)
+#define AIPS_MPRA_MTR6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
+#define AIPS_MPRA_MTR6 AIPS_MPRA_MTR6_MASK
+#define AIPS_MPRA_MPL5_MASK                      (0x100U)
+#define AIPS_MPRA_MPL5_SHIFT                     (8U)
+#define AIPS_MPRA_MPL5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MPL5 AIPS_MPRA_MPL5_MASK
+#define AIPS_MPRA_MTW5_MASK                      (0x200U)
+#define AIPS_MPRA_MTW5_SHIFT                     (9U)
+#define AIPS_MPRA_MTW5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTW5 AIPS_MPRA_MTW5_MASK
+#define AIPS_MPRA_MTR5_MASK                      (0x400U)
+#define AIPS_MPRA_MTR5_SHIFT                     (10U)
+#define AIPS_MPRA_MTR5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MTR5 AIPS_MPRA_MTR5_MASK
+#define AIPS_MPRA_MPL4_MASK                      (0x1000U)
+#define AIPS_MPRA_MPL4_SHIFT                     (12U)
+#define AIPS_MPRA_MPL4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MPL4 AIPS_MPRA_MPL4_MASK
+#define AIPS_MPRA_MTW4_MASK                      (0x2000U)
+#define AIPS_MPRA_MTW4_SHIFT                     (13U)
+#define AIPS_MPRA_MTW4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTW4 AIPS_MPRA_MTW4_MASK
+#define AIPS_MPRA_MTR4_MASK                      (0x4000U)
+#define AIPS_MPRA_MTR4_SHIFT                     (14U)
+#define AIPS_MPRA_MTR4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MTR4 AIPS_MPRA_MTR4_MASK
+#define AIPS_MPRA_MPL3_MASK                      (0x10000U)
+#define AIPS_MPRA_MPL3_SHIFT                     (16U)
+#define AIPS_MPRA_MPL3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MPL3 AIPS_MPRA_MPL3_MASK
+#define AIPS_MPRA_MTW3_MASK                      (0x20000U)
+#define AIPS_MPRA_MTW3_SHIFT                     (17U)
+#define AIPS_MPRA_MTW3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTW3 AIPS_MPRA_MTW3_MASK
+#define AIPS_MPRA_MTR3_MASK                      (0x40000U)
+#define AIPS_MPRA_MTR3_SHIFT                     (18U)
+#define AIPS_MPRA_MTR3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MTR3 AIPS_MPRA_MTR3_MASK
+#define AIPS_MPRA_MPL2_MASK                      (0x100000U)
+#define AIPS_MPRA_MPL2_SHIFT                     (20U)
+#define AIPS_MPRA_MPL2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MPL2 AIPS_MPRA_MPL2_MASK
+#define AIPS_MPRA_MTW2_MASK                      (0x200000U)
+#define AIPS_MPRA_MTW2_SHIFT                     (21U)
+#define AIPS_MPRA_MTW2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTW2 AIPS_MPRA_MTW2_MASK
+#define AIPS_MPRA_MTR2_MASK                      (0x400000U)
+#define AIPS_MPRA_MTR2_SHIFT                     (22U)
+#define AIPS_MPRA_MTR2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MTR2 AIPS_MPRA_MTR2_MASK
+#define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
+#define AIPS_MPRA_MPL1_SHIFT                     (24U)
+#define AIPS_MPRA_MPL1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MPL1 AIPS_MPRA_MPL1_MASK
+#define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
+#define AIPS_MPRA_MTW1_SHIFT                     (25U)
+#define AIPS_MPRA_MTW1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTW1 AIPS_MPRA_MTW1_MASK
+#define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
+#define AIPS_MPRA_MTR1_SHIFT                     (26U)
+#define AIPS_MPRA_MTR1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MTR1 AIPS_MPRA_MTR1_MASK
+#define AIPS_MPRA_MPL0_MASK                      (0x10000000U)
+#define AIPS_MPRA_MPL0_SHIFT                     (28U)
+#define AIPS_MPRA_MPL0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MPL0 AIPS_MPRA_MPL0_MASK
+#define AIPS_MPRA_MTW0_MASK                      (0x20000000U)
+#define AIPS_MPRA_MTW0_SHIFT                     (29U)
+#define AIPS_MPRA_MTW0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTW0 AIPS_MPRA_MTW0_MASK
+#define AIPS_MPRA_MTR0_MASK                      (0x40000000U)
+#define AIPS_MPRA_MTR0_SHIFT                     (30U)
+#define AIPS_MPRA_MTR0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+#define AIPS_MPRA_MTR0 AIPS_MPRA_MTR0_MASK
+
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7_MASK                      (0x1U)
+#define AIPS_PACRA_TP7_SHIFT                     (0U)
+#define AIPS_PACRA_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_TP7 AIPS_PACRA_TP7_MASK
+#define AIPS_PACRA_WP7_MASK                      (0x2U)
+#define AIPS_PACRA_WP7_SHIFT                     (1U)
+#define AIPS_PACRA_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_WP7 AIPS_PACRA_WP7_MASK
+#define AIPS_PACRA_SP7_MASK                      (0x4U)
+#define AIPS_PACRA_SP7_SHIFT                     (2U)
+#define AIPS_PACRA_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_SP7 AIPS_PACRA_SP7_MASK
+#define AIPS_PACRA_TP6_MASK                      (0x10U)
+#define AIPS_PACRA_TP6_SHIFT                     (4U)
+#define AIPS_PACRA_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_TP6 AIPS_PACRA_TP6_MASK
+#define AIPS_PACRA_WP6_MASK                      (0x20U)
+#define AIPS_PACRA_WP6_SHIFT                     (5U)
+#define AIPS_PACRA_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_WP6 AIPS_PACRA_WP6_MASK
+#define AIPS_PACRA_SP6_MASK                      (0x40U)
+#define AIPS_PACRA_SP6_SHIFT                     (6U)
+#define AIPS_PACRA_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_SP6 AIPS_PACRA_SP6_MASK
+#define AIPS_PACRA_TP5_MASK                      (0x100U)
+#define AIPS_PACRA_TP5_SHIFT                     (8U)
+#define AIPS_PACRA_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_TP5 AIPS_PACRA_TP5_MASK
+#define AIPS_PACRA_WP5_MASK                      (0x200U)
+#define AIPS_PACRA_WP5_SHIFT                     (9U)
+#define AIPS_PACRA_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_WP5 AIPS_PACRA_WP5_MASK
+#define AIPS_PACRA_SP5_MASK                      (0x400U)
+#define AIPS_PACRA_SP5_SHIFT                     (10U)
+#define AIPS_PACRA_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_SP5 AIPS_PACRA_SP5_MASK
+#define AIPS_PACRA_TP4_MASK                      (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT                     (12U)
+#define AIPS_PACRA_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_TP4 AIPS_PACRA_TP4_MASK
+#define AIPS_PACRA_WP4_MASK                      (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT                     (13U)
+#define AIPS_PACRA_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_WP4 AIPS_PACRA_WP4_MASK
+#define AIPS_PACRA_SP4_MASK                      (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT                     (14U)
+#define AIPS_PACRA_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_SP4 AIPS_PACRA_SP4_MASK
+#define AIPS_PACRA_TP3_MASK                      (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT                     (16U)
+#define AIPS_PACRA_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_TP3 AIPS_PACRA_TP3_MASK
+#define AIPS_PACRA_WP3_MASK                      (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT                     (17U)
+#define AIPS_PACRA_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_WP3 AIPS_PACRA_WP3_MASK
+#define AIPS_PACRA_SP3_MASK                      (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT                     (18U)
+#define AIPS_PACRA_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_SP3 AIPS_PACRA_SP3_MASK
+#define AIPS_PACRA_TP2_MASK                      (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT                     (20U)
+#define AIPS_PACRA_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_TP2 AIPS_PACRA_TP2_MASK
+#define AIPS_PACRA_WP2_MASK                      (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT                     (21U)
+#define AIPS_PACRA_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_WP2 AIPS_PACRA_WP2_MASK
+#define AIPS_PACRA_SP2_MASK                      (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT                     (22U)
+#define AIPS_PACRA_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_SP2 AIPS_PACRA_SP2_MASK
+#define AIPS_PACRA_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT                     (24U)
+#define AIPS_PACRA_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_TP1 AIPS_PACRA_TP1_MASK
+#define AIPS_PACRA_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT                     (25U)
+#define AIPS_PACRA_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_WP1 AIPS_PACRA_WP1_MASK
+#define AIPS_PACRA_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT                     (26U)
+#define AIPS_PACRA_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_SP1 AIPS_PACRA_SP1_MASK
+#define AIPS_PACRA_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT                     (28U)
+#define AIPS_PACRA_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_TP0 AIPS_PACRA_TP0_MASK
+#define AIPS_PACRA_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT                     (29U)
+#define AIPS_PACRA_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_WP0 AIPS_PACRA_WP0_MASK
+#define AIPS_PACRA_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT                     (30U)
+#define AIPS_PACRA_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+#define AIPS_PACRA_SP0 AIPS_PACRA_SP0_MASK
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7_MASK                      (0x1U)
+#define AIPS_PACRB_TP7_SHIFT                     (0U)
+#define AIPS_PACRB_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_TP7 AIPS_PACRB_TP7_MASK
+#define AIPS_PACRB_WP7_MASK                      (0x2U)
+#define AIPS_PACRB_WP7_SHIFT                     (1U)
+#define AIPS_PACRB_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_WP7 AIPS_PACRB_WP7_MASK
+#define AIPS_PACRB_SP7_MASK                      (0x4U)
+#define AIPS_PACRB_SP7_SHIFT                     (2U)
+#define AIPS_PACRB_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_SP7 AIPS_PACRB_SP7_MASK
+#define AIPS_PACRB_TP6_MASK                      (0x10U)
+#define AIPS_PACRB_TP6_SHIFT                     (4U)
+#define AIPS_PACRB_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_TP6 AIPS_PACRB_TP6_MASK
+#define AIPS_PACRB_WP6_MASK                      (0x20U)
+#define