diff options
Diffstat (limited to 'lib/chibios-contrib/os/hal/boards/MICROBIT')
-rw-r--r-- | lib/chibios-contrib/os/hal/boards/MICROBIT/board.c | 91 | ||||
-rw-r--r-- | lib/chibios-contrib/os/hal/boards/MICROBIT/board.h | 147 | ||||
-rw-r--r-- | lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk | 9 |
3 files changed, 247 insertions, 0 deletions
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c new file mode 100644 index 000000000..12f78e29b --- /dev/null +++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.c | |||
@@ -0,0 +1,91 @@ | |||
1 | /* | ||
2 | Copyright (C) 2017 Stéphane D'Alu | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | #include "hal.h" | ||
18 | |||
19 | #if HAL_USE_PAL || defined(__DOXYGEN__) | ||
20 | |||
21 | /* RAM Banks | ||
22 | * (Values are defined in Nordic gcc_startup_nrf51.s) | ||
23 | */ | ||
24 | #define NRF_POWER_RAMON_ADDRESS 0x40000524 | ||
25 | #define NRF_POWER_RAMONB_ADDRESS 0x40000554 | ||
26 | #define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3 | ||
27 | |||
28 | /** | ||
29 | * @brief PAL setup. | ||
30 | * @details Digital I/O ports static configuration as defined in @p board.h. | ||
31 | * This variable is used by the HAL when initializing the PAL driver. | ||
32 | */ | ||
33 | const PALConfig pal_default_config = | ||
34 | { | ||
35 | .pads = { | ||
36 | PAL_MODE_OUTPUT_OPENDRAIN, /* P0.0 : SCL P19 */ | ||
37 | PAL_MODE_UNCONNECTED, /* P0.1 : PAD1 P2 */ | ||
38 | PAL_MODE_UNCONNECTED, /* P0.2 : PAD2 P1 */ | ||
39 | PAL_MODE_UNCONNECTED, /* P0.3 : PAD3 P0 */ | ||
40 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.4 : COL1 P3 */ | ||
41 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : COL2 P4 */ | ||
42 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : COL3 P10 */ | ||
43 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.7 : COL4 */ | ||
44 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.8 : COL5 */ | ||
45 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.9 : COL6 */ | ||
46 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.10: COL7 P9 */ | ||
47 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.11: COL8 P7 */ | ||
48 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.12: COL9 P6 */ | ||
49 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.13: ROW1 */ | ||
50 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.14: ROW2 */ | ||
51 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.15: ROW3 */ | ||
52 | PAL_MODE_UNCONNECTED, /* P0.16 P16 */ | ||
53 | PAL_MODE_INPUT, /* P0.17: BTN_A P5 */ | ||
54 | PAL_MODE_UNCONNECTED, /* P0.18 P8 */ | ||
55 | PAL_MODE_INPUT, /* P0.19: BTN_RST */ | ||
56 | PAL_MODE_UNCONNECTED, /* P0.20 P12 */ | ||
57 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: SPI_MOSI P15 */ | ||
58 | PAL_MODE_INPUT_PULLUP, /* P0.22: SPI_MISO P14 */ | ||
59 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.23: SPI_SCK P13 */ | ||
60 | PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: UART_TX */ | ||
61 | PAL_MODE_INPUT_PULLUP, /* P0.25: UART_RX */ | ||
62 | PAL_MODE_INPUT, /* P0.26: BTN_B P11 */ | ||
63 | PAL_MODE_INPUT, /* P0.27: ACC_INT2 */ | ||
64 | PAL_MODE_INPUT, /* P0.28: ACC_INT1 */ | ||
65 | PAL_MODE_INPUT, /* P0.29: MAG_INT1 */ | ||
66 | PAL_MODE_OUTPUT_OPENDRAIN, /* P0.30: SDA P20 */ | ||
67 | PAL_MODE_UNCONNECTED, /* P0.31 */ | ||
68 | }, | ||
69 | }; | ||
70 | #endif | ||
71 | |||
72 | /** | ||
73 | * @brief Early initialization code. | ||
74 | * @details This initialization is performed just after reset before BSS and | ||
75 | * DATA segments initialization. | ||
76 | */ | ||
77 | void __early_init(void) | ||
78 | { | ||
79 | /* Make sure ALL RAM banks are powered on */ | ||
80 | *(uint32_t *)NRF_POWER_RAMON_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; | ||
81 | *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; | ||
82 | } | ||
83 | |||
84 | /** | ||
85 | * @brief Late initialization code. | ||
86 | * @note This initialization is performed after BSS and DATA segments | ||
87 | * initialization and before invoking the main() function. | ||
88 | */ | ||
89 | void boardInit(void) | ||
90 | { | ||
91 | } | ||
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h new file mode 100644 index 000000000..157bd7502 --- /dev/null +++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.h | |||
@@ -0,0 +1,147 @@ | |||
1 | /* | ||
2 | Copyright (C) 2016 Stephane D'Alu | ||
3 | |||
4 | Licensed under the Apache License, Version 2.0 (the "License"); | ||
5 | you may not use this file except in compliance with the License. | ||
6 | You may obtain a copy of the License at | ||
7 | |||
8 | http://www.apache.org/licenses/LICENSE-2.0 | ||
9 | |||
10 | Unless required by applicable law or agreed to in writing, software | ||
11 | distributed under the License is distributed on an "AS IS" BASIS, | ||
12 | WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. | ||
13 | See the License for the specific language governing permissions and | ||
14 | limitations under the License. | ||
15 | */ | ||
16 | |||
17 | #ifndef _BOARD_H_ | ||
18 | #define _BOARD_H_ | ||
19 | |||
20 | /* | ||
21 | * See: https://www.microbit.co.uk/device/pins | ||
22 | * https://lancaster-university.github.io/microbit-docs/ubit/display/ | ||
23 | */ | ||
24 | |||
25 | /* Board identifier. */ | ||
26 | #define BOARD_MICROBIT | ||
27 | #define BOARD_NAME "micro:bit" | ||
28 | |||
29 | /* Board oscillators-related settings. */ | ||
30 | #define NRF51_XTAL_VALUE 16000000 | ||
31 | #define NRF51_LFCLK_SOURCE 0 /* RC oscillator */ | ||
32 | |||
33 | /* | ||
34 | * IO pins assignments. | ||
35 | */ | ||
36 | #define IOPORT1_P0 3U | ||
37 | #define IOPORT1_P1 2U | ||
38 | #define IOPORT1_P2 1U | ||
39 | #define IOPORT1_P3 4U | ||
40 | #define IOPORT1_P4 5U | ||
41 | #define IOPORT1_P5 17U | ||
42 | #define IOPORT1_P6 12U | ||
43 | #define IOPORT1_P7 11U | ||
44 | #define IOPORT1_P8 18U | ||
45 | #define IOPORT1_P9 10U | ||
46 | #define IOPORT1_P10 6U | ||
47 | #define IOPORT1_P11 26U | ||
48 | #define IOPORT1_P12 20U | ||
49 | #define IOPORT1_P13 23U | ||
50 | #define IOPORT1_P14 22U | ||
51 | #define IOPORT1_P15 21U | ||
52 | #define IOPORT1_P16 16U | ||
53 | #define IOPORT1_P19 0U | ||
54 | #define IOPORT1_P20 30U | ||
55 | #define IOPORT1_BTN_A 17U | ||
56 | #define IOPORT1_BTN_B 26U | ||
57 | #define IOPORT1_BTN_RST 19U | ||
58 | #define IOPORT1_LED_COL_1 4U | ||
59 | #define IOPORT1_LED_COL_2 5U | ||
60 | #define IOPORT1_LED_COL_3 6U | ||
61 | #define IOPORT1_LED_COL_4 7U | ||
62 | #define IOPORT1_LED_COL_5 8U | ||
63 | #define IOPORT1_LED_COL_6 9U | ||
64 | #define IOPORT1_LED_COL_7 10U | ||
65 | #define IOPORT1_LED_COL_8 11U | ||
66 | #define IOPORT1_LED_COL_9 12U | ||
67 | #define IOPORT1_LED_ROW_1 13U | ||
68 | #define IOPORT1_LED_ROW_2 14U | ||
69 | #define IOPORT1_LED_ROW_3 15U | ||
70 | #define IOPORT1_PAD_0 IOPORT1_P0 | ||
71 | #define IOPORT1_PAD_1 IOPORT1_P1 | ||
72 | #define IOPORT1_PAD_2 IOPORT1_P2 | ||
73 | #define IOPORT1_SPI_MOSI 21U | ||
74 | #define IOPORT1_SPI_MISO 22U | ||
75 | #define IOPORT1_SPI_SCK 23U | ||
76 | #define IOPORT1_I2C_SCL 0U | ||
77 | #define IOPORT1_I2C_SDA 30U | ||
78 | #define IOPORT1_UART_TX 24U | ||
79 | #define IOPORT1_UART_RX 25U | ||
80 | #define IOPORT1_ACC_INT1 28U | ||
81 | #define IOPORT1_ACC_INT2 27U | ||
82 | #define IOPORT1_MAG_INT1 29U | ||
83 | |||
84 | |||
85 | /* | ||
86 | * IO lines assignments. | ||
87 | */ | ||
88 | #define LINE_P0 PAL_LINE(IOPORT1, IOPORT1_P0) | ||
89 | #define LINE_P1 PAL_LINE(IOPORT1, IOPORT1_P1) | ||
90 | #define LINE_P2 PAL_LINE(IOPORT1, IOPORT1_P2) | ||
91 | #define LINE_P3 PAL_LINE(IOPORT1, IOPORT1_P3) | ||
92 | #define LINE_P4 PAL_LINE(IOPORT1, IOPORT1_P4) | ||
93 | #define LINE_P5 PAL_LINE(IOPORT1, IOPORT1_P5) | ||
94 | #define LINE_P6 PAL_LINE(IOPORT1, IOPORT1_P6) | ||
95 | #define LINE_P7 PAL_LINE(IOPORT1, IOPORT1_P7) | ||
96 | #define LINE_P8 PAL_LINE(IOPORT1, IOPORT1_P8) | ||
97 | #define LINE_P9 PAL_LINE(IOPORT1, IOPORT1_P9) | ||
98 | #define LINE_P10 PAL_LINE(IOPORT1, IOPORT1_P10) | ||
99 | #define LINE_P11 PAL_LINE(IOPORT1, IOPORT1_P11) | ||
100 | #define LINE_P12 PAL_LINE(IOPORT1, IOPORT1_P12) | ||
101 | #define LINE_P13 PAL_LINE(IOPORT1, IOPORT1_P13) | ||
102 | #define LINE_P14 PAL_LINE(IOPORT1, IOPORT1_P14) | ||
103 | #define LINE_P15 PAL_LINE(IOPORT1, IOPORT1_P15) | ||
104 | #define LINE_P16 PAL_LINE(IOPORT1, IOPORT1_P16) | ||
105 | #define LINE_P19 PAL_LINE(IOPORT1, IOPORT1_P19) | ||
106 | #define LINE_P20 PAL_LINE(IOPORT1, IOPORT1_P20) | ||
107 | #define LINE_BTN_A PAL_LINE(IOPORT1, IOPORT1_BTN_A) | ||
108 | #define LINE_BTN_B PAL_LINE(IOPORT1, IOPORT1_BTN_B) | ||
109 | #define LINE_BTN_RST PAL_LINE(IOPORT1, IOPORT1_BTN_RST) | ||
110 | #define LINE_LED_COL_1 PAL_LINE(IOPORT1, IOPORT1_LED_COL_1) | ||
111 | #define LINE_LED_COL_2 PAL_LINE(IOPORT1, IOPORT1_LED_COL_2) | ||
112 | #define LINE_LED_COL_3 PAL_LINE(IOPORT1, IOPORT1_LED_COL_3) | ||
113 | #define LINE_LED_COL_4 PAL_LINE(IOPORT1, IOPORT1_LED_COL_4) | ||
114 | #define LINE_LED_COL_5 PAL_LINE(IOPORT1, IOPORT1_LED_COL_5) | ||
115 | #define LINE_LED_COL_6 PAL_LINE(IOPORT1, IOPORT1_LED_COL_6) | ||
116 | #define LINE_LED_COL_7 PAL_LINE(IOPORT1, IOPORT1_LED_COL_7) | ||
117 | #define LINE_LED_COL_8 PAL_LINE(IOPORT1, IOPORT1_LED_COL_8) | ||
118 | #define LINE_LED_COL_9 PAL_LINE(IOPORT1, IOPORT1_LED_COL_9) | ||
119 | #define LINE_LED_ROW_1 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1) | ||
120 | #define LINE_LED_ROW_2 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2) | ||
121 | #define LINE_LED_ROW_3 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3) | ||
122 | #define LINE_PAD_0 PAL_LINE(IOPORT1, IOPORT1_PAD_0) | ||
123 | #define LINE_PAD_1 PAL_LINE(IOPORT1, IOPORT1_PAD_1) | ||
124 | #define LINE_PAD_2 PAL_LINE(IOPORT1, IOPORT1_PAD_2) | ||
125 | #define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) | ||
126 | #define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) | ||
127 | #define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) | ||
128 | #define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) | ||
129 | #define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) | ||
130 | #define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) | ||
131 | #define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) | ||
132 | #define LINE_ACC_INT1 PAL_LINE(IOPORT1, IOPORT1_ACC_INT1) | ||
133 | #define LINE_ACC_INT2 PAL_LINE(IOPORT1, IOPORT1_ACC_INT2) | ||
134 | #define LINE_MAG_INT1 PAL_LINE(IOPORT1, IOPORT1_MAG_INT1) | ||
135 | |||
136 | |||
137 | #if !defined(_FROM_ASM_) | ||
138 | #ifdef __cplusplus | ||
139 | extern "C" { | ||
140 | #endif | ||
141 | void boardInit(void); | ||
142 | #ifdef __cplusplus | ||
143 | } | ||
144 | #endif | ||
145 | #endif /* _FROM_ASM_ */ | ||
146 | |||
147 | #endif /* _BOARD_H_ */ | ||
diff --git a/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk new file mode 100644 index 000000000..8e26ae6a2 --- /dev/null +++ b/lib/chibios-contrib/os/hal/boards/MICROBIT/board.mk | |||
@@ -0,0 +1,9 @@ | |||
1 | # List of all the board related files. | ||
2 | BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c | ||
3 | |||
4 | # Required include directories | ||
5 | BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT | ||
6 | |||
7 | # Shared variables | ||
8 | ALLCSRC += $(BOARDSRC) | ||
9 | ALLINC += $(BOARDINC) | ||