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-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.c294
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.h164
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.c422
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.h114
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashDev.c25
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashOS.h65
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashPrg.c197
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QSPI.uvproj476
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QuadSPI_4KB_SEC.FLMbin0 -> 1266960 bytes
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.c161
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.h554
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Target.lin22
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/readme.txt5
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.c304
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.c294
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.h164
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/clock_config.c420
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/clock_config.h114
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/dcd.c304
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/dcd.h32
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/peripherals.c24
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/peripherals.h28
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/pin_mux.c605
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/pin_mux.h436
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/xip/driver_xip_board.cmake16
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/xip/evkmimxrt1024_flexspi_nor_config.c48
-rw-r--r--lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/xip/evkmimxrt1024_flexspi_nor_config.h266
28 files changed, 5586 insertions, 0 deletions
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.c
new file mode 100644
index 000000000..8ff218b60
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.c
@@ -0,0 +1,294 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51/* MPU configuration. */
52void BOARD_ConfigMPU(void)
53{
54#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
55 extern uint32_t Image$$RW_m_ncache$$Base[];
56 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
58 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
61 0 :
62 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
63#elif defined(__MCUXPRESSO)
64 extern uint32_t __base_NCACHE_REGION;
65 extern uint32_t __top_NCACHE_REGION;
66 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
67 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
68#elif defined(__ICCARM__) || defined(__GNUC__)
69 extern uint32_t __NCACHE_REGION_START[];
70 extern uint32_t __NCACHE_REGION_SIZE[];
71 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
72 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
73#endif
74 volatile uint32_t i = 0;
75
76 /* Disable I cache and D cache */
77 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
78 {
79 SCB_DisableICache();
80 }
81 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
82 {
83 SCB_DisableDCache();
84 }
85
86 /* Disable MPU */
87 ARM_MPU_Disable();
88
89 /* MPU configure:
90 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
91 * SubRegionDisable, Size)
92 * API in mpu_armv7.h.
93 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
94 * disabled.
95 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
96 * Privileged mode.
97 * Use MACROS defined in mpu_armv7.h:
98 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
99 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
100 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
101 * 0 x 0 0 Strongly Ordered shareable
102 * 0 x 0 1 Device shareable
103 * 0 0 1 0 Normal not shareable Outer and inner write
104 * through no write allocate
105 * 0 0 1 1 Normal not shareable Outer and inner write
106 * back no write allocate
107 * 0 1 1 0 Normal shareable Outer and inner write
108 * through no write allocate
109 * 0 1 1 1 Normal shareable Outer and inner write
110 * back no write allocate
111 * 1 0 0 0 Normal not shareable outer and inner
112 * noncache
113 * 1 1 0 0 Normal shareable outer and inner
114 * noncache
115 * 1 0 1 1 Normal not shareable outer and inner write
116 * back write/read acllocate
117 * 1 1 1 1 Normal shareable outer and inner write
118 * back write/read acllocate
119 * 2 x 0 0 Device not shareable
120 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
121 * policy.
122 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
123 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
124 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
125 * mpu_armv7.h.
126 */
127
128 /*
129 * Add default region to deny access to whole address space to workaround speculative prefetch.
130 * Refer to Arm errata 1013783-B for more details.
131 *
132 */
133 /* Region 0 setting: Instruction access disabled, No data access permission. */
134 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
136
137 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
138 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
140
141 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
142 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
144
145#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
146 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
147 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
148 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
149#endif
150
151 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
152 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
153 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
154
155 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
156 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
157 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
158
159 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
160 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
161 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
162
163 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
164 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
165 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
166
167 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
168 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
169 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
170
171 while ((size >> i) > 0x1U)
172 {
173 i++;
174 }
175
176 if (i != 0)
177 {
178 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
179 assert(!(nonCacheStart % size));
180 assert(size == (uint32_t)(1 << i));
181 assert(i >= 5);
182
183 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
184 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
185 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
186 }
187
188 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
189 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
190 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
191
192 /* Enable MPU */
193 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
194
195 /* Enable I cache and D cache */
196 SCB_EnableDCache();
197 SCB_EnableICache();
198}
199
200#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
201void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
202{
203 lpi2c_master_config_t lpi2cConfig = {0};
204
205 /*
206 * lpi2cConfig.debugEnable = false;
207 * lpi2cConfig.ignoreAck = false;
208 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
209 * lpi2cConfig.baudRate_Hz = 100000U;
210 * lpi2cConfig.busIdleTimeout_ns = 0;
211 * lpi2cConfig.pinLowTimeout_ns = 0;
212 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
213 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
214 */
215 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
216 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
217}
218
219status_t BOARD_LPI2C_Send(LPI2C_Type *base,
220 uint8_t deviceAddress,
221 uint32_t subAddress,
222 uint8_t subAddressSize,
223 uint8_t *txBuff,
224 uint8_t txBuffSize)
225{
226 lpi2c_master_transfer_t xfer;
227
228 xfer.flags = kLPI2C_TransferDefaultFlag;
229 xfer.slaveAddress = deviceAddress;
230 xfer.direction = kLPI2C_Write;
231 xfer.subaddress = subAddress;
232 xfer.subaddressSize = subAddressSize;
233 xfer.data = txBuff;
234 xfer.dataSize = txBuffSize;
235
236 return LPI2C_MasterTransferBlocking(base, &xfer);
237}
238
239status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
240 uint8_t deviceAddress,
241 uint32_t subAddress,
242 uint8_t subAddressSize,
243 uint8_t *rxBuff,
244 uint8_t rxBuffSize)
245{
246 lpi2c_master_transfer_t xfer;
247
248 xfer.flags = kLPI2C_TransferDefaultFlag;
249 xfer.slaveAddress = deviceAddress;
250 xfer.direction = kLPI2C_Read;
251 xfer.subaddress = subAddress;
252 xfer.subaddressSize = subAddressSize;
253 xfer.data = rxBuff;
254 xfer.dataSize = rxBuffSize;
255
256 return LPI2C_MasterTransferBlocking(base, &xfer);
257}
258
259void BOARD_Accel_I2C_Init(void)
260{
261 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
262}
263
264status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
265{
266 uint8_t data = (uint8_t)txBuff;
267
268 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
269}
270
271status_t BOARD_Accel_I2C_Receive(
272 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
273{
274 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
275}
276
277void BOARD_Codec_I2C_Init(void)
278{
279 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
280}
281
282status_t BOARD_Codec_I2C_Send(
283 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
284{
285 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
286 txBuffSize);
287}
288
289status_t BOARD_Codec_I2C_Receive(
290 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
291{
292 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
293}
294#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.h
new file mode 100644
index 000000000..cdbfd1caf
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/board.h
@@ -0,0 +1,164 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1024-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_INSTANCE 1U
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
44#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
45#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (1U)
49#define LOGIC_LED_OFF (0U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO1
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (24U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_OFF() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO5
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (0U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The board flash size */
79#define BOARD_FLASH_SIZE (0x400000U)
80
81/*! @brief The ENET PHY address. */
82#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
83
84/* USB PHY condfiguration */
85#define BOARD_USB_PHY_D_CAL (0x0CU)
86#define BOARD_USB_PHY_TXCAL45DP (0x06U)
87#define BOARD_USB_PHY_TXCAL45DM (0x06U)
88
89#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
90#define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
91#define BOARD_ARDUINO_I2C_INDEX (4)
92/*! @brief The WIFI-QCA shield pin. */
93#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
94#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
95#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 23U /*!< PIO4 pin index: 23 */
96#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_23 /*!< Pin name */
97#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
98#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
99#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
100
101#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
102#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
103#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 22U /*!< PIO1 pin index: 22 */
104#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_22 /*!< Pin name */
105#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
106#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
107#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
108
109/* Display. */
110#define BOARD_LCD_DC_GPIO GPIO1 /*! LCD data/command port */
111#define BOARD_LCD_DC_GPIO_PIN 15U /*! LCD data/command pin */
112
113/* @Brief Board Bluetooth HCI UART configuration */
114#define BOARD_BT_UART_BASEADDR LPUART3
115#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
116#define BOARD_BT_UART_IRQ LPUART3_IRQn
117#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
118
119/*! @brief board has sdcard */
120#define BOARD_HAS_SDCARD (1U)
121
122#if defined(__cplusplus)
123extern "C" {
124#endif /* __cplusplus */
125
126/*******************************************************************************
127 * API
128 ******************************************************************************/
129uint32_t BOARD_DebugConsoleSrcFreq(void);
130
131void BOARD_InitDebugConsole(void);
132void BOARD_ConfigMPU(void);
133#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
134void BOARD_InitDebugConsole(void);
135void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
136status_t BOARD_LPI2C_Send(LPI2C_Type *base,
137 uint8_t deviceAddress,
138 uint32_t subAddress,
139 uint8_t subaddressSize,
140 uint8_t *txBuff,
141 uint8_t txBuffSize);
142status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
143 uint8_t deviceAddress,
144 uint32_t subAddress,
145 uint8_t subaddressSize,
146 uint8_t *rxBuff,
147 uint8_t rxBuffSize);
148void BOARD_Accel_I2C_Init(void);
149status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
150status_t BOARD_Accel_I2C_Receive(
151 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
152void BOARD_Codec_I2C_Init(void);
153status_t BOARD_Codec_I2C_Send(
154 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
155status_t BOARD_Codec_I2C_Receive(
156 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
157#endif /* SDK_I2C_BASED_COMPONENT_USED */
158void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
159void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
160#if defined(__cplusplus)
161}
162#endif /* __cplusplus */
163
164#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.c
new file mode 100644
index 000000000..e5188c752
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.c
@@ -0,0 +1,422 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7/*
8 * How to setup clock using clock driver functions:
9 *
10 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
11 *
12 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
13 *
14 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
15 *
16 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
17 *
18 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
19 *
20 */
21
22/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
23!!GlobalInfo
24product: Clocks v7.0
25processor: MIMXRT1024xxxxx
26package_id: MIMXRT1024DAG5A
27mcu_data: ksdk2_0
28processor_version: 0.7.1
29board: MIMXRT1024-EVK
30 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
31
32#include "clock_config.h"
33#include "fsl_iomuxc.h"
34
35/*******************************************************************************
36 * Definitions
37 ******************************************************************************/
38
39/*******************************************************************************
40 * Variables
41 ******************************************************************************/
42/* System clock frequency. */
43extern uint32_t SystemCoreClock;
44
45/*******************************************************************************
46 ************************ BOARD_InitBootClocks function ************************
47 ******************************************************************************/
48void BOARD_InitBootClocks(void)
49{
50 BOARD_BootClockRUN();
51}
52
53/*******************************************************************************
54 ********************** Configuration BOARD_BootClockRUN ***********************
55 ******************************************************************************/
56/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
57!!Configuration
58name: BOARD_BootClockRUN
59called_from_default_init: true
60outputs:
61- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
62- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
63- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
64- {id: CLK_1M.outFreq, value: 1 MHz}
65- {id: CLK_24M.outFreq, value: 24 MHz}
66- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
67- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
68- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
69- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
72- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
73- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
74- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
75- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
76- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
77- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
80- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
81- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
83- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
84- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
86- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
87- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
88- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
89- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
90- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
91- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
92settings:
93- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
94- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
95- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
96- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
97- {id: CCM.IPG_PODF.scale, value: '4'}
98- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
99- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
100- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
101- {id: CCM.SEMC_PODF.scale, value: '8'}
102- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
103- {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
104- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
105- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
106- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
107- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
108- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
109- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
110- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
111- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
112- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
113- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
115- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
116- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
117- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
118- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
119- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
120- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
121- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
122- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
123- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
124- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
125- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
129- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
130- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
131- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
132sources:
133- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
134 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
135
136/*******************************************************************************
137 * Variables for BOARD_BootClockRUN configuration
138 ******************************************************************************/
139const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
140 {
141 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
142 .numerator = 0, /* 30 bit numerator of fractional loop divider */
143 .denominator = 1, /* 30 bit denominator of fractional loop divider */
144 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145 };
146const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
147 {
148 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
149 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
150 };
151const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
152 {
153 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
154 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
155 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
156 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
157 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
158 };
159/*******************************************************************************
160 * Code for BOARD_BootClockRUN configuration
161 ******************************************************************************/
162void BOARD_BootClockRUN(void)
163{
164 /* Init RTC OSC clock frequency. */
165 CLOCK_SetRtcXtalFreq(32768U);
166 /* Enable 1MHz clock output. */
167 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
168 /* Use free 1MHz clock output. */
169 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
170 /* Set XTAL 24MHz clock frequency. */
171 CLOCK_SetXtalFreq(24000000U);
172 /* Enable XTAL 24MHz clock source. */
173 CLOCK_InitExternalClk(0);
174 /* Enable internal RC. */
175 CLOCK_InitRcOsc24M();
176 /* Switch clock source to external OSC. */
177 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
178 /* Set Oscillator ready counter value. */
179 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
180 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
181 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
182 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
183 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
184 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
185 /* Waiting for DCDC_STS_DC_OK bit is asserted */
186 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
187 {
188 }
189 /* Set AHB_PODF. */
190 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
191 /* Disable IPG clock gate. */
192 CLOCK_DisableClock(kCLOCK_Adc1);
193 CLOCK_DisableClock(kCLOCK_Adc2);
194 CLOCK_DisableClock(kCLOCK_Xbar1);
195 CLOCK_DisableClock(kCLOCK_Xbar2);
196 /* Set IPG_PODF. */
197 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
198 /* Set ARM_PODF. */
199 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
200 /* Set PERIPH_CLK2_PODF. */
201 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
202 /* Disable PERCLK clock gate. */
203 CLOCK_DisableClock(kCLOCK_Gpt1);
204 CLOCK_DisableClock(kCLOCK_Gpt1S);
205 CLOCK_DisableClock(kCLOCK_Gpt2);
206 CLOCK_DisableClock(kCLOCK_Gpt2S);
207 CLOCK_DisableClock(kCLOCK_Pit);
208 /* Set PERCLK_PODF. */
209 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
210 /* Disable USDHC1 clock gate. */
211 CLOCK_DisableClock(kCLOCK_Usdhc1);
212 /* Set USDHC1_PODF. */
213 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
214 /* Set Usdhc1 clock source. */
215 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
216 /* Disable USDHC2 clock gate. */
217 CLOCK_DisableClock(kCLOCK_Usdhc2);
218 /* Set USDHC2_PODF. */
219 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
220 /* Set Usdhc2 clock source. */
221 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
222 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
223 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
224 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
225#ifndef SKIP_SYSCLK_INIT
226 /* Disable Semc clock gate. */
227 CLOCK_DisableClock(kCLOCK_Semc);
228 /* Set SEMC_PODF. */
229 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
230 /* Set Semc alt clock source. */
231 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
232 /* Set Semc clock source. */
233 CLOCK_SetMux(kCLOCK_SemcMux, 0);
234#endif
235 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
236 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
237 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
238#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
239 /* Disable Flexspi clock gate. */
240 CLOCK_DisableClock(kCLOCK_FlexSpi);
241 /* Set FLEXSPI_PODF. */
242 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
243 /* Set Flexspi clock source. */
244 CLOCK_SetMux(kCLOCK_FlexspiMux, 3);
245#endif
246 /* Disable LPSPI clock gate. */
247 CLOCK_DisableClock(kCLOCK_Lpspi1);
248 CLOCK_DisableClock(kCLOCK_Lpspi2);
249 CLOCK_DisableClock(kCLOCK_Lpspi3);
250 CLOCK_DisableClock(kCLOCK_Lpspi4);
251 /* Set LPSPI_PODF. */
252 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
253 /* Set Lpspi clock source. */
254 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
255 /* Disable TRACE clock gate. */
256 CLOCK_DisableClock(kCLOCK_Trace);
257 /* Set TRACE_PODF. */
258 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
259 /* Set Trace clock source. */
260 CLOCK_SetMux(kCLOCK_TraceMux, 0);
261 /* Disable SAI1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Sai1);
263 /* Set SAI1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
265 /* Set SAI1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
267 /* Set Sai1 clock source. */
268 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
269 /* Disable SAI2 clock gate. */
270 CLOCK_DisableClock(kCLOCK_Sai2);
271 /* Set SAI2_CLK_PRED. */
272 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
273 /* Set SAI2_CLK_PODF. */
274 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
275 /* Set Sai2 clock source. */
276 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
277 /* Disable SAI3 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai3);
279 /* Set SAI3_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
281 /* Set SAI3_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
283 /* Set Sai3 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
285 /* Disable Lpi2c clock gate. */
286 CLOCK_DisableClock(kCLOCK_Lpi2c1);
287 CLOCK_DisableClock(kCLOCK_Lpi2c2);
288 CLOCK_DisableClock(kCLOCK_Lpi2c3);
289 /* Set LPI2C_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
291 /* Set Lpi2c clock source. */
292 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
293 /* Disable CAN clock gate. */
294 CLOCK_DisableClock(kCLOCK_Can1);
295 CLOCK_DisableClock(kCLOCK_Can2);
296 CLOCK_DisableClock(kCLOCK_Can1S);
297 CLOCK_DisableClock(kCLOCK_Can2S);
298 /* Set CAN_CLK_PODF. */
299 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
300 /* Set Can clock source. */
301 CLOCK_SetMux(kCLOCK_CanMux, 2);
302 /* Disable UART clock gate. */
303 CLOCK_DisableClock(kCLOCK_Lpuart1);
304 CLOCK_DisableClock(kCLOCK_Lpuart2);
305 CLOCK_DisableClock(kCLOCK_Lpuart3);
306 CLOCK_DisableClock(kCLOCK_Lpuart4);
307 CLOCK_DisableClock(kCLOCK_Lpuart5);
308 CLOCK_DisableClock(kCLOCK_Lpuart6);
309 CLOCK_DisableClock(kCLOCK_Lpuart7);
310 CLOCK_DisableClock(kCLOCK_Lpuart8);
311 /* Set UART_CLK_PODF. */
312 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
313 /* Set Uart clock source. */
314 CLOCK_SetMux(kCLOCK_UartMux, 0);
315 /* Disable SPDIF clock gate. */
316 CLOCK_DisableClock(kCLOCK_Spdif);
317 /* Set SPDIF0_CLK_PRED. */
318 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
319 /* Set SPDIF0_CLK_PODF. */
320 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
321 /* Set Spdif clock source. */
322 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
323 /* Disable Flexio1 clock gate. */
324 CLOCK_DisableClock(kCLOCK_Flexio1);
325 /* Set FLEXIO1_CLK_PRED. */
326 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
327 /* Set FLEXIO1_CLK_PODF. */
328 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
329 /* Set Flexio1 clock source. */
330 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
331 /* Set Pll3 sw clock source. */
332 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
333 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
334 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
335 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
336#ifndef SKIP_SYSCLK_INIT
337#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
338 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
339#endif
340 /* Init System PLL. */
341 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
342 /* Init System pfd0. */
343 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
344 /* Init System pfd1. */
345 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
346 /* Init System pfd2. */
347 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
348 /* Init System pfd3. */
349 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
350#endif
351 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
352 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
353 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
354#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
355 /* Init Usb1 PLL. */
356 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
357 /* Init Usb1 pfd0. */
358 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
359 /* Init Usb1 pfd1. */
360 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
361 /* Init Usb1 pfd2. */
362 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
363 /* Init Usb1 pfd3. */
364 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
365 /* Disable Usb1 PLL output for USBPHY1. */
366 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
367#endif
368 /* DeInit Audio PLL. */
369 CLOCK_DeinitAudioPll();
370 /* Bypass Audio PLL. */
371 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
372 /* Set divider for Audio PLL. */
373 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
374 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
375 /* Enable Audio PLL output. */
376 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
377 /* Init Enet PLL. */
378 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
379 /* Set preperiph clock source. */
380 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
381 /* Set periph clock source. */
382 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
383 /* Set periph clock2 clock source. */
384 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
385 /* Set per clock source. */
386 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
387 /* Set clock out1 divider. */
388 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
389 /* Set clock out1 source. */
390 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
391 /* Set clock out2 divider. */
392 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
393 /* Set clock out2 source. */
394 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
395 /* Set clock out1 drives clock out1. */
396 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
397 /* Disable clock out1. */
398 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
399 /* Disable clock out2. */
400 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
401 /* Set SAI1 MCLK1 clock source. */
402 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
403 /* Set SAI1 MCLK2 clock source. */
404 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
405 /* Set SAI1 MCLK3 clock source. */
406 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
407 /* Set SAI2 MCLK3 clock source. */
408 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
409 /* Set SAI3 MCLK3 clock source. */
410 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
411 /* Set MQS configuration. */
412 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
413 /* Set ENET Tx clock source. */
414 IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
415 /* Set GPT1 High frequency reference clock source. */
416 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
417 /* Set GPT2 High frequency reference clock source. */
418 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
419 /* Set SystemCoreClock variable. */
420 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
421}
422
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.h
new file mode 100644
index 000000000..d78780972
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/clock_config.h
@@ -0,0 +1,114 @@
1/*
2 * Copyright 2018-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7#ifndef _CLOCK_CONFIG_H_
8#define _CLOCK_CONFIG_H_
9
10#include "fsl_common.h"
11
12/*******************************************************************************
13 * Definitions
14 ******************************************************************************/
15#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
16
17#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
18/*******************************************************************************
19 ************************ BOARD_InitBootClocks function ************************
20 ******************************************************************************/
21
22#if defined(__cplusplus)
23extern "C" {
24#endif /* __cplusplus*/
25
26/*!
27 * @brief This function executes default configuration of clocks.
28 *
29 */
30void BOARD_InitBootClocks(void);
31
32#if defined(__cplusplus)
33}
34#endif /* __cplusplus*/
35
36/*******************************************************************************
37 ********************** Configuration BOARD_BootClockRUN ***********************
38 ******************************************************************************/
39/*******************************************************************************
40 * Definitions for BOARD_BootClockRUN configuration
41 ******************************************************************************/
42#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 500000000U /*!< Core clock frequency: 500000000Hz */
43
44/* Clock outputs (values are in Hz): */
45#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 500000000UL
46#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
47#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
48#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
49#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
50#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
51#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
52#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 0UL
53#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 0UL
54#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 0UL
55#define BOARD_BOOTCLOCKRUN_ENET_500M_REF_CLK 500000000UL
56#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
57#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 132000000UL
58#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 62500000UL
59#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 62500000UL
60#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 125000000UL
61#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
62#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
63#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
64#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 62500000UL
65#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
66#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
67#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
68#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
69#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
70#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
71#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
72#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
73#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
74#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
75#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
76#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
77#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 62500000UL
78#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
79#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
80#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
81#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
82#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
83#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 176000000UL
84#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 176000000UL
85
86/*! @brief Usb1 PLL set for BOARD_BootClockRUN configuration.
87 */
88extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
89/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
90 */
91extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
92/*! @brief Enet PLL set for BOARD_BootClockRUN configuration.
93 */
94extern const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN;
95
96/*******************************************************************************
97 * API for BOARD_BootClockRUN configuration
98 ******************************************************************************/
99#if defined(__cplusplus)
100extern "C" {
101#endif /* __cplusplus*/
102
103/*!
104 * @brief This function executes configuration of clocks.
105 *
106 */
107void BOARD_BootClockRUN(void);
108
109#if defined(__cplusplus)
110}
111#endif /* __cplusplus*/
112
113#endif /* _CLOCK_CONFIG_H_ */
114
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashDev.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashDev.c
new file mode 100644
index 000000000..d5f4fa7eb
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashDev.c
@@ -0,0 +1,25 @@
1/***********************************************************************/
2/* This file is part of the ARM Toolchain package */
3/* Copyright (c) 2010 Keil - An ARM Company. All rights reserved. */
4/***********************************************************************/
5/* */
6/* FlashDev.C: Device Description for New Device Flash */
7/* */
8/***********************************************************************/
9
10#include "FlashOS.H" // FlashOS Structures
11
12struct FlashDevice const FlashDevice = {FLASH_DRV_VERS, // Driver Version, do not modify!
13 "MIMXRT1024 4mB QuadSPI NOR Flash", // Device Name
14 EXTSPI, // Device Type
15 0x60000000, // Device Start Address
16 0x400000, // Device Size in Bytes (4mB)
17 256, // Programming Page Size
18 0, // Reserved, must be 0
19 0xFF, // Initial Content of Erased Memory
20 100, // Program Page Timeout 100 mSec
21 5000, // Erase Sector Timeout 5000 mSec
22
23 // Specify Size and Address of Sectors
24 0x1000, 0x00000000, // Sector Size 4kB (2048 Sectors)
25 SECTOR_END};
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashOS.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashOS.h
new file mode 100644
index 000000000..e596c355d
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashOS.h
@@ -0,0 +1,65 @@
1/***********************************************************************/
2/* This file is part of the ARM Toolchain package */
3/* Copyright KEIL ELEKTRONIK GmbH 2003 - 2007 */
4/***********************************************************************/
5/* */
6/* FlashOS.H: Data structures and entries */
7/* for Flash Programming Functions */
8/* */
9/***********************************************************************/
10
11#define VERS 1 // Interface Version 1.01
12
13#define UNKNOWN 0 // Unknown
14#define ONCHIP 1 // On-chip Flash Memory
15#define EXT8BIT 2 // External Flash Device on 8-bit Bus
16#define EXT16BIT 3 // External Flash Device on 16-bit Bus
17#define EXT32BIT 4 // External Flash Device on 32-bit Bus
18#define EXTSPI 5 // External Flash Device on SPI
19
20#define SECTOR_NUM 512 // Max Number of Sector Items
21#define PAGE_MAX 65536 // Max Page Size for Programming
22
23struct FlashSectors
24{
25 unsigned long szSector; // Sector Size in Bytes
26 unsigned long AddrSector; // Address of Sector
27};
28
29#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF
30
31struct FlashDevice
32{
33 unsigned short Vers; // Version Number and Architecture
34 char DevName[128]; // Device Name and Description
35 unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ...
36 unsigned long DevAdr; // Default Device Start Address
37 unsigned long szDev; // Total Size of Device
38 unsigned long szPage; // Programming Page Size
39 unsigned long Res; // Reserved for future Extension
40 unsigned char valEmpty; // Content of Erased Memory
41
42 unsigned long toProg; // Time Out of Program Page Function
43 unsigned long toErase; // Time Out of Erase Sector Function
44
45 struct FlashSectors sectors[SECTOR_NUM];
46};
47
48#define FLASH_DRV_VERS (0x0100 + VERS) // Driver Version, do not modify!
49
50// Flash Programming Functions (Called by FlashOS)
51extern int Init(unsigned long adr, // Initialize Flash
52 unsigned long clk,
53 unsigned long fnc);
54extern int UnInit(unsigned long fnc); // De-initialize Flash
55extern int BlankCheck(unsigned long adr, // Blank Check
56 unsigned long sz,
57 unsigned char pat);
58extern int EraseChip(void); // Erase complete Device
59extern int EraseSector(unsigned long adr); // Erase Sector Function
60extern int ProgramPage(unsigned long adr, // Program Page Function
61 unsigned long sz,
62 unsigned char *buf);
63extern unsigned long Verify(unsigned long adr, // Verify Function
64 unsigned long sz,
65 unsigned char *buf);
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashPrg.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashPrg.c
new file mode 100644
index 000000000..ed334b10f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/FlashPrg.c
@@ -0,0 +1,197 @@
1/***********************************************************************/
2/* This file is part of the ARM Toolchain package */
3/* Copyright (c) 2010 Keil - An ARM Company. All rights reserved. */
4/***********************************************************************/
5/* */
6/* FlashDev.C: Flash Programming Functions adapted */
7/* for New Device 256kB Flash */
8/* */
9/***********************************************************************/
10
11#include "FlashOS.H" // FlashOS Structures
12#include "fsl_romapi.h"
13
14#define FLEXSPI_NOR_INSTANCE 0
15#define SECTOR_SIZE (4096)
16#define BASE_ADDRESS (0x60000000)
17
18/* Init this global variable to workaround of the issue to running this flash algo in Segger */
19flexspi_nor_config_t config = {1};
20
21/*
22 * Initialize Flash Programming Functions
23 * Parameter: adr: Device Base Address
24 * clk: Clock Frequency (Hz)
25 * fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
26 * Return Value: 0 - OK, 1 - Failed
27 */
28
29/*${macro:start}*/
30#define FlexSpiInstance 0U
31#define EXAMPLE_FLEXSPI_AMBA_BASE FlexSPI_AMBA_BASE
32#define FLASH_SIZE 0x400000UL /* 4Mb */
33#define FLASH_PAGE_SIZE 256UL /* 256Bytes */
34#define FLASH_SECTOR_SIZE 0x1000UL /* 4KBytes */
35#define FLASH_BLOCK_SIZE 0x10000UL /* 64KBytes */
36/*${macro:end}*/
37
38void flexspi_nor_get_config(flexspi_nor_config_t *config)
39{
40 config->memConfig.tag = FLEXSPI_CFG_BLK_TAG;
41 config->memConfig.version = FLEXSPI_CFG_BLK_VERSION;
42 config->memConfig.readSampleClkSrc = kFLEXSPIReadSampleClk_LoopbackFromDqsPad;
43 config->memConfig.serialClkFreq =
44 kFLEXSPISerialClk_133MHz; /* Serial Flash Frequencey.See System Boot Chapter for more details */
45 config->memConfig.sflashA1Size = FLASH_SIZE;
46 config->memConfig.csHoldTime = 3U; /* Data hold time, default value: 3 */
47 config->memConfig.csSetupTime = 3U; /* Date setup time, default value: 3 */
48 config->memConfig.deviceType = kFLEXSPIDeviceType_SerialNOR; /* Flash device type default type: Serial NOR */
49 config->memConfig.deviceModeType = kDeviceConfigCmdType_Generic;
50 config->memConfig.columnAddressWidth = 0U;
51 config->memConfig.deviceModeCfgEnable = 0U;
52 config->memConfig.waitTimeCfgCommands = 0U;
53 config->memConfig.configCmdEnable = 0U;
54 /* Always enable Safe configuration Frequency */
55 config->memConfig.controllerMiscOption = FSL_ROM_FLEXSPI_BITMASK(kFLEXSPIMiscOffset_SafeConfigFreqEnable);
56 config->memConfig.sflashPadType = kSerialFlash_4Pads; /* Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
57 config->pageSize = FLASH_PAGE_SIZE;
58 config->sectorSize = FLASH_SECTOR_SIZE;
59 config->blockSize = FLASH_BLOCK_SIZE;
60 config->ipcmdSerialClkFreq = kFLEXSPISerialClk_30MHz; /* Clock frequency for IP command */
61
62 /* Fast Read Quad I/O */
63 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_READ + 0U] =
64 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xebU, RADDR_SDR, FLEXSPI_4PAD, 0x18U);
65 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_READ + 1U] =
66 FSL_ROM_FLEXSPI_LUT_SEQ(DUMMY_SDR, FLEXSPI_4PAD, 0x06U, READ_SDR, FLEXSPI_4PAD, 0x4U);
67
68 /* Read Status */
69 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_READSTATUS] =
70 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05U, READ_SDR, FLEXSPI_1PAD, 0x1U);
71
72 /* Write Enable */
73 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_WRITEENABLE] =
74 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06U, STOP, FLEXSPI_1PAD, 0x0U);
75
76 /* Page Program - quad mode */
77 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 0U] =
78 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x32U, RADDR_SDR, FLEXSPI_1PAD, 0x18U);
79 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM + 1U] =
80 FSL_ROM_FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_4PAD, 0x04U, STOP, FLEXSPI_1PAD, 0x0U);
81
82 /* Sector Erase */
83 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_ERASESECTOR] =
84 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x20U, RADDR_SDR, FLEXSPI_1PAD, 0x18U);
85
86 /* Block Erase */
87 config->memConfig.lookupTable[4U * NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK] =
88 FSL_ROM_FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD8U, RADDR_SDR, FLEXSPI_1PAD, 0x18U);
89}
90
91int Init(unsigned long adr, unsigned long clk, unsigned long fnc)
92{
93 status_t status;
94
95 WDOG1->WMCR &= ~WDOG_WMCR_PDE_MASK;
96 WDOG2->WMCR &= ~WDOG_WMCR_PDE_MASK;
97
98 /* Watchdog disable */
99
100 if (WDOG1->WCR & WDOG_WCR_WDE_MASK)
101 {
102 WDOG1->WCR &= ~WDOG_WCR_WDE_MASK;
103 }
104 if (WDOG2->WCR & WDOG_WCR_WDE_MASK)
105 {
106 WDOG2->WCR &= ~WDOG_WCR_WDE_MASK;
107 }
108 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
109 RTWDOG->TOVAL = 0xFFFF;
110 RTWDOG->CS = (uint32_t)((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
111
112 IOMUXC->SW_MUX_CTL_PAD[86] = IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(1) | IOMUXC_SW_MUX_CTL_PAD_SION(1);
113 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
114 {
115 SCB_DisableDCache();
116 }
117 memset(&config, 0U, sizeof(flexspi_nor_config_t));
118 flexspi_nor_get_config(&config);
119 status = ROM_FLEXSPI_NorFlash_Init(FLEXSPI_NOR_INSTANCE, &config);
120}
121
122/*
123 * De-Initialize Flash Programming Functions
124 * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
125 * Return Value: 0 - OK, 1 - Failed
126 */
127
128int UnInit(unsigned long fnc)
129{
130 /* Add your Code */
131 return (0); // Finished without Errors
132}
133
134/*
135 * Erase complete Flash Memory
136 * Return Value: 0 - OK, 1 - Failed
137 */
138
139int EraseChip(void)
140{
141 status_t status;
142 status = ROM_FLEXSPI_NorFlash_Erase(FLEXSPI_NOR_INSTANCE, &config, 0, FLASH_SIZE); // Erase all
143 if (status != kStatus_Success)
144 {
145 return (1);
146 }
147 else
148 {
149 return (0); // Finished without Errors
150 }
151}
152
153/*
154 * Erase Sector in Flash Memory
155 * Parameter: adr: Sector Address
156 * Return Value: 0 - OK, 1 - Failed
157 */
158
159int EraseSector(unsigned long adr)
160{
161 status_t status;
162 adr = adr - BASE_ADDRESS;
163 status = ROM_FLEXSPI_NorFlash_Erase(FLEXSPI_NOR_INSTANCE, &config, adr, SECTOR_SIZE); // Erase 1 sector
164 if (status != kStatus_Success)
165 {
166 return (1);
167 }
168 else
169 {
170 return (0);
171 }
172}
173
174/*
175 * Program Page in Flash Memory
176 * Parameter: adr: Page Start Address
177 * sz: Page Size
178 * buf: Page Data
179 * Return Value: 0 - OK, 1 - Failed
180 */
181
182int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf)
183{
184 status_t status;
185 adr = adr - BASE_ADDRESS;
186 // Program data to destination
187 status = ROM_FLEXSPI_NorFlash_ProgramPage(FLEXSPI_NOR_INSTANCE, &config, adr, (uint32_t *)buf); // program 1 page
188
189 if (status != kStatus_Success)
190 {
191 return (1);
192 }
193 else
194 {
195 return (0);
196 }
197}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QSPI.uvproj b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QSPI.uvproj
new file mode 100644
index 000000000..99a6a8088
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QSPI.uvproj
@@ -0,0 +1,476 @@
1<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
2<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_proj.xsd">
3
4 <SchemaVersion>1.1</SchemaVersion>
5
6 <Header>### uVision Project, (C) Keil Software</Header>
7
8 <Targets>
9 <Target>
10 <TargetName>RT1024</TargetName>
11 <ToolsetNumber>0x4</ToolsetNumber>
12 <ToolsetName>ARM-ADS</ToolsetName>
13 <pCCUsed>5060750::V5.06 update 6 (build 750)::.\ARMCC</pCCUsed>
14 <uAC6>0</uAC6>
15 <TargetOption>
16 <TargetCommonOption>
17 <Device>Cortex-M0</Device>
18 <Vendor>ARM</Vendor>
19 <Cpu>CLOCK(12000000) CPUTYPE("Cortex-M0")</Cpu>
20 <FlashUtilSpec></FlashUtilSpec>
21 <StartupFile></StartupFile>
22 <FlashDriverDll></FlashDriverDll>
23 <DeviceId>4803</DeviceId>
24 <RegisterFile></RegisterFile>
25 <MemoryEnv></MemoryEnv>
26 <Cmp></Cmp>
27 <Asm></Asm>
28 <Linker></Linker>
29 <OHString></OHString>
30 <InfinionOptionDll></InfinionOptionDll>
31 <SLE66CMisc></SLE66CMisc>
32 <SLE66AMisc></SLE66AMisc>
33 <SLE66LinkerMisc></SLE66LinkerMisc>
34 <SFDFile></SFDFile>
35 <bCustSvd>0</bCustSvd>
36 <UseEnv>0</UseEnv>
37 <BinPath></BinPath>
38 <IncludePath></IncludePath>
39 <LibPath></LibPath>
40 <RegisterFilePath>Philips\</RegisterFilePath>
41 <DBRegisterFilePath>Philips\</DBRegisterFilePath>
42 <TargetStatus>
43 <Error>0</Error>
44 <ExitCodeStop>0</ExitCodeStop>
45 <ButtonStop>0</ButtonStop>
46 <NotGenerated>0</NotGenerated>
47 <InvalidFlash>1</InvalidFlash>
48 </TargetStatus>
49 <OutputDirectory>.\Output\</OutputDirectory>
50 <OutputName>MIMXRT1024_QSPI</OutputName>
51 <CreateExecutable>1</CreateExecutable>
52 <CreateLib>0</CreateLib>
53 <CreateHexFile>0</CreateHexFile>
54 <DebugInformation>1</DebugInformation>
55 <BrowseInformation>1</BrowseInformation>
56 <ListingPath>.\</ListingPath>
57 <HexFormatSelection>1</HexFormatSelection>
58 <Merge32K>0</Merge32K>
59 <CreateBatchFile>0</CreateBatchFile>
60 <BeforeCompile>
61 <RunUserProg1>0</RunUserProg1>
62 <RunUserProg2>0</RunUserProg2>
63 <UserProg1Name></UserProg1Name>
64 <UserProg2Name></UserProg2Name>
65 <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
66 <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
67 <nStopU1X>0</nStopU1X>
68 <nStopU2X>0</nStopU2X>
69 </BeforeCompile>
70 <BeforeMake>
71 <RunUserProg1>0</RunUserProg1>
72 <RunUserProg2>0</RunUserProg2>
73 <UserProg1Name></UserProg1Name>
74 <UserProg2Name></UserProg2Name>
75 <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
76 <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
77 <nStopB1X>0</nStopB1X>
78 <nStopB2X>0</nStopB2X>
79 </BeforeMake>
80 <AfterMake>
81 <RunUserProg1>1</RunUserProg1>
82 <RunUserProg2>1</RunUserProg2>
83 <UserProg1Name>cmd.exe /C copy "Output\%L" "MIMXRT1024_QuadSPI_4KB_SEC.FLM"</UserProg1Name>
84 <UserProg2Name>fromelf --bincombined -o "[email protected]" "#L"</UserProg2Name>
85 <UserProg1Dos16Mode>0</UserProg1Dos16Mode>
86 <UserProg2Dos16Mode>0</UserProg2Dos16Mode>
87 <nStopA1X>0</nStopA1X>
88 <nStopA2X>0</nStopA2X>
89 </AfterMake>
90 <SelectedForBatchBuild>0</SelectedForBatchBuild>
91 <SVCSIdString></SVCSIdString>
92 </TargetCommonOption>
93 <CommonProperty>
94 <UseCPPCompiler>0</UseCPPCompiler>
95 <RVCTCodeConst>0</RVCTCodeConst>
96 <RVCTZI>0</RVCTZI>
97 <RVCTOtherData>0</RVCTOtherData>
98 <ModuleSelection>0</ModuleSelection>
99 <IncludeInBuild>1</IncludeInBuild>
100 <AlwaysBuild>0</AlwaysBuild>
101 <GenerateAssemblyFile>0</GenerateAssemblyFile>
102 <AssembleAssemblyFile>0</AssembleAssemblyFile>
103 <PublicsOnly>0</PublicsOnly>
104 <StopOnExitCode>3</StopOnExitCode>
105 <CustomArgument></CustomArgument>
106 <IncludeLibraryModules></IncludeLibraryModules>
107 <ComprImg>1</ComprImg>
108 </CommonProperty>
109 <DllOption>
110 <SimDllName>SARMCM3.DLL</SimDllName>
111 <SimDllArguments></SimDllArguments>
112 <SimDlgDll>DARMCM1.DLL</SimDlgDll>
113 <SimDlgDllArguments></SimDlgDllArguments>
114 <TargetDllName>SARMCM3.DLL</TargetDllName>
115 <TargetDllArguments></TargetDllArguments>
116 <TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
117 <TargetDlgDllArguments></TargetDlgDllArguments>
118 </DllOption>
119 <DebugOption>
120 <OPTHX>
121 <HexSelection>1</HexSelection>
122 <HexRangeLowAddress>0</HexRangeLowAddress>
123 <HexRangeHighAddress>0</HexRangeHighAddress>
124 <HexOffset>0</HexOffset>
125 <Oh166RecLen>16</Oh166RecLen>
126 </OPTHX>
127 <Simulator>
128 <UseSimulator>1</UseSimulator>
129 <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
130 <RunToMain>0</RunToMain>
131 <RestoreBreakpoints>1</RestoreBreakpoints>
132 <RestoreWatchpoints>1</RestoreWatchpoints>
133 <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
134 <RestoreFunctions>1</RestoreFunctions>
135 <RestoreToolbox>1</RestoreToolbox>
136 <LimitSpeedToRealTime>0</LimitSpeedToRealTime>
137 <RestoreSysVw>1</RestoreSysVw>
138 </Simulator>
139 <Target>
140 <UseTarget>0</UseTarget>
141 <LoadApplicationAtStartup>1</LoadApplicationAtStartup>
142 <RunToMain>0</RunToMain>
143 <RestoreBreakpoints>1</RestoreBreakpoints>
144 <RestoreWatchpoints>0</RestoreWatchpoints>
145 <RestoreMemoryDisplay>1</RestoreMemoryDisplay>
146 <RestoreFunctions>0</RestoreFunctions>
147 <RestoreToolbox>1</RestoreToolbox>
148 <RestoreTracepoints>0</RestoreTracepoints>
149 <RestoreSysVw>1</RestoreSysVw>
150 </Target>
151 <RunDebugAfterBuild>0</RunDebugAfterBuild>
152 <TargetSelection>-1</TargetSelection>
153 <SimDlls>
154 <CpuDll></CpuDll>
155 <CpuDllArguments></CpuDllArguments>
156 <PeripheralDll></PeripheralDll>
157 <PeripheralDllArguments></PeripheralDllArguments>
158 <InitializationFile></InitializationFile>
159 </SimDlls>
160 <TargetDlls>
161 <CpuDll></CpuDll>
162 <CpuDllArguments></CpuDllArguments>
163 <PeripheralDll></PeripheralDll>
164 <PeripheralDllArguments></PeripheralDllArguments>
165 <InitializationFile></InitializationFile>
166 <Driver></Driver>
167 </TargetDlls>
168 </DebugOption>
169 <Utilities>
170 <Flash1>
171 <UseTargetDll>1</UseTargetDll>
172 <UseExternalTool>0</UseExternalTool>
173 <RunIndependent>0</RunIndependent>
174 <UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
175 <Capability>1</Capability>
176 <DriverSelection>4096</DriverSelection>
177 </Flash1>
178 <bUseTDR>0</bUseTDR>
179 <Flash2>BIN\UL2ARM.DLL</Flash2>
180 <Flash3>"" ()</Flash3>
181 <Flash4></Flash4>
182 <pFcarmOut></pFcarmOut>
183 <pFcarmGrp></pFcarmGrp>
184 <pFcArmRoot></pFcArmRoot>
185 <FcArmLst>0</FcArmLst>
186 </Utilities>
187 <TargetArmAds>
188 <ArmAdsMisc>
189 <GenerateListings>0</GenerateListings>
190 <asHll>1</asHll>
191 <asAsm>1</asAsm>
192 <asMacX>1</asMacX>
193 <asSyms>1</asSyms>
194 <asFals>1</asFals>
195 <asDbgD>1</asDbgD>
196 <asForm>1</asForm>
197 <ldLst>0</ldLst>
198 <ldmm>1</ldmm>
199 <ldXref>1</ldXref>
200 <BigEnd>0</BigEnd>
201 <AdsALst>0</AdsALst>
202 <AdsACrf>1</AdsACrf>
203 <AdsANop>0</AdsANop>
204 <AdsANot>0</AdsANot>
205 <AdsLLst>1</AdsLLst>
206 <AdsLmap>1</AdsLmap>
207 <AdsLcgr>0</AdsLcgr>
208 <AdsLsym>1</AdsLsym>
209 <AdsLszi>1</AdsLszi>
210 <AdsLtoi>1</AdsLtoi>
211 <AdsLsun>1</AdsLsun>
212 <AdsLven>1</AdsLven>
213 <AdsLsxf>0</AdsLsxf>
214 <RvctClst>0</RvctClst>
215 <GenPPlst>0</GenPPlst>
216 <AdsCpuType>"Cortex-M0"</AdsCpuType>
217 <RvctDeviceName></RvctDeviceName>
218 <mOS>0</mOS>
219 <uocRom>0</uocRom>
220 <uocRam>0</uocRam>
221 <hadIROM>0</hadIROM>
222 <hadIRAM>0</hadIRAM>
223 <hadXRAM>0</hadXRAM>
224 <uocXRam>0</uocXRam>
225 <RvdsVP>0</RvdsVP>
226 <RvdsMve>0</RvdsMve>
227 <RvdsCdeCp>0</RvdsCdeCp>
228 <hadIRAM2>0</hadIRAM2>
229 <hadIROM2>0</hadIROM2>
230 <StupSel>0</StupSel>
231 <useUlib>0</useUlib>
232 <EndSel>0</EndSel>
233 <uLtcg>0</uLtcg>
234 <nSecure>0</nSecure>
235 <RoSelD>0</RoSelD>
236 <RwSelD>5</RwSelD>
237 <CodeSel>0</CodeSel>
238 <OptFeed>0</OptFeed>
239 <NoZi1>0</NoZi1>
240 <NoZi2>0</NoZi2>
241 <NoZi3>0</NoZi3>
242 <NoZi4>0</NoZi4>
243 <NoZi5>0</NoZi5>
244 <Ro1Chk>0</Ro1Chk>
245 <Ro2Chk>0</Ro2Chk>
246 <Ro3Chk>0</Ro3Chk>
247 <Ir1Chk>0</Ir1Chk>
248 <Ir2Chk>0</Ir2Chk>
249 <Ra1Chk>0</Ra1Chk>
250 <Ra2Chk>0</Ra2Chk>
251 <Ra3Chk>0</Ra3Chk>
252 <Im1Chk>0</Im1Chk>
253 <Im2Chk>0</Im2Chk>
254 <OnChipMemories>
255 <Ocm1>
256 <Type>0</Type>
257 <StartAddress>0x0</StartAddress>
258 <Size>0x0</Size>
259 </Ocm1>
260 <Ocm2>
261 <Type>0</Type>
262 <StartAddress>0x0</StartAddress>
263 <Size>0x0</Size>
264 </Ocm2>
265 <Ocm3>
266 <Type>0</Type>
267 <StartAddress>0x0</StartAddress>
268 <Size>0x0</Size>
269 </Ocm3>
270 <Ocm4>
271 <Type>0</Type>
272 <StartAddress>0x0</StartAddress>
273 <Size>0x0</Size>
274 </Ocm4>
275 <Ocm5>
276 <Type>0</Type>
277 <StartAddress>0x0</StartAddress>
278 <Size>0x0</Size>
279 </Ocm5>
280 <Ocm6>
281 <Type>0</Type>
282 <StartAddress>0x0</StartAddress>
283 <Size>0x0</Size>
284 </Ocm6>
285 <IRAM>
286 <Type>0</Type>
287 <StartAddress>0x40000000</StartAddress>
288 <Size>0x4000</Size>
289 </IRAM>
290 <IROM>
291 <Type>1</Type>
292 <StartAddress>0x0</StartAddress>
293 <Size>0x40000</Size>
294 </IROM>
295 <XRAM>
296 <Type>0</Type>
297 <StartAddress>0x0</StartAddress>
298 <Size>0x0</Size>
299 </XRAM>
300 <OCR_RVCT1>
301 <Type>1</Type>
302 <StartAddress>0x0</StartAddress>
303 <Size>0x0</Size>
304 </OCR_RVCT1>
305 <OCR_RVCT2>
306 <Type>1</Type>
307 <StartAddress>0x0</StartAddress>
308 <Size>0x0</Size>
309 </OCR_RVCT2>
310 <OCR_RVCT3>
311 <Type>1</Type>
312 <StartAddress>0x0</StartAddress>
313 <Size>0x0</Size>
314 </OCR_RVCT3>
315 <OCR_RVCT4>
316 <Type>1</Type>
317 <StartAddress>0x0</StartAddress>
318 <Size>0x0</Size>
319 </OCR_RVCT4>
320 <OCR_RVCT5>
321 <Type>1</Type>
322 <StartAddress>0x0</StartAddress>
323 <Size>0x0</Size>
324 </OCR_RVCT5>
325 <OCR_RVCT6>
326 <Type>0</Type>
327 <StartAddress>0x0</StartAddress>
328 <Size>0x0</Size>
329 </OCR_RVCT6>
330 <OCR_RVCT7>
331 <Type>0</Type>
332 <StartAddress>0x0</StartAddress>
333 <Size>0x0</Size>
334 </OCR_RVCT7>
335 <OCR_RVCT8>
336 <Type>0</Type>
337 <StartAddress>0x0</StartAddress>
338 <Size>0x0</Size>
339 </OCR_RVCT8>
340 <OCR_RVCT9>
341 <Type>0</Type>
342 <StartAddress>0x0</StartAddress>
343 <Size>0x0</Size>
344 </OCR_RVCT9>
345 <OCR_RVCT10>
346 <Type>0</Type>
347 <StartAddress>0x0</StartAddress>
348 <Size>0x0</Size>
349 </OCR_RVCT10>
350 </OnChipMemories>
351 <RvctStartVector></RvctStartVector>
352 </ArmAdsMisc>
353 <Cads>
354 <interw>0</interw>
355 <Optim>3</Optim>
356 <oTime>0</oTime>
357 <SplitLS>0</SplitLS>
358 <OneElfS>0</OneElfS>
359 <Strict>0</Strict>
360 <EnumInt>0</EnumInt>
361 <PlainCh>0</PlainCh>
362 <Ropi>1</Ropi>
363 <Rwpi>1</Rwpi>
364 <wLevel>0</wLevel>
365 <uThumb>0</uThumb>
366 <uSurpInc>0</uSurpInc>
367 <uC99>1</uC99>
368 <uGnu>0</uGnu>
369 <useXO>0</useXO>
370 <v6Lang>1</v6Lang>
371 <v6LangP>1</v6LangP>
372 <vShortEn>1</vShortEn>
373 <vShortWch>1</vShortWch>
374 <v6Lto>0</v6Lto>
375 <v6WtE>0</v6WtE>
376 <v6Rtti>0</v6Rtti>
377 <VariousControls>
378 <MiscControls></MiscControls>
379 <Define>CPU_MIMXRT1024DAG5A</Define>
380 <Undefine></Undefine>
381 <IncludePath>..\..\..\CMSIS\Include;..\..\..\devices\MIMXRT1024;..\..\..\devices\MIMXRT1024\drivers;..\..\..\platform\drivers\common;.\Sources</IncludePath>
382 </VariousControls>
383 </Cads>
384 <Aads>
385 <interw>0</interw>
386 <Ropi>1</Ropi>
387 <Rwpi>1</Rwpi>
388 <thumb>0</thumb>
389 <SplitLS>0</SplitLS>
390 <SwStkChk>0</SwStkChk>
391 <NoWarn>0</NoWarn>
392 <uSurpInc>0</uSurpInc>
393 <useXO>0</useXO>
394 <ClangAsOpt>4</ClangAsOpt>
395 <VariousControls>
396 <MiscControls></MiscControls>
397 <Define></Define>
398 <Undefine></Undefine>
399 <IncludePath></IncludePath>
400 </VariousControls>
401 </Aads>
402 <LDads>
403 <umfTarg>0</umfTarg>
404 <Ropi>0</Ropi>
405 <Rwpi>0</Rwpi>
406 <noStLib>0</noStLib>
407 <RepFail>1</RepFail>
408 <useFile>0</useFile>
409 <TextAddressRange></TextAddressRange>
410 <DataAddressRange></DataAddressRange>
411 <pXoBase></pXoBase>
412 <ScatterFile>.\Target.lin</ScatterFile>
413 <IncludeLibs></IncludeLibs>
414 <IncludeLibsPath></IncludeLibsPath>
415 <Misc>--diag_suppress L6305</Misc>
416 <LinkerInputFile></LinkerInputFile>
417 <DisabledWarnings></DisabledWarnings>
418 </LDads>
419 </TargetArmAds>
420 </TargetOption>
421 <Groups>
422 <Group>
423 <GroupName>Program Functions</GroupName>
424 <Files>
425 <File>
426 <FileName>FlashPrg.c</FileName>
427 <FileType>1</FileType>
428 <FilePath>.\FlashPrg.c</FilePath>
429 </File>
430 </Files>
431 </Group>
432 <Group>
433 <GroupName>Device Description</GroupName>
434 <Files>
435 <File>
436 <FileName>FlashDev.c</FileName>
437 <FileType>1</FileType>
438 <FilePath>.\FlashDev.c</FilePath>
439 </File>
440 </Files>
441 </Group>
442 <Group>
443 <GroupName>Sources</GroupName>
444 <Files>
445 <File>
446 <FileName>fsl_romapi.c</FileName>
447 <FileType>1</FileType>
448 <FilePath>.\Sources\fsl_romapi.c</FilePath>
449 </File>
450 <File>
451 <FileName>fsl_romapi.h</FileName>
452 <FileType>5</FileType>
453 <FilePath>.\Sources\fsl_romapi.h</FilePath>
454 </File>
455 </Files>
456 </Group>
457 </Groups>
458 </Target>
459 </Targets>
460
461 <LayerInfo>
462 <Layers>
463 <Layer>
464 <LayName>&lt;Project Info&gt;</LayName>
465 <LayDesc></LayDesc>
466 <LayUrl></LayUrl>
467 <LayKeys></LayKeys>
468 <LayCat></LayCat>
469 <LayLic></LayLic>
470 <LayTarg>0</LayTarg>
471 <LayPrjMark>1</LayPrjMark>
472 </Layer>
473 </Layers>
474 </LayerInfo>
475
476</Project>
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QuadSPI_4KB_SEC.FLM b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QuadSPI_4KB_SEC.FLM
new file mode 100644
index 000000000..290d54dd0
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/MIMXRT1024_QuadSPI_4KB_SEC.FLM
Binary files differ
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.c
new file mode 100644
index 000000000..0507e5a8f
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.c
@@ -0,0 +1,161 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_romapi.h"
9
10/*******************************************************************************
11 * Prototypes
12 ******************************************************************************/
13
14/*!
15 * @brief Interface for the ROM FLEXSPI NOR flash driver.
16 */
17typedef struct
18{
19 uint32_t version;
20 status_t (*init)(uint32_t instance, flexspi_nor_config_t *config);
21 status_t (*program)(uint32_t instance, flexspi_nor_config_t *config, uint32_t dst_addr, const uint32_t *src);
22 uint32_t reserved0;
23 status_t (*erase)(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t lengthInBytes);
24 uint32_t reserved1;
25 void (*clear_cache)(uint32_t instance);
26 status_t (*xfer)(uint32_t instance, flexspi_xfer_t *xfer);
27 status_t (*update_lut)(uint32_t instance, uint32_t seqIndex, const uint32_t *lutBase, uint32_t seqNumber);
28 uint32_t reserved2;
29} flexspi_nor_driver_interface_t;
30
31/*!
32 * @brief Root of the bootloader api tree.
33 *
34 * An instance of this struct resides in read-only memory in the bootloader. It
35 * provides a user application access to APIs exported by the bootloader.
36 *
37 * @note The order of existing fields must not be changed.
38 */
39typedef struct
40{
41 void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing */
42 const uint32_t version; /*!< Bootloader version number */
43 const uint8_t *copyright; /*!< Bootloader Copyright */
44 const uint32_t reserved0;
45 flexspi_nor_driver_interface_t *flexSpiNorDriver; /*!< FLEXSPI NOR flash api */
46} bootloader_api_entry_t;
47
48/*******************************************************************************
49 * Variables
50 ******************************************************************************/
51
52#define g_bootloaderTree ((bootloader_api_entry_t *)*(uint32_t *)0x0020001cU)
53
54#define api_flexspi_nor_erase_sector \
55 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x0021055dU)
56#define api_flexspi_nor_erase_block \
57 ((status_t(*)(uint32_t instance, flexspi_nor_config_t * config, uint32_t address))0x002104a9U)
58/*******************************************************************************
59 * Codes
60 ******************************************************************************/
61
62/*******************************************************************************
63 * ROM FLEXSPI NOR driver
64 ******************************************************************************/
65#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
66
67/*!
68 * @brief Initialize Serial NOR devices via FLEXSPI.
69 *
70 * @param instance storge the instance of FLEXSPI.
71 * @param config A pointer to the storage for the driver runtime state.
72 */
73status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config)
74{
75 return g_bootloaderTree->flexSpiNorDriver->init(instance, config);
76}
77
78/*!
79 * @brief Program data to Serial NOR via FLEXSPI.
80 *
81 * @param instance storge the instance of FLEXSPI.
82 * @param config A pointer to the storage for the driver runtime state.
83 * @param dstAddr A pointer to the desired flash memory to be programmed.
84 * @param src A pointer to the source buffer of data that is to be programmed
85 * into the NOR flash.
86 */
87status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
88 flexspi_nor_config_t *config,
89 uint32_t dstAddr,
90 const uint32_t *src)
91{
92 return g_bootloaderTree->flexSpiNorDriver->program(instance, config, dstAddr, src);
93}
94
95/*!
96 * @brief Erase Flash Region specified by address and length.
97 *
98 * @param instance storge the index of FLEXSPI.
99 * @param config A pointer to the storage for the driver runtime state.
100 * @param start The start address of the desired NOR flash memory to be erased.
101 * @param length The length, given in bytes to be erased.
102 */
103status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length)
104{
105 return g_bootloaderTree->flexSpiNorDriver->erase(instance, config, start, length);
106}
107
108#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
109/*!
110 * @brief Erase one sector specified by address.
111 *
112 * @param instance storge the index of FLEXSPI.
113 * @param config A pointer to the storage for the driver runtime state.
114 * @param start The start address of the desired NOR flash memory to be erased.
115 */
116status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
117{
118 return api_flexspi_nor_erase_sector(instance, config, start);
119}
120#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
121
122#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
123/*!
124 * @brief Erase one block specified by address.
125 *
126 * @param instance storge the index of FLEXSPI.
127 * @param config A pointer to the storage for the driver runtime state.
128 * @param start The start address of the desired NOR flash memory to be erased.
129 */
130status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start)
131{
132 return api_flexspi_nor_erase_block(instance, config, start);
133}
134#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
135
136#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
137/*! @brief FLEXSPI command */
138status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer)
139{
140 return g_bootloaderTree->flexSpiNorDriver->xfer(instance, xfer);
141}
142#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
143
144#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
145/*! @brief Configure FLEXSPI Lookup table. */
146status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
147 uint32_t seqIndex,
148 const uint32_t *lutBase,
149 uint32_t seqNumber)
150{
151 return g_bootloaderTree->flexSpiNorDriver->update_lut(instance, seqIndex, lutBase, seqNumber);
152}
153#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
154
155/*! @brief Software reset for the FLEXSPI logic. */
156void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance)
157{
158 g_bootloaderTree->flexSpiNorDriver->clear_cache(instance);
159}
160
161#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.h
new file mode 100644
index 000000000..75650b626
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Sources/fsl_romapi.h
@@ -0,0 +1,554 @@
1/*
2 * Copyright 2017-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _FSL_ROMAPI_H_
9#define _FSL_ROMAPI_H_
10
11#include "fsl_common.h"
12
13/*!
14 * @addtogroup romapi
15 * @{
16 */
17
18/*! @brief ROMAPI version 1.1.0. */
19#define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 0U))
20/*! @brief ROM FLEXSPI NOR driver version 1.4.0. */
21#define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U))
22
23/*!
24 * @name Common ROMAPI fearures info defines
25 * @{
26 */
27/* @brief ROM has FLEXSPI NOR API. */
28#define FSL_ROM_HAS_FLEXSPINOR_API (1)
29/* @brief ROM has run bootloader API. */
30#define FSL_ROM_HAS_RUNBOOTLOADER_API (0)
31/* @brief ROM has FLEXSPI NOR get config API. */
32#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0)
33/* @brief ROM has flash init API. */
34#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1)
35/* @brief ROM has erase API. */
36#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1)
37/* @brief ROM has erase sector API. */
38#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1)
39/* @brief ROM has erase block API. */
40#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (1)
41/* @brief ROM has erase all API. */
42#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (0)
43/* @brief ROM has page program API. */
44#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1)
45/* @brief ROM has update lut API. */
46#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1)
47/* @brief ROM has FLEXSPI command API. */
48#define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1)
49
50/*@}*/
51
52#define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/
53#define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/
54
55#define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \
56 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \
57 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1))
58
59/*! @brief Generate bit mask */
60#define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset))
61
62/*! @brief FLEXSPI memory config block related defintions */
63#define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */
64#define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */
65
66#define CMD_SDR 0x01U
67#define CMD_DDR 0x21U
68#define RADDR_SDR 0x02U
69#define RADDR_DDR 0x22U
70#define CADDR_SDR 0x03U
71#define CADDR_DDR 0x23U
72#define MODE1_SDR 0x04U
73#define MODE1_DDR 0x24U
74#define MODE2_SDR 0x05U
75#define MODE2_DDR 0x25U
76#define MODE4_SDR 0x06U
77#define MODE4_DDR 0x26U
78#define MODE8_SDR 0x07U
79#define MODE8_DDR 0x27U
80#define WRITE_SDR 0x08U
81#define WRITE_DDR 0x28U
82#define READ_SDR 0x09U
83#define READ_DDR 0x29U
84#define LEARN_SDR 0x0AU
85#define LEARN_DDR 0x2AU
86#define DATSZ_SDR 0x0BU
87#define DATSZ_DDR 0x2BU
88#define DUMMY_SDR 0x0CU
89#define DUMMY_DDR 0x2CU
90#define DUMMY_RWDS_SDR 0x0DU
91#define DUMMY_RWDS_DDR 0x2DU
92#define JMP_ON_CS 0x1FU
93#define STOP 0U
94
95#define FLEXSPI_1PAD 0U
96#define FLEXSPI_2PAD 1U
97#define FLEXSPI_4PAD 2U
98#define FLEXSPI_8PAD 3U
99
100/*!
101 * NOR LUT sequence index used for default LUT assignment
102 * NOTE:
103 * The will take effect if the lut sequences are not customized.
104 */
105#define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */
106#define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */
107#define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \
108 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */
109#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */
110#define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \
111 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */
112#define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */
113#define NOR_CMD_LUT_SEQ_IDX_READID 7U
114#define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */
115#define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */
116#define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */
117#define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */
118#define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \
119 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */
120#define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \
121 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */
122
123/*!
124 * @name Support for init FLEXSPI NOR configuration
125 * @{
126 */
127/*! @brief Flash Pad Definitions */
128enum
129{
130 kSerialFlash_1Pad = 1U,
131 kSerialFlash_2Pads = 2U,
132 kSerialFlash_4Pads = 4U,
133 kSerialFlash_8Pads = 8U,
134};
135
136/*! @brief FLEXSPI clock configuration type */
137enum
138{
139 kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */
140 kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */
141};
142
143/*! @brief FLEXSPI Read Sample Clock Source definition */
144typedef enum _flexspi_read_sample_clk
145{
146 kFLEXSPIReadSampleClk_LoopbackInternally = 0U,
147 kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U,
148 kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U,
149 kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U,
150} flexspi_read_sample_clk_t;
151
152/*! @brief Flash Type Definition */
153enum
154{
155 kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */
156};
157
158/*! @brief Flash Configuration Command Type */
159enum
160{
161 kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */
162 kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */
163 kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */
164 kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */
165 kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */
166 kDeviceConfigCmdType_Reset, /*!< Reset device command */
167};
168
169/*! @brief Defintions for FLEXSPI Serial Clock Frequency */
170typedef enum _flexspi_serial_clk_freq
171{
172 kFLEXSPISerialClk_NoChange = 0U,
173 kFLEXSPISerialClk_30MHz = 1U,
174 kFLEXSPISerialClk_50MHz = 2U,
175 kFLEXSPISerialClk_60MHz = 3U,
176 kFLEXSPISerialClk_75MHz = 4U,
177 kFLEXSPISerialClk_80MHz = 5U,
178 kFLEXSPISerialClk_100MHz = 6U,
179 kFLEXSPISerialClk_133MHz = 7U,
180 kFLEXSPISerialClk_166MHz = 8U,
181 kFLEXSPISerialClk_200MHz = 9U,
182} flexspi_serial_clk_freq_t;
183
184/*! @brief Misc feature bit definitions */
185enum
186{
187 kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */
188 kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */
189 kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */
190 kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */
191 kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */
192 kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */
193 kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */
194 kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */
195};
196
197/*@}*/
198
199/*!
200 * @name FLEXSPI NOR Configuration
201 * @{
202 */
203
204/*! @brief FLEXSPI LUT Sequence structure */
205typedef struct _flexspi_lut_seq
206{
207 uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */
208 uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */
209 uint16_t reserved;
210} flexspi_lut_seq_t;
211
212typedef struct
213{
214 uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */
215 uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */
216} flexspi_dll_time_t;
217
218/*! @brief FLEXSPI Memory Configuration Block */
219typedef struct _flexspi_mem_config
220{
221 uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */
222 uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */
223 uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */
224 uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */
225 uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */
226 uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */
227 uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For
228 Serial NAND, need to refer to datasheet */
229 uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */
230 uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch,
231 Generic configuration, etc. */
232 uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for
233 DPI/QPI/OPI switch or reset command */
234 flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt
235 sequence number, [31:16] Reserved */
236 uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */
237 uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */
238 uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */
239 flexspi_lut_seq_t
240 configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */
241 uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */
242 uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */
243 uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */
244 uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more
245 details */
246 uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */
247 uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */
248 uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot
249 Chapter for more details */
250 uint8_t
251 lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot
252 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */
253 uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */
254 uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */
255 uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */
256 uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */
257 uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */
258 uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */
259 uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */
260 uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */
261 uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */
262 uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */
263 uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */
264 flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */
265 uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */
266 uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 -
267 busy flag is 0 when flash device is busy */
268 uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */
269 flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */
270 uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */
271} flexspi_mem_config_t;
272
273/*! @brief Serial NOR configuration block */
274typedef struct _flexspi_nor_config
275{
276 flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */
277 uint32_t pageSize; /*!< Page size of Serial NOR */
278 uint32_t sectorSize; /*!< Sector size of Serial NOR */
279 uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */
280 uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */
281 uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */
282 uint8_t reserved0[1]; /*!< Reserved for future use */
283 uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */
284 uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */
285 uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */
286 uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */
287 uint32_t blockSize; /*!< Block size */
288 uint32_t reserve2[11]; /*!< Reserved for future use */
289} flexspi_nor_config_t;
290
291/*@}*/
292
293/*! @brief Manufacturer ID */
294enum
295{
296 kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */
297 kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/
298 kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */
299 kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */
300};
301
302/*! @brief ROM FLEXSPI NOR flash status */
303enum _flexspi_nor_status
304{
305 kStatus_ROM_FLEXSPI_SequenceExecutionTimeout =
306 MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */
307 kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */
308 kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */
309 kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed =
310 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */
311 kStatus_ROM_FLEXSPINOR_SFDP_NotFound =
312 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */
313 kStatus_ROM_FLEXSPINOR_Flash_NotFound =
314 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */
315};
316
317typedef enum _flexspi_operation
318{
319 kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */
320 kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */
321 kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */
322 kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */
323 kFLEXSPIOperation_End = kFLEXSPIOperation_Read,
324} flexspi_operation_t;
325
326/*! @brief FLEXSPI Transfer Context */
327typedef struct _flexspi_xfer
328{
329 flexspi_operation_t operation; /*!< FLEXSPI operation */
330 uint32_t baseAddress; /*!< FLEXSPI operation base address */
331 uint32_t seqId; /*!< Sequence Id */
332 uint32_t seqNum; /*!< Sequence Number */
333 bool isParallelModeEnable; /*!< Is a parallel transfer */
334 uint32_t *txBuffer; /*!< Tx buffer */
335 uint32_t txSize; /*!< Tx size in bytes */
336 uint32_t *rxBuffer; /*!< Rx buffer */
337 uint32_t rxSize; /*!< Rx size in bytes */
338} flexspi_xfer_t;
339
340#ifdef __cplusplus
341extern "C" {
342#endif
343
344#if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI
345
346/*!
347 * @name Initialization
348 * @{
349 */
350
351/*!
352 * @brief Initialize Serial NOR devices via FLEXSPI
353 *
354 * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs.
355 *
356 * @param instance storge the instance of FLEXSPI.
357 * @param config A pointer to the storage for the driver runtime state.
358 *
359 * @retval kStatus_Success Api was executed succesfuly.
360 * @retval kStatus_InvalidArgument A invalid argument is provided.
361 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
362 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
363 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
364 */
365status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config);
366
367/*@}*/
368
369/*!
370 * @name Programming
371 * @{
372 */
373/*!
374 * @brief Program data to Serial NOR via FLEXSPI.
375 *
376 * This function programs the NOR flash memory with the dest address for a given
377 * flash area as determined by the dst address and the length.
378 *
379 * @param instance storge the instance of FLEXSPI.
380 * @param config A pointer to the storage for the driver runtime state.
381 * @param dstAddr A pointer to the desired flash memory to be programmed.
382 * NOTE:
383 * It is recommended that use page aligned access;
384 * If the dstAddr is not aligned to page,the driver automatically
385 * aligns address down with the page address.
386 * @param src A pointer to the source buffer of data that is to be programmed
387 * into the NOR flash.
388 *
389 * @retval kStatus_Success Api was executed succesfuly.
390 * @retval kStatus_InvalidArgument A invalid argument is provided.
391 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
392 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
393 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
394 */
395status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance,
396 flexspi_nor_config_t *config,
397 uint32_t dstAddr,
398 const uint32_t *src);
399
400/*@}*/
401
402/*!
403 * @name Erasing
404 * @{
405 */
406#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR
407/*!
408 * @brief Erase one sector specified by address
409 *
410 * This function erases one of NOR flash sectors based on the desired address.
411 *
412 * @param instance storge the index of FLEXSPI.
413 * @param config A pointer to the storage for the driver runtime state.
414 * @param address The start address of the desired NOR flash memory to be erased.
415 * NOTE:
416 * It is recommended that use sector-aligned access nor device;
417 * If dstAddr is not aligned with the sector,The driver automatically
418 * aligns address down with the sector address.
419 *
420 * @retval kStatus_Success Api was executed succesfuly.
421 * @retval kStatus_InvalidArgument A invalid argument is provided.
422 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
423 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
424 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
425 */
426status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address);
427#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */
428
429#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK
430/*!
431 * @brief Erase one block specified by address
432 *
433 * This function erases one block of NOR flash based on the desired address.
434 *
435 * @param instance storge the index of FLEXSPI.
436 * @param config A pointer to the storage for the driver runtime state.
437 * @param start The start address of the desired NOR flash memory to be erased.
438 * NOTE:
439 * It is recommended that use block-aligned access nor device;
440 * If dstAddr is not aligned with the block,The driver automatically
441 * aligns address down with the block address.
442 *
443 * @retval kStatus_Success Api was executed succesfuly.
444 * @retval kStatus_InvalidArgument A invalid argument is provided.
445 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
446 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
447 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
448 */
449status_t ROM_FLEXSPI_NorFlash_EraseBlock(uint32_t instance, flexspi_nor_config_t *config, uint32_t start);
450#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK */
451
452/*!
453 * @brief Erase Flash Region specified by address and length
454 *
455 * This function erases the appropriate number of flash sectors based on the
456 * desired start address and length.
457 *
458 * @param instance storge the index of FLEXSPI.
459 * @param config A pointer to the storage for the driver runtime state.
460 * @param start The start address of the desired NOR flash memory to be erased.
461 * NOTE:
462 * It is recommended that use sector-aligned access nor device;
463 * If dstAddr is not aligned with the sector,the driver automatically
464 * aligns address down with the sector address.
465 * @param length The length, given in bytes to be erased.
466 * NOTE:
467 * It is recommended that use sector-aligned access nor device;
468 * If length is not aligned with the sector,the driver automatically
469 * aligns up with the sector.
470 * @retval kStatus_Success Api was executed succesfuly.
471 * @retval kStatus_InvalidArgument A invalid argument is provided.
472 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
473 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
474 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout
475 */
476status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length);
477
478/*@}*/
479
480/*!
481 * @name Command
482 * @{
483 */
484
485#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER
486/*!
487 * @brief FLEXSPI command
488 *
489 * This function is used to perform the command write sequence to the NOR device.
490 *
491 * @param instance storge the index of FLEXSPI.
492 * @param xfer A pointer to the storage FLEXSPI Transfer Context.
493 *
494 * @retval kStatus_Success Api was executed succesfuly.
495 * @retval kStatus_InvalidArgument A invalid argument is provided.
496 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
497 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
498 */
499status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer);
500#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */
501/*@}*/
502
503/*!
504 * @name UpdateLut
505 * @{
506 */
507#if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT
508/*!
509 * @brief Configure FLEXSPI Lookup table
510 *
511 * @param instance storge the index of FLEXSPI.
512 * @param seqIndex storge the sequence Id.
513 * @param lutBase A pointer to the look-up-table for command sequences.
514 * @param seqNumber storge sequence number.
515 *
516 * @retval kStatus_Success Api was executed succesfuly.
517 * @retval kStatus_InvalidArgument A invalid argument is provided.
518 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided.
519 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout.
520 */
521status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance,
522 uint32_t seqIndex,
523 const uint32_t *lutBase,
524 uint32_t seqNumber);
525#endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */
526
527/*@}*/
528
529/*!
530 * @name ClearCache
531 * @{
532 */
533
534/*!
535 * @brief Software reset for the FLEXSPI logic.
536 *
537 * This function sets the software reset flags for both AHB and buffer domain and
538 * resets both AHB buffer and also IP FIFOs.
539 *
540 * @param instance storge the index of FLEXSPI.
541 */
542void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance);
543
544/*@}*/
545
546#endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */
547
548#ifdef __cplusplus
549}
550#endif
551
552/*! @}*/
553
554#endif /* _FSL_ROMAPI_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Target.lin b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Target.lin
new file mode 100644
index 000000000..31904693c
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/Target.lin
@@ -0,0 +1,22 @@
1; Linker Control File (scatter-loading)
2;
3
4PRG 0 PI ; Programming Functions
5{
6 PrgCode +0 ; Code
7 {
8 * (+RO)
9 }
10 PrgData +0 ; Data
11 {
12 * (+RW,+ZI)
13 }
14}
15
16DSCR +0 ; Device Description
17{
18 DevDscr +0
19 {
20 FlashDev.o
21 }
22}
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/readme.txt b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/readme.txt
new file mode 100644
index 000000000..d11069202
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/cmsis_pack_flash_algo/readme.txt
@@ -0,0 +1,5 @@
1This is the project to generate flash algorithm MIMXRT1024_QuadSPI_4KB_SEC.FLM which is integrated in NXP.MIMXRT1024_DFP.x.x.x.pack.
2User can generate his own flash algorithm and replace the one in CMSIS_PACK_INSTALL_DIR\NXP\MIMXRT1024_DFP\12.0.0\arm folder.
3
4Note:
5When opening this project, warning might be occured since this is an MDK Version 4 project. Install Legacy support is not a must option. You can just click "Cancel" to ignore it.
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.c
new file mode 100644
index 000000000..cf7491919
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.c
@@ -0,0 +1,304 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#include "dcd.h"
14
15/* Component ID definition, used by tools. */
16#ifndef FSL_COMPONENT_ID
17#define FSL_COMPONENT_ID "platform.drivers.xip_board"
18#endif
19
20#if defined(XIP_BOOT_HEADER_ENABLE) && (XIP_BOOT_HEADER_ENABLE == 1)
21#if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
22#if defined(__CC_ARM) || defined(__ARMCC_VERSION) || defined(__GNUC__)
23__attribute__((section(".boot_hdr.dcd_data"), used))
24#elif defined(__ICCARM__)
25#pragma location = ".boot_hdr.dcd_data"
26#endif
27
28/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
29!!GlobalInfo
30product: DCDx V2.0
31processor: MIMXRT1024xxxxx
32package_id: MIMXRT1024DAG5A
33mcu_data: ksdk2_0
34processor_version: 0.0.0
35output_format: c_array
36 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
37/* COMMENTS BELOW ARE USED AS SETTINGS FOR DCD DATA */
38const uint8_t dcd_data[] = {
39 /* HEADER */
40 /* Tag */
41 0xD2,
42 /* Image Length */
43 0x03, 0xE8,
44 /* Version */
45 0x41,
46
47 /* COMMANDS */
48
49 /* group: 'Imported Commands' */
50 /* #1.1-8, command header bytes for merged 'Write - value' command */
51 0xCC, 0x00, 0x44, 0x04,
52 /* #1.1, command: write_value, address: CCM_CCGR0, value: 0xFFFFFFFF, size: 4 */
53 0x40, 0x0F, 0xC0, 0x68, 0xFF, 0xFF, 0xFF, 0xFF,
54 /* #1.2, command: write_value, address: CCM_CCGR1, value: 0xFFFFFFFF, size: 4 */
55 0x40, 0x0F, 0xC0, 0x6C, 0xFF, 0xFF, 0xFF, 0xFF,
56 /* #1.3, command: write_value, address: CCM_CCGR2, value: 0xFFFFFFFF, size: 4 */
57 0x40, 0x0F, 0xC0, 0x70, 0xFF, 0xFF, 0xFF, 0xFF,
58 /* #1.4, command: write_value, address: CCM_CCGR3, value: 0xFFFFFFFF, size: 4 */
59 0x40, 0x0F, 0xC0, 0x74, 0xFF, 0xFF, 0xFF, 0xFF,
60 /* #1.5, command: write_value, address: CCM_CCGR4, value: 0xFFFFFFFF, size: 4 */
61 0x40, 0x0F, 0xC0, 0x78, 0xFF, 0xFF, 0xFF, 0xFF,
62 /* #1.6, command: write_value, address: CCM_CCGR5, value: 0xFFFFFFFF, size: 4 */
63 0x40, 0x0F, 0xC0, 0x7C, 0xFF, 0xFF, 0xFF, 0xFF,
64 /* #1.7, command: write_value, address: CCM_CCGR6, value: 0xFFFFFFFF, size: 4 */
65 0x40, 0x0F, 0xC0, 0x80, 0xFF, 0xFF, 0xFF, 0xFF,
66 /* #1.8, command: write_value, address: CCM_ANALOG_PLL_SYS, value: 0x2001, size: 4 */
67 0x40, 0x0D, 0x80, 0x30, 0x00, 0x00, 0x20, 0x01,
68 /* #2, command: write_clear_bits, address: CCM_ANALOG_PFD_528, value: 0x800000, size: 4 */
69 0xCC, 0x00, 0x0C, 0x0C, 0x40, 0x0D, 0x81, 0x00, 0x00, 0x80, 0x00, 0x00,
70 /* #3.1-98, command header bytes for merged 'Write - value' command */
71 0xCC, 0x03, 0x14, 0x04,
72 /* #3.1, command: write_value, address: CCM_CBCDR, value: 0xD8340, size: 4 */
73 0x40, 0x0F, 0xC0, 0x14, 0x00, 0x0D, 0x83, 0x40,
74 /* #3.2, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00, value: 0x00, size: 4 */
75 0x40, 0x1F, 0x80, 0x14, 0x00, 0x00, 0x00, 0x00,
76 /* #3.3, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01, value: 0x00, size: 4 */
77 0x40, 0x1F, 0x80, 0x18, 0x00, 0x00, 0x00, 0x00,
78 /* #3.4, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02, value: 0x00, size: 4 */
79 0x40, 0x1F, 0x80, 0x1C, 0x00, 0x00, 0x00, 0x00,
80 /* #3.5, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03, value: 0x00, size: 4 */
81 0x40, 0x1F, 0x80, 0x20, 0x00, 0x00, 0x00, 0x00,
82 /* #3.6, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04, value: 0x00, size: 4 */
83 0x40, 0x1F, 0x80, 0x24, 0x00, 0x00, 0x00, 0x00,
84 /* #3.7, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05, value: 0x00, size: 4 */
85 0x40, 0x1F, 0x80, 0x28, 0x00, 0x00, 0x00, 0x00,
86 /* #3.8, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06, value: 0x00, size: 4 */
87 0x40, 0x1F, 0x80, 0x2C, 0x00, 0x00, 0x00, 0x00,
88 /* #3.9, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07, value: 0x00, size: 4 */
89 0x40, 0x1F, 0x80, 0x30, 0x00, 0x00, 0x00, 0x00,
90 /* #3.10, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08, value: 0x00, size: 4 */
91 0x40, 0x1F, 0x80, 0x34, 0x00, 0x00, 0x00, 0x00,
92 /* #3.11, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09, value: 0x00, size: 4 */
93 0x40, 0x1F, 0x80, 0x38, 0x00, 0x00, 0x00, 0x00,
94 /* #3.12, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10, value: 0x00, size: 4 */
95 0x40, 0x1F, 0x80, 0x3C, 0x00, 0x00, 0x00, 0x00,
96 /* #3.13, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11, value: 0x00, size: 4 */
97 0x40, 0x1F, 0x80, 0x40, 0x00, 0x00, 0x00, 0x00,
98 /* #3.14, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12, value: 0x00, size: 4 */
99 0x40, 0x1F, 0x80, 0x44, 0x00, 0x00, 0x00, 0x00,
100 /* #3.15, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13, value: 0x00, size: 4 */
101 0x40, 0x1F, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00,
102 /* #3.16, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14, value: 0x00, size: 4 */
103 0x40, 0x1F, 0x80, 0x4C, 0x00, 0x00, 0x00, 0x00,
104 /* #3.17, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15, value: 0x00, size: 4 */
105 0x40, 0x1F, 0x80, 0x50, 0x00, 0x00, 0x00, 0x00,
106 /* #3.18, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16, value: 0x00, size: 4 */
107 0x40, 0x1F, 0x80, 0x54, 0x00, 0x00, 0x00, 0x00,
108 /* #3.19, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17, value: 0x00, size: 4 */
109 0x40, 0x1F, 0x80, 0x58, 0x00, 0x00, 0x00, 0x00,
110 /* #3.20, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18, value: 0x00, size: 4 */
111 0x40, 0x1F, 0x80, 0x5C, 0x00, 0x00, 0x00, 0x00,
112 /* #3.21, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19, value: 0x00, size: 4 */
113 0x40, 0x1F, 0x80, 0x60, 0x00, 0x00, 0x00, 0x00,
114 /* #3.22, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20, value: 0x00, size: 4 */
115 0x40, 0x1F, 0x80, 0x64, 0x00, 0x00, 0x00, 0x00,
116 /* #3.23, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21, value: 0x00, size: 4 */
117 0x40, 0x1F, 0x80, 0x68, 0x00, 0x00, 0x00, 0x00,
118 /* #3.24, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22, value: 0x00, size: 4 */
119 0x40, 0x1F, 0x80, 0x6C, 0x00, 0x00, 0x00, 0x00,
120 /* #3.25, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23, value: 0x00, size: 4 */
121 0x40, 0x1F, 0x80, 0x70, 0x00, 0x00, 0x00, 0x00,
122 /* #3.26, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24, value: 0x00, size: 4 */
123 0x40, 0x1F, 0x80, 0x74, 0x00, 0x00, 0x00, 0x00,
124 /* #3.27, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25, value: 0x00, size: 4 */
125 0x40, 0x1F, 0x80, 0x78, 0x00, 0x00, 0x00, 0x00,
126 /* #3.28, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26, value: 0x00, size: 4 */
127 0x40, 0x1F, 0x80, 0x7C, 0x00, 0x00, 0x00, 0x00,
128 /* #3.29, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27, value: 0x00, size: 4 */
129 0x40, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00,
130 /* #3.30, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28, value: 0x10, size: 4 */
131 0x40, 0x1F, 0x80, 0x84, 0x00, 0x00, 0x00, 0x10,
132 /* #3.31, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29, value: 0x00, size: 4 */
133 0x40, 0x1F, 0x80, 0x88, 0x00, 0x00, 0x00, 0x00,
134 /* #3.32, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30, value: 0x00, size: 4 */
135 0x40, 0x1F, 0x80, 0x8C, 0x00, 0x00, 0x00, 0x00,
136 /* #3.33, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31, value: 0x00, size: 4 */
137 0x40, 0x1F, 0x80, 0x90, 0x00, 0x00, 0x00, 0x00,
138 /* #3.34, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32, value: 0x00, size: 4 */
139 0x40, 0x1F, 0x80, 0x94, 0x00, 0x00, 0x00, 0x00,
140 /* #3.35, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33, value: 0x00, size: 4 */
141 0x40, 0x1F, 0x80, 0x98, 0x00, 0x00, 0x00, 0x00,
142 /* #3.36, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34, value: 0x00, size: 4 */
143 0x40, 0x1F, 0x80, 0x9C, 0x00, 0x00, 0x00, 0x00,
144 /* #3.37, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35, value: 0x00, size: 4 */
145 0x40, 0x1F, 0x80, 0xA0, 0x00, 0x00, 0x00, 0x00,
146 /* #3.38, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36, value: 0x00, size: 4 */
147 0x40, 0x1F, 0x80, 0xA4, 0x00, 0x00, 0x00, 0x00,
148 /* #3.39, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37, value: 0x00, size: 4 */
149 0x40, 0x1F, 0x80, 0xA8, 0x00, 0x00, 0x00, 0x00,
150 /* #3.40, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38, value: 0x00, size: 4 */
151 0x40, 0x1F, 0x80, 0xAC, 0x00, 0x00, 0x00, 0x00,
152 /* #3.41, command: write_value, address: IOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39, value: 0x00, size: 4 */
153 0x40, 0x1F, 0x80, 0xB0, 0x00, 0x00, 0x00, 0x00,
154 /* #3.42, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00, value: 0xE1, size: 4 */
155 0x40, 0x1F, 0x81, 0x88, 0x00, 0x00, 0x00, 0xE1,
156 /* #3.43, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01, value: 0xE1, size: 4 */
157 0x40, 0x1F, 0x81, 0x8C, 0x00, 0x00, 0x00, 0xE1,
158 /* #3.44, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02, value: 0xE1, size: 4 */
159 0x40, 0x1F, 0x81, 0x90, 0x00, 0x00, 0x00, 0xE1,
160 /* #3.45, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03, value: 0xE1, size: 4 */
161 0x40, 0x1F, 0x81, 0x94, 0x00, 0x00, 0x00, 0xE1,
162 /* #3.46, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04, value: 0xE1, size: 4 */
163 0x40, 0x1F, 0x81, 0x98, 0x00, 0x00, 0x00, 0xE1,
164 /* #3.47, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05, value: 0xE1, size: 4 */
165 0x40, 0x1F, 0x81, 0x9C, 0x00, 0x00, 0x00, 0xE1,
166 /* #3.48, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06, value: 0xE1, size: 4 */
167 0x40, 0x1F, 0x81, 0xA0, 0x00, 0x00, 0x00, 0xE1,
168 /* #3.49, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07, value: 0xE1, size: 4 */
169 0x40, 0x1F, 0x81, 0xA4, 0x00, 0x00, 0x00, 0xE1,
170 /* #3.50, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08, value: 0xE1, size: 4 */
171 0x40, 0x1F, 0x81, 0xA8, 0x00, 0x00, 0x00, 0xE1,
172 /* #3.51, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09, value: 0xE1, size: 4 */
173 0x40, 0x1F, 0x81, 0xAC, 0x00, 0x00, 0x00, 0xE1,
174 /* #3.52, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10, value: 0xE1, size: 4 */
175 0x40, 0x1F, 0x81, 0xB0, 0x00, 0x00, 0x00, 0xE1,
176 /* #3.53, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11, value: 0xE1, size: 4 */
177 0x40, 0x1F, 0x81, 0xB4, 0x00, 0x00, 0x00, 0xE1,
178 /* #3.54, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12, value: 0xE1, size: 4 */
179 0x40, 0x1F, 0x81, 0xB8, 0x00, 0x00, 0x00, 0xE1,
180 /* #3.55, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13, value: 0xE1, size: 4 */
181 0x40, 0x1F, 0x81, 0xBC, 0x00, 0x00, 0x00, 0xE1,
182 /* #3.56, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14, value: 0xE1, size: 4 */
183 0x40, 0x1F, 0x81, 0xC0, 0x00, 0x00, 0x00, 0xE1,
184 /* #3.57, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15, value: 0xE1, size: 4 */
185 0x40, 0x1F, 0x81, 0xC4, 0x00, 0x00, 0x00, 0xE1,
186 /* #3.58, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16, value: 0xE1, size: 4 */
187 0x40, 0x1F, 0x81, 0xC8, 0x00, 0x00, 0x00, 0xE1,
188 /* #3.59, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17, value: 0xE1, size: 4 */
189 0x40, 0x1F, 0x81, 0xCC, 0x00, 0x00, 0x00, 0xE1,
190 /* #3.60, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18, value: 0xE1, size: 4 */
191 0x40, 0x1F, 0x81, 0xD0, 0x00, 0x00, 0x00, 0xE1,
192 /* #3.61, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19, value: 0xE1, size: 4 */
193 0x40, 0x1F, 0x81, 0xD4, 0x00, 0x00, 0x00, 0xE1,
194 /* #3.62, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20, value: 0xE1, size: 4 */
195 0x40, 0x1F, 0x81, 0xD8, 0x00, 0x00, 0x00, 0xE1,
196 /* #3.63, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21, value: 0xE1, size: 4 */
197 0x40, 0x1F, 0x81, 0xDC, 0x00, 0x00, 0x00, 0xE1,
198 /* #3.64, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22, value: 0xE1, size: 4 */
199 0x40, 0x1F, 0x81, 0xE0, 0x00, 0x00, 0x00, 0xE1,
200 /* #3.65, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23, value: 0xE1, size: 4 */
201 0x40, 0x1F, 0x81, 0xE4, 0x00, 0x00, 0x00, 0xE1,
202 /* #3.66, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24, value: 0xE1, size: 4 */
203 0x40, 0x1F, 0x81, 0xE8, 0x00, 0x00, 0x00, 0xE1,
204 /* #3.67, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25, value: 0xE1, size: 4 */
205 0x40, 0x1F, 0x81, 0xEC, 0x00, 0x00, 0x00, 0xE1,
206 /* #3.68, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26, value: 0xE1, size: 4 */
207 0x40, 0x1F, 0x81, 0xF0, 0x00, 0x00, 0x00, 0xE1,
208 /* #3.69, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27, value: 0xE1, size: 4 */
209 0x40, 0x1F, 0x81, 0xF4, 0x00, 0x00, 0x00, 0xE1,
210 /* #3.70, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28, value: 0xE1, size: 4 */
211 0x40, 0x1F, 0x81, 0xF8, 0x00, 0x00, 0x00, 0xE1,
212 /* #3.71, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29, value: 0xE1, size: 4 */
213 0x40, 0x1F, 0x81, 0xFC, 0x00, 0x00, 0x00, 0xE1,
214 /* #3.72, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30, value: 0xE1, size: 4 */
215 0x40, 0x1F, 0x82, 0x00, 0x00, 0x00, 0x00, 0xE1,
216 /* #3.73, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31, value: 0xE1, size: 4 */
217 0x40, 0x1F, 0x82, 0x04, 0x00, 0x00, 0x00, 0xE1,
218 /* #3.74, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32, value: 0xE1, size: 4 */
219 0x40, 0x1F, 0x82, 0x08, 0x00, 0x00, 0x00, 0xE1,
220 /* #3.75, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33, value: 0xE1, size: 4 */
221 0x40, 0x1F, 0x82, 0x0C, 0x00, 0x00, 0x00, 0xE1,
222 /* #3.76, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34, value: 0xE1, size: 4 */
223 0x40, 0x1F, 0x82, 0x10, 0x00, 0x00, 0x00, 0xE1,
224 /* #3.77, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35, value: 0xE1, size: 4 */
225 0x40, 0x1F, 0x82, 0x14, 0x00, 0x00, 0x00, 0xE1,
226 /* #3.78, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36, value: 0xE1, size: 4 */
227 0x40, 0x1F, 0x82, 0x18, 0x00, 0x00, 0x00, 0xE1,
228 /* #3.79, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37, value: 0xE1, size: 4 */
229 0x40, 0x1F, 0x82, 0x1C, 0x00, 0x00, 0x00, 0xE1,
230 /* #3.80, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38, value: 0xE1, size: 4 */
231 0x40, 0x1F, 0x82, 0x20, 0x00, 0x00, 0x00, 0xE1,
232 /* #3.81, command: write_value, address: IOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39, value: 0xE1, size: 4 */
233 0x40, 0x1F, 0x82, 0x24, 0x00, 0x00, 0x00, 0xE1,
234 /* #3.82, command: write_value, address: SEMC_MCR, value: 0x10000000, size: 4 */
235 0x40, 0x2F, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00,
236 /* #3.83, command: write_value, address: SEMC_BMCR0, value: 0x81, size: 4 */
237 0x40, 0x2F, 0x00, 0x08, 0x00, 0x00, 0x00, 0x81,
238 /* #3.84, command: write_value, address: SEMC_BMCR1, value: 0x81, size: 4 */
239 0x40, 0x2F, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x81,
240 /* #3.85, command: write_value, address: SEMC_BR0, value: 0x8000001B, size: 4 */
241 0x40, 0x2F, 0x00, 0x10, 0x80, 0x00, 0x00, 0x1B,
242 /* #3.86, command: write_value, address: SEMC_BR1, value: 0x8200001B, size: 4 */
243 0x40, 0x2F, 0x00, 0x14, 0x82, 0x00, 0x00, 0x1B,
244 /* #3.87, command: write_value, address: SEMC_BR2, value: 0x8400001B, size: 4 */
245 0x40, 0x2F, 0x00, 0x18, 0x84, 0x00, 0x00, 0x1B,
246 /* #3.88, command: write_value, address: SEMC_IOCR, value: 0x7988, size: 4 */
247 0x40, 0x2F, 0x00, 0x04, 0x00, 0x00, 0x79, 0x88,
248 /* #3.89, command: write_value, address: SEMC_SDRAMCR0, value: 0xF37, size: 4 */
249 0x40, 0x2F, 0x00, 0x40, 0x00, 0x00, 0x0F, 0x37,
250 /* #3.90, command: write_value, address: SEMC_SDRAMCR1, value: 0x652922, size: 4 */
251 0x40, 0x2F, 0x00, 0x44, 0x00, 0x65, 0x29, 0x22,
252 /* #3.91, command: write_value, address: SEMC_SDRAMCR2, value: 0x10920, size: 4 */
253 0x40, 0x2F, 0x00, 0x48, 0x00, 0x01, 0x09, 0x20,
254 /* #3.92, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A08, size: 4 */
255 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x08,
256 /* #3.93, command: write_value, address: SEMC_DBICR0, value: 0x21, size: 4 */
257 0x40, 0x2F, 0x00, 0x80, 0x00, 0x00, 0x00, 0x21,
258 /* #3.94, command: write_value, address: SEMC_DBICR1, value: 0x888888, size: 4 */
259 0x40, 0x2F, 0x00, 0x84, 0x00, 0x88, 0x88, 0x88,
260 /* #3.95, command: write_value, address: SEMC_IPCR1, value: 0x02, size: 4 */
261 0x40, 0x2F, 0x00, 0x94, 0x00, 0x00, 0x00, 0x02,
262 /* #3.96, command: write_value, address: SEMC_IPCR2, value: 0x00, size: 4 */
263 0x40, 0x2F, 0x00, 0x98, 0x00, 0x00, 0x00, 0x00,
264 /* #3.97, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
265 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
266 /* #3.98, command: write_value, address: SEMC_IPCMD, value: 0xA55A000F, size: 4 */
267 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0F,
268 /* #4, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
269 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
270 /* #5.1-2, command header bytes for merged 'Write - value' command */
271 0xCC, 0x00, 0x14, 0x04,
272 /* #5.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
273 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
274 /* #5.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
275 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
276 /* #6, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
277 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
278 /* #7.1-2, command header bytes for merged 'Write - value' command */
279 0xCC, 0x00, 0x14, 0x04,
280 /* #7.1, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
281 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
282 /* #7.2, command: write_value, address: SEMC_IPCMD, value: 0xA55A000C, size: 4 */
283 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0C,
284 /* #8, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
285 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
286 /* #9.1-3, command header bytes for merged 'Write - value' command */
287 0xCC, 0x00, 0x1C, 0x04,
288 /* #9.1, command: write_value, address: SEMC_IPTXDAT, value: 0x33, size: 4 */
289 0x40, 0x2F, 0x00, 0xA0, 0x00, 0x00, 0x00, 0x33,
290 /* #9.2, command: write_value, address: SEMC_IPCR0, value: 0x80000000, size: 4 */
291 0x40, 0x2F, 0x00, 0x90, 0x80, 0x00, 0x00, 0x00,
292 /* #9.3, command: write_value, address: SEMC_IPCMD, value: 0xA55A000A, size: 4 */
293 0x40, 0x2F, 0x00, 0x9C, 0xA5, 0x5A, 0x00, 0x0A,
294 /* #10, command: check_any_bit_set, address: SEMC_INTR, value: 0x01, size: 4 */
295 0xCF, 0x00, 0x0C, 0x1C, 0x40, 0x2F, 0x00, 0x3C, 0x00, 0x00, 0x00, 0x01,
296 /* #11, command: write_value, address: SEMC_SDRAMCR3, value: 0x50210A09, size: 4 */
297 0xCC, 0x00, 0x0C, 0x04, 0x40, 0x2F, 0x00, 0x4C, 0x50, 0x21, 0x0A, 0x09
298 };
299/* BE CAREFUL MODIFYING THIS SETTINGS - IT IS YAML SETTINGS FOR TOOLS */
300
301#else
302const uint8_t dcd_data[] = {0x00};
303#endif /* XIP_BOOT_HEADER_DCD_ENABLE */
304#endif /* XIP_BOOT_HEADER_ENABLE */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.h
new file mode 100644
index 000000000..185b0ecd8
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/dcd.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12
13#ifndef __DCD__
14#define __DCD__
15
16#include <stdint.h>
17
18/*! @name Driver version */
19/*@{*/
20/*! @brief XIP_BOARD driver version 2.0.1. */
21#define FSL_XIP_BOARD_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
22/*@}*/
23
24/*************************************
25 * DCD Data
26 *************************************/
27#define DCD_TAG_HEADER (0xD2)
28#define DCD_VERSION (0x41)
29#define DCD_TAG_HEADER_SHIFT (24)
30#define DCD_ARRAY_SIZE 1
31
32#endif /* __DCD__ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.c
new file mode 100644
index 000000000..8ff218b60
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.c
@@ -0,0 +1,294 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#include "fsl_common.h"
9#include "fsl_debug_console.h"
10#include "board.h"
11#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
12#include "fsl_lpi2c.h"
13#endif /* SDK_I2C_BASED_COMPONENT_USED */
14#include "fsl_iomuxc.h"
15
16/*******************************************************************************
17 * Variables
18 ******************************************************************************/
19
20/*******************************************************************************
21 * Code
22 ******************************************************************************/
23
24/* Get debug console frequency. */
25uint32_t BOARD_DebugConsoleSrcFreq(void)
26{
27 uint32_t freq;
28
29 /* To make it simple, we assume default PLL and divider settings, and the only variable
30 from application is use PLL3 source or OSC source */
31 if (CLOCK_GetMux(kCLOCK_UartMux) == 0) /* PLL3 div6 80M */
32 {
33 freq = (CLOCK_GetPllFreq(kCLOCK_PllUsb1) / 6U) / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
34 }
35 else
36 {
37 freq = CLOCK_GetOscFreq() / (CLOCK_GetDiv(kCLOCK_UartDiv) + 1U);
38 }
39
40 return freq;
41}
42
43/* Initialize debug console. */
44void BOARD_InitDebugConsole(void)
45{
46 uint32_t uartClkSrcFreq = BOARD_DebugConsoleSrcFreq();
47
48 DbgConsole_Init(BOARD_DEBUG_UART_INSTANCE, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
49}
50
51/* MPU configuration. */
52void BOARD_ConfigMPU(void)
53{
54#if defined(__CC_ARM) || defined(__ARMCC_VERSION)
55 extern uint32_t Image$$RW_m_ncache$$Base[];
56 /* RW_m_ncache_unused is a auxiliary region which is used to get the whole size of noncache section */
57 extern uint32_t Image$$RW_m_ncache_unused$$Base[];
58 extern uint32_t Image$$RW_m_ncache_unused$$ZI$$Limit[];
59 uint32_t nonCacheStart = (uint32_t)Image$$RW_m_ncache$$Base;
60 uint32_t size = ((uint32_t)Image$$RW_m_ncache_unused$$Base == nonCacheStart) ?
61 0 :
62 ((uint32_t)Image$$RW_m_ncache_unused$$ZI$$Limit - nonCacheStart);
63#elif defined(__MCUXPRESSO)
64 extern uint32_t __base_NCACHE_REGION;
65 extern uint32_t __top_NCACHE_REGION;
66 uint32_t nonCacheStart = (uint32_t)(&__base_NCACHE_REGION);
67 uint32_t size = (uint32_t)(&__top_NCACHE_REGION) - nonCacheStart;
68#elif defined(__ICCARM__) || defined(__GNUC__)
69 extern uint32_t __NCACHE_REGION_START[];
70 extern uint32_t __NCACHE_REGION_SIZE[];
71 uint32_t nonCacheStart = (uint32_t)__NCACHE_REGION_START;
72 uint32_t size = (uint32_t)__NCACHE_REGION_SIZE;
73#endif
74 volatile uint32_t i = 0;
75
76 /* Disable I cache and D cache */
77 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
78 {
79 SCB_DisableICache();
80 }
81 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
82 {
83 SCB_DisableDCache();
84 }
85
86 /* Disable MPU */
87 ARM_MPU_Disable();
88
89 /* MPU configure:
90 * Use ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable,
91 * SubRegionDisable, Size)
92 * API in mpu_armv7.h.
93 * param DisableExec Instruction access (XN) disable bit,0=instruction fetches enabled, 1=instruction fetches
94 * disabled.
95 * param AccessPermission Data access permissions, allows you to configure read/write access for User and
96 * Privileged mode.
97 * Use MACROS defined in mpu_armv7.h:
98 * ARM_MPU_AP_NONE/ARM_MPU_AP_PRIV/ARM_MPU_AP_URO/ARM_MPU_AP_FULL/ARM_MPU_AP_PRO/ARM_MPU_AP_RO
99 * Combine TypeExtField/IsShareable/IsCacheable/IsBufferable to configure MPU memory access attributes.
100 * TypeExtField IsShareable IsCacheable IsBufferable Memory Attribtue Shareability Cache
101 * 0 x 0 0 Strongly Ordered shareable
102 * 0 x 0 1 Device shareable
103 * 0 0 1 0 Normal not shareable Outer and inner write
104 * through no write allocate
105 * 0 0 1 1 Normal not shareable Outer and inner write
106 * back no write allocate
107 * 0 1 1 0 Normal shareable Outer and inner write
108 * through no write allocate
109 * 0 1 1 1 Normal shareable Outer and inner write
110 * back no write allocate
111 * 1 0 0 0 Normal not shareable outer and inner
112 * noncache
113 * 1 1 0 0 Normal shareable outer and inner
114 * noncache
115 * 1 0 1 1 Normal not shareable outer and inner write
116 * back write/read acllocate
117 * 1 1 1 1 Normal shareable outer and inner write
118 * back write/read acllocate
119 * 2 x 0 0 Device not shareable
120 * Above are normal use settings, if your want to see more details or want to config different inner/outter cache
121 * policy.
122 * please refer to Table 4-55 /4-56 in arm cortex-M7 generic user guide <dui0646b_cortex_m7_dgug.pdf>
123 * param SubRegionDisable Sub-region disable field. 0=sub-region is enabled, 1=sub-region is disabled.
124 * param Size Region size of the region to be configured. use ARM_MPU_REGION_SIZE_xxx MACRO in
125 * mpu_armv7.h.
126 */
127
128 /*
129 * Add default region to deny access to whole address space to workaround speculative prefetch.
130 * Refer to Arm errata 1013783-B for more details.
131 *
132 */
133 /* Region 0 setting: Instruction access disabled, No data access permission. */
134 MPU->RBAR = ARM_MPU_RBAR(0, 0x00000000U);
135 MPU->RASR = ARM_MPU_RASR(1, ARM_MPU_AP_NONE, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4GB);
136
137 /* Region 1 setting: Memory with Device type, not shareable, non-cacheable. */
138 MPU->RBAR = ARM_MPU_RBAR(1, 0x80000000U);
139 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
140
141 /* Region 2 setting: Memory with Device type, not shareable, non-cacheable. */
142 MPU->RBAR = ARM_MPU_RBAR(2, 0x60000000U);
143 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_512MB);
144
145#if defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1)
146 /* Region 3 setting: Memory with Normal type, not shareable, outer/inner write back. */
147 MPU->RBAR = ARM_MPU_RBAR(3, 0x60000000U);
148 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_RO, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_4MB);
149#endif
150
151 /* Region 4 setting: Memory with Device type, not shareable, non-cacheable. */
152 MPU->RBAR = ARM_MPU_RBAR(4, 0x00000000U);
153 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_1GB);
154
155 /* Region 5 setting: Memory with Normal type, not shareable, outer/inner write back */
156 MPU->RBAR = ARM_MPU_RBAR(5, 0x00000000U);
157 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
158
159 /* Region 6 setting: Memory with Normal type, not shareable, outer/inner write back */
160 MPU->RBAR = ARM_MPU_RBAR(6, 0x20000000U);
161 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_64KB);
162
163 /* Region 7 setting: Memory with Normal type, not shareable, outer/inner write back */
164 MPU->RBAR = ARM_MPU_RBAR(7, 0x20200000U);
165 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_128KB);
166
167 /* Region 8 setting: Memory with Normal type, not shareable, outer/inner write back */
168 MPU->RBAR = ARM_MPU_RBAR(8, 0x80000000U);
169 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 0, 0, 1, 1, 0, ARM_MPU_REGION_SIZE_32MB);
170
171 while ((size >> i) > 0x1U)
172 {
173 i++;
174 }
175
176 if (i != 0)
177 {
178 /* The MPU region size should be 2^N, 5<=N<=32, region base should be multiples of size. */
179 assert(!(nonCacheStart % size));
180 assert(size == (uint32_t)(1 << i));
181 assert(i >= 5);
182
183 /* Region 9 setting: Memory with Normal type, not shareable, non-cacheable */
184 MPU->RBAR = ARM_MPU_RBAR(9, nonCacheStart);
185 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 1, 0, 0, 0, 0, i - 1);
186 }
187
188 /* Region 10 setting: Memory with Device type, not shareable, non-cacheable */
189 MPU->RBAR = ARM_MPU_RBAR(10, 0x40000000);
190 MPU->RASR = ARM_MPU_RASR(0, ARM_MPU_AP_FULL, 2, 0, 0, 0, 0, ARM_MPU_REGION_SIZE_4MB);
191
192 /* Enable MPU */
193 ARM_MPU_Enable(MPU_CTRL_PRIVDEFENA_Msk);
194
195 /* Enable I cache and D cache */
196 SCB_EnableDCache();
197 SCB_EnableICache();
198}
199
200#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
201void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz)
202{
203 lpi2c_master_config_t lpi2cConfig = {0};
204
205 /*
206 * lpi2cConfig.debugEnable = false;
207 * lpi2cConfig.ignoreAck = false;
208 * lpi2cConfig.pinConfig = kLPI2C_2PinOpenDrain;
209 * lpi2cConfig.baudRate_Hz = 100000U;
210 * lpi2cConfig.busIdleTimeout_ns = 0;
211 * lpi2cConfig.pinLowTimeout_ns = 0;
212 * lpi2cConfig.sdaGlitchFilterWidth_ns = 0;
213 * lpi2cConfig.sclGlitchFilterWidth_ns = 0;
214 */
215 LPI2C_MasterGetDefaultConfig(&lpi2cConfig);
216 LPI2C_MasterInit(base, &lpi2cConfig, clkSrc_Hz);
217}
218
219status_t BOARD_LPI2C_Send(LPI2C_Type *base,
220 uint8_t deviceAddress,
221 uint32_t subAddress,
222 uint8_t subAddressSize,
223 uint8_t *txBuff,
224 uint8_t txBuffSize)
225{
226 lpi2c_master_transfer_t xfer;
227
228 xfer.flags = kLPI2C_TransferDefaultFlag;
229 xfer.slaveAddress = deviceAddress;
230 xfer.direction = kLPI2C_Write;
231 xfer.subaddress = subAddress;
232 xfer.subaddressSize = subAddressSize;
233 xfer.data = txBuff;
234 xfer.dataSize = txBuffSize;
235
236 return LPI2C_MasterTransferBlocking(base, &xfer);
237}
238
239status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
240 uint8_t deviceAddress,
241 uint32_t subAddress,
242 uint8_t subAddressSize,
243 uint8_t *rxBuff,
244 uint8_t rxBuffSize)
245{
246 lpi2c_master_transfer_t xfer;
247
248 xfer.flags = kLPI2C_TransferDefaultFlag;
249 xfer.slaveAddress = deviceAddress;
250 xfer.direction = kLPI2C_Read;
251 xfer.subaddress = subAddress;
252 xfer.subaddressSize = subAddressSize;
253 xfer.data = rxBuff;
254 xfer.dataSize = rxBuffSize;
255
256 return LPI2C_MasterTransferBlocking(base, &xfer);
257}
258
259void BOARD_Accel_I2C_Init(void)
260{
261 BOARD_LPI2C_Init(BOARD_ACCEL_I2C_BASEADDR, BOARD_ACCEL_I2C_CLOCK_FREQ);
262}
263
264status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff)
265{
266 uint8_t data = (uint8_t)txBuff;
267
268 return BOARD_LPI2C_Send(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, &data, 1);
269}
270
271status_t BOARD_Accel_I2C_Receive(
272 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
273{
274 return BOARD_LPI2C_Receive(BOARD_ACCEL_I2C_BASEADDR, deviceAddress, subAddress, subaddressSize, rxBuff, rxBuffSize);
275}
276
277void BOARD_Codec_I2C_Init(void)
278{
279 BOARD_LPI2C_Init(BOARD_CODEC_I2C_BASEADDR, BOARD_CODEC_I2C_CLOCK_FREQ);
280}
281
282status_t BOARD_Codec_I2C_Send(
283 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize)
284{
285 return BOARD_LPI2C_Send(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, (uint8_t *)txBuff,
286 txBuffSize);
287}
288
289status_t BOARD_Codec_I2C_Receive(
290 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize)
291{
292 return BOARD_LPI2C_Receive(BOARD_CODEC_I2C_BASEADDR, deviceAddress, subAddress, subAddressSize, rxBuff, rxBuffSize);
293}
294#endif /* SDK_I2C_BASED_COMPONENT_USED */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.h b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.h
new file mode 100644
index 000000000..cdbfd1caf
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/board.h
@@ -0,0 +1,164 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8#ifndef _BOARD_H_
9#define _BOARD_H_
10
11#include "clock_config.h"
12#include "fsl_common.h"
13#include "fsl_gpio.h"
14
15/*******************************************************************************
16 * Definitions
17 ******************************************************************************/
18/*! @brief The board name */
19#define BOARD_NAME "MIMXRT1024-EVK"
20
21/* The UART to use for debug messages. */
22#define BOARD_DEBUG_UART_TYPE kSerialPort_Uart
23#define BOARD_DEBUG_UART_BASEADDR (uint32_t) LPUART1
24#define BOARD_DEBUG_UART_INSTANCE 1U
25
26#define BOARD_DEBUG_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
27
28#define BOARD_UART_IRQ LPUART1_IRQn
29#define BOARD_UART_IRQ_HANDLER LPUART1_IRQHandler
30
31#ifndef BOARD_DEBUG_UART_BAUDRATE
32#define BOARD_DEBUG_UART_BAUDRATE (115200U)
33#endif /* BOARD_DEBUG_UART_BAUDRATE */
34
35/* @Brief Board accelerator sensor configuration */
36#define BOARD_ACCEL_I2C_BASEADDR LPI2C4
37#define BOARD_ACCEL_I2C_CLOCK_SOURCE_SELECT (0U)
38#define BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER (5U)
39#define BOARD_ACCEL_I2C_CLOCK_FREQ (CLOCK_GetFreq(kCLOCK_Usb1PllClk) / 8 / (BOARD_ACCEL_I2C_CLOCK_SOURCE_DIVIDER + 1U))
40
41#define BOARD_CODEC_I2C_BASEADDR LPI2C1
42#define BOARD_CODEC_I2C_INSTANCE 1U
43#define BOARD_CODEC_I2C_CLOCK_SOURCE_SELECT (0U)
44#define BOARD_CODEC_I2C_CLOCK_SOURCE_DIVIDER (5U)
45#define BOARD_CODEC_I2C_CLOCK_FREQ (10000000U)
46
47/*! @brief The USER_LED used for board */
48#define LOGIC_LED_ON (1U)
49#define LOGIC_LED_OFF (0U)
50#ifndef BOARD_USER_LED_GPIO
51#define BOARD_USER_LED_GPIO GPIO1
52#endif
53#ifndef BOARD_USER_LED_GPIO_PIN
54#define BOARD_USER_LED_GPIO_PIN (24U)
55#endif
56
57#define USER_LED_INIT(output) \
58 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, output); \
59 BOARD_USER_LED_GPIO->GDIR |= (1U << BOARD_USER_LED_GPIO_PIN) /*!< Enable target USER_LED */
60#define USER_LED_OFF() \
61 GPIO_PortClear(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!< Turn off target USER_LED */
62#define USER_LED_ON() GPIO_PortSet(BOARD_USER_LED_GPIO, 1U << BOARD_USER_LED_GPIO_PIN) /*!<Turn on target USER_LED*/
63#define USER_LED_TOGGLE() \
64 GPIO_PinWrite(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN, \
65 0x1 ^ GPIO_PinRead(BOARD_USER_LED_GPIO, BOARD_USER_LED_GPIO_PIN)) /*!< Toggle target USER_LED */
66
67/*! @brief Define the port interrupt number for the board switches */
68#ifndef BOARD_USER_BUTTON_GPIO
69#define BOARD_USER_BUTTON_GPIO GPIO5
70#endif
71#ifndef BOARD_USER_BUTTON_GPIO_PIN
72#define BOARD_USER_BUTTON_GPIO_PIN (0U)
73#endif
74#define BOARD_USER_BUTTON_IRQ GPIO5_Combined_0_15_IRQn
75#define BOARD_USER_BUTTON_IRQ_HANDLER GPIO5_Combined_0_15_IRQHandler
76#define BOARD_USER_BUTTON_NAME "SW4"
77
78/*! @brief The board flash size */
79#define BOARD_FLASH_SIZE (0x400000U)
80
81/*! @brief The ENET PHY address. */
82#define BOARD_ENET0_PHY_ADDRESS (0x02U) /* Phy address of enet port 0. */
83
84/* USB PHY condfiguration */
85#define BOARD_USB_PHY_D_CAL (0x0CU)
86#define BOARD_USB_PHY_TXCAL45DP (0x06U)
87#define BOARD_USB_PHY_TXCAL45DM (0x06U)
88
89#define BOARD_ARDUINO_INT_IRQ (GPIO1_Combined_16_31_IRQn)
90#define BOARD_ARDUINO_I2C_IRQ (LPI2C4_IRQn)
91#define BOARD_ARDUINO_I2C_INDEX (4)
92/*! @brief The WIFI-QCA shield pin. */
93#define BOARD_INITGT202SHIELD_PWRON_GPIO GPIO1 /*!< GPIO device name: GPIO */
94#define BOARD_INITGT202SHIELD_PWRON_PORT 1U /*!< PORT device index: 1 */
95#define BOARD_INITGT202SHIELD_PWRON_GPIO_PIN 23U /*!< PIO4 pin index: 23 */
96#define BOARD_INITGT202SHIELD_PWRON_PIN_NAME GPIO1_23 /*!< Pin name */
97#define BOARD_INITGT202SHIELD_PWRON_LABEL "PWRON" /*!< Label */
98#define BOARD_INITGT202SHIELD_PWRON_NAME "PWRON" /*!< Identifier name */
99#define BOARD_INITGT202SHIELD_PWRON_DIRECTION kGPIO_DigitalOutput /*!< Direction */
100
101#define BOARD_INITGT202SHIELD_IRQ_GPIO GPIO1 /*!< GPIO device name: GPIO */
102#define BOARD_INITGT202SHIELD_IRQ_PORT 1U /*!< PORT device index: 1 */
103#define BOARD_INITGT202SHIELD_IRQ_GPIO_PIN 22U /*!< PIO1 pin index: 22 */
104#define BOARD_INITGT202SHIELD_IRQ_PIN_NAME GPIO1_22 /*!< Pin name */
105#define BOARD_INITGT202SHIELD_IRQ_LABEL "IRQ" /*!< Label */
106#define BOARD_INITGT202SHIELD_IRQ_NAME "IRQ" /*!< Identifier name */
107#define BOARD_INITGT202SHIELD_IRQ_DIRECTION kGPIO_DigitalInput /*!< Direction */
108
109/* Display. */
110#define BOARD_LCD_DC_GPIO GPIO1 /*! LCD data/command port */
111#define BOARD_LCD_DC_GPIO_PIN 15U /*! LCD data/command pin */
112
113/* @Brief Board Bluetooth HCI UART configuration */
114#define BOARD_BT_UART_BASEADDR LPUART3
115#define BOARD_BT_UART_CLK_FREQ BOARD_DebugConsoleSrcFreq()
116#define BOARD_BT_UART_IRQ LPUART3_IRQn
117#define BOARD_BT_UART_IRQ_HANDLER LPUART3_IRQHandler
118
119/*! @brief board has sdcard */
120#define BOARD_HAS_SDCARD (1U)
121
122#if defined(__cplusplus)
123extern "C" {
124#endif /* __cplusplus */
125
126/*******************************************************************************
127 * API
128 ******************************************************************************/
129uint32_t BOARD_DebugConsoleSrcFreq(void);
130
131void BOARD_InitDebugConsole(void);
132void BOARD_ConfigMPU(void);
133#if defined(SDK_I2C_BASED_COMPONENT_USED) && SDK_I2C_BASED_COMPONENT_USED
134void BOARD_InitDebugConsole(void);
135void BOARD_LPI2C_Init(LPI2C_Type *base, uint32_t clkSrc_Hz);
136status_t BOARD_LPI2C_Send(LPI2C_Type *base,
137 uint8_t deviceAddress,
138 uint32_t subAddress,
139 uint8_t subaddressSize,
140 uint8_t *txBuff,
141 uint8_t txBuffSize);
142status_t BOARD_LPI2C_Receive(LPI2C_Type *base,
143 uint8_t deviceAddress,
144 uint32_t subAddress,
145 uint8_t subaddressSize,
146 uint8_t *rxBuff,
147 uint8_t rxBuffSize);
148void BOARD_Accel_I2C_Init(void);
149status_t BOARD_Accel_I2C_Send(uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint32_t txBuff);
150status_t BOARD_Accel_I2C_Receive(
151 uint8_t deviceAddress, uint32_t subAddress, uint8_t subaddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
152void BOARD_Codec_I2C_Init(void);
153status_t BOARD_Codec_I2C_Send(
154 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, const uint8_t *txBuff, uint8_t txBuffSize);
155status_t BOARD_Codec_I2C_Receive(
156 uint8_t deviceAddress, uint32_t subAddress, uint8_t subAddressSize, uint8_t *rxBuff, uint8_t rxBuffSize);
157#endif /* SDK_I2C_BASED_COMPONENT_USED */
158void BOARD_SD_Pin_Config(uint32_t speed, uint32_t strength);
159void BOARD_MMC_Pin_Config(uint32_t speed, uint32_t strength);
160#if defined(__cplusplus)
161}
162#endif /* __cplusplus */
163
164#endif /* _BOARD_H_ */
diff --git a/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/clock_config.c b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/clock_config.c
new file mode 100644
index 000000000..337624657
--- /dev/null
+++ b/lib/chibios-contrib/ext/mcux-sdk/boards/evkmimxrt1024/project_template/clock_config.c
@@ -0,0 +1,420 @@
1/*
2 * Copyright 2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8/*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24!!GlobalInfo
25product: Clocks v5.0
26processor: MIMXRT1024xxxxx
27package_id: MIMXRT1024DAG5A
28mcu_data: ksdk2_0
29processor_version: 0.0.0
30board: MIMXRT1024-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33#include "clock_config.h"
34#include "fsl_iomuxc.h"
35
36/*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40/*******************************************************************************
41 * Variables
42 ******************************************************************************/
43/* System clock frequency. */
44extern uint32_t SystemCoreClock;
45
46/*******************************************************************************
47 ************************ BOARD_InitBootClocks function ************************
48 ******************************************************************************/
49void BOARD_InitBootClocks(void)
50{
51 BOARD_BootClockRUN();
52}
53
54/*******************************************************************************
55 ********************** Configuration BOARD_BootClockRUN ***********************
56 ******************************************************************************/
57/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
58!!Configuration
59name: BOARD_BootClockRUN
60called_from_default_init: true
61outputs:
62- {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
63- {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
64- {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
65- {id: CLK_1M.outFreq, value: 1 MHz}
66- {id: CLK_24M.outFreq, value: 24 MHz}
67- {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
68- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
69- {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
70- {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
71- {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
72- {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
73- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
74- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
75- {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
76- {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
77- {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
78- {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
79- {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
80- {id: SAI1_MCLK3.outFreq, value: 30 MHz}
81- {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
82- {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
83- {id: SAI2_MCLK3.outFreq, value: 30 MHz}
84- {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
85- {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
86- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
87- {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
88- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
89- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
90- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
91- {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
92- {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
93settings:
94- {id: CCM.AHB_PODF.scale, value: '1', locked: true}
95- {id: CCM.ARM_PODF.scale, value: '1', locked: true}
96- {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
97- {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
98- {id: CCM.IPG_PODF.scale, value: '4'}
99- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
100- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
101- {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
102- {id: CCM.SEMC_PODF.scale, value: '8'}
103- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
104- {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
105- {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
106- {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
107- {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
108- {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
109- {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
110- {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
111- {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
112- {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
113- {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
114- {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
115- {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
116- {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
117- {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
118- {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
119- {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
120- {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
121- {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
122- {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
123- {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
124- {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
125- {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
126- {id: CCM_ANALOG.PLL4.denom, value: '50'}
127- {id: CCM_ANALOG.PLL4.div, value: '47'}
128- {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
129- {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
130- {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
131- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
132sources:
133- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
134- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
135 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
136
137/*******************************************************************************
138 * Variables for BOARD_BootClockRUN configuration
139 ******************************************************************************/
140const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
141 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
142 .numerator = 0, /* 30 bit numerator of fractional loop divider */
143 .denominator = 1, /* 30 bit denominator of fractional loop divider */
144 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
145};
146const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
147 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
148 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149};
150const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN = {
151 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
152 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
153 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
154 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
155 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
156};
157/*******************************************************************************
158 * Code for BOARD_BootClockRUN configuration
159 ******************************************************************************/
160void BOARD_BootClockRUN(void)
161{
162 /* Init RTC OSC clock frequency. */
163 CLOCK_SetRtcXtalFreq(32768U);
164 /* Enable 1MHz clock output. */
165 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
166 /* Use free 1MHz clock output. */
167 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
168 /* Set XTAL 24MHz clock frequency. */
169 CLOCK_SetXtalFreq(24000000U);
170 /* Enable XTAL 24MHz clock source. */
171 CLOCK_InitExternalClk(0);
172 /* Enable internal RC. */
173 CLOCK_InitRcOsc24M();
174 /* Switch clock source to external OSC. */
175 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
176 /* Set Oscillator ready counter value. */
177 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
178 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
179 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
180 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
181 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 500Mhz. */
182 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
183 /* Waiting for DCDC_STS_DC_OK bit is asserted */
184 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
185 {
186 }
187 /* Set AHB_PODF. */
188 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
189 /* Disable IPG clock gate. */
190 CLOCK_DisableClock(kCLOCK_Adc1);
191 CLOCK_DisableClock(kCLOCK_Adc2);
192 CLOCK_DisableClock(kCLOCK_Xbar1);
193 CLOCK_DisableClock(kCLOCK_Xbar2);
194 /* Set IPG_PODF. */
195 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
196 /* Set ARM_PODF. */
197 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
198 /* Set PERIPH_CLK2_PODF. */
199 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
200 /* Disable PERCLK clock gate. */
201 CLOCK_DisableClock(kCLOCK_Gpt1);
202 CLOCK_DisableClock(kCLOCK_Gpt1S);
203 CLOCK_DisableClock(kCLOCK_Gpt2);
204 CLOCK_DisableClock(kCLOCK_Gpt2S);
205 CLOCK_DisableClock(kCLOCK_Pit);
206 /* Set PERCLK_PODF. */
207 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
208 /* Disable USDHC1 clock gate. */
209 CLOCK_DisableClock(kCLOCK_Usdhc1);
210 /* Set USDHC1_PODF. */
211 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
212 /* Set Usdhc1 clock source. */
213 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
214 /* Disable USDHC2 clock gate. */
215 CLOCK_DisableClock(kCLOCK_Usdhc2);
216 /* Set USDHC2_PODF. */
217 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
218 /* Set Usdhc2 clock source. */
219 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
220 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
221 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
222 * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
223 * well.*/
224#ifndef SKIP_SYSCLK_INIT
225 /* Disable Semc clock gate. */
226 CLOCK_DisableClock(kCLOCK_Semc);
227 /* Set SEMC_PODF. */
228 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
229 /* Set Semc alt clock source. */
230 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
231 /* Set Semc clock source. */
232 CLOCK_SetMux(kCLOCK_SemcMux, 0);
233#endif
234 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
235 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
236 * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
237 * well.*/
238#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
239 /* Disable Flexspi clock gate. */
240 CLOCK_DisableClock(kCLOCK_FlexSpi);
241 /* Set FLEXSPI_PODF. */
242 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
243 /* Set Flexspi clock source. */
244 CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
245#endif
246 /* Disable LPSPI clock gate. */
247 CLOCK_DisableClock(kCLOCK_Lpspi1);
248 CLOCK_DisableClock(kCLOCK_Lpspi2);
249 CLOCK_DisableClock(kCLOCK_Lpspi3);
250 CLOCK_DisableClock(kCLOCK_Lpspi4);
251 /* Set LPSPI_PODF. */
252 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
253 /* Set Lpspi clock source. */
254 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
255 /* Disable TRACE clock gate. */
256 CLOCK_DisableClock(kCLOCK_Trace);
257 /* Set TRACE_PODF. */
258 CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
259 /* Set Trace clock source. */
260 CLOCK_SetMux(kCLOCK_TraceMux, 2);
261 /* Disable SAI1 clock gate. */
262 CLOCK_DisableClock(kCLOCK_Sai1);
263 /* Set SAI1_CLK_PRED. */
264 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
265 /* Set SAI1_CLK_PODF. */
266 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
267 /* Set Sai1 clock source. */
268 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
269 /* Disable SAI2 clock gate. */
270 CLOCK_DisableClock(kCLOCK_Sai2);
271 /* Set SAI2_CLK_PRED. */
272 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
273 /* Set SAI2_CLK_PODF. */
274 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
275 /* Set Sai2 clock source. */
276 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
277 /* Disable SAI3 clock gate. */
278 CLOCK_DisableClock(kCLOCK_Sai3);
279 /* Set SAI3_CLK_PRED. */
280 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
281 /* Set SAI3_CLK_PODF. */
282 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
283 /* Set Sai3 clock source. */
284 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
285 /* Disable Lpi2c clock gate. */
286 CLOCK_DisableClock(kCLOCK_Lpi2c1);
287 CLOCK_DisableClock(kCLOCK_Lpi2c2);
288 CLOCK_DisableClock(kCLOCK_Lpi2c3);
289 /* Set LPI2C_CLK_PODF. */
290 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
291 /* Set Lpi2c clock source. */
292 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
293 /* Disable CAN clock gate. */
294 CLOCK_DisableClock(kCLOCK_Can1);
295 CLOCK_DisableClock(kCLOCK_Can2);
296 CLOCK_DisableClock(kCLOCK_Can1S);
297 CLOCK_DisableClock(kCLOCK_Can2S);