468 files changed, 178833 insertions, 0 deletions
diff --git a/lib/chibios/os/hal/boards/ADICUP360/board.c b/lib/chibios/os/hal/boards/ADICUP360/board.c
new file mode 100644
index 000000000..4b2fbb6df
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADICUP360/board.c
@@ -0,0 +1,154 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#include "hal.h"
+#include "aducm_gp.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of ADUCM36x GP port setup.
+ */
+typedef struct {
+  uint32_t              con;
+  uint32_t              oen;
+  uint32_t              pul;
+  uint32_t              oce;
+} gp_setup_t;
+/**
+ * @brief   Type of ADUCM36x GPIO initialization data.
+ */
+typedef struct {
+  gp_setup_t            GP0Data;
+  gp_setup_t            GP1Data;
+  gp_setup_t            GP2Data;
+} gp_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gp_config_t gp_default_config = {
+  {VAL_GP0CON, VAL_GP0OEN, VAL_GP0PUL, VAL_GP0OCE},
+  {VAL_GP1CON, VAL_GP1OEN, VAL_GP1PUL, VAL_GP1OCE},
+  {VAL_GP2CON, VAL_GP2OEN, VAL_GP2PUL, VAL_GP2OCE}
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gp_init(aducm_gp_t *gpp, const gp_setup_t *config) {
+  gpp->CON  = config->con;
+  gpp->OEN  = config->oen;
+  gpp->PUL  = config->pul;
+  gpp->OCE  = config->oce;
+}
+static void aducm_gpio_init(void) {
+  /* Initializing all the defined GP ports.*/
+  gp_init(GP0, &gp_default_config.GP0Data);
+  gp_init(GP1, &gp_default_config.GP1Data);
+  gp_init(GP2, &gp_default_config.GP2Data);
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GP ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  aducm_gpio_init();
+  aducm_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @note    You can add your board-specific code here.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios/os/hal/boards/ADICUP360/board.h b/lib/chibios/os/hal/boards/ADICUP360/board.h
new file mode 100644
index 000000000..d0a685e37
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADICUP360/board.h
@@ -0,0 +1,271 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#ifndef BOARD_H
+#define BOARD_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/*
+ * Setup for Analog Devices ADICUP360 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ADICUP360
+#define BOARD_NAME                  "Analog Devices ADICUP360"
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(ADUCM_LFXTAL)
+#define ADUCM_LFXTAL                32768U
+#endif
+/*
+ * MCU type as defined in the ADI header.
+ */
+#define ADUCM360
+/*
+ * IO pins assignments.
+ */
+#define GP0_0                       0U
+#define GP0_1                       1U
+#define GP0_2                       2U
+#define GP0_3                       3U
+#define GP0_LED_BLUE                4U
+#define GP0_LED_GREEN               5U
+#define GP0_6                       6U
+#define GP0_7                       7U
+#define GP0_NPOR                    7U
+#define GP1_0                       0U
+#define GP1_1                       1U
+#define GP1_2                       2U
+#define GP1_3                       3U
+#define GP1_4                       4U
+#define GP1_5                       5U
+#define GP1_6                       6U
+#define GP1_7                       7U
+#define GP2_0                       0U
+#define GP2_1                       1U
+#define GP2_BUTTON                  2U
+#define GP2_SWCLK                   3U
+#define GP2_SWD                     4U
+#define GP2_5                       5U
+#define GP2_6                       6U
+#define GP2_7                       7U
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED_BLUE               PAL_LINE(GP0, 4U)
+#define LINE_LED_GREEN              PAL_LINE(GP0, 5U)
+#define LINE_NPOR                   PAL_LINE(GP0, 7U)
+#define LINE_BUTTON                 PAL_LINE(GP2, 2U)
+#define LINE_SWCLK                  PAL_LINE(GP2, 3U)
+#define LINE_SWD                    PAL_LINE(GP2, 4U)
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the ADUCM360 Reference Manual for details.
+ */
+#define PIN_CON_CON(n, v)           ((v) << (n * 2U))
+#define PIN_OEN_INPUT(n)            (0U << (n))
+#define PIN_OEN_OUTPUT(n)           (1U << (n))
+#define PIN_PUL_FLOATING(n)         (0U << (n))
+#define PIN_PUL_PULLUP(n)           (1U << (n))
+#define PIN_OCE_NORMAL(n)           (0U << (n))
+#define PIN_OCE_HIGHZ(n)            (1U << (n))
+/*
+ * P0 setup:
+ *
+ * P0.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P0.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P0.2  - PIN2                     (CON0, GPIO - input pullup).
+ * P0.3  - PIN3                     (CON0, GPIO - input pullup).
+ * P0.4  - LED_BLUE                 (CON0, GPIO - output floating).
+ * P0.5  - LED_GREEN                (CON0, GPIO - output floating).
+ * P0.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P0.7  - NPOR                     (CON0, NPOR).
+ */
+#define VAL_GP0CON                  (PIN_CON_CON(GP0_0, 0) |                \
+                                     PIN_CON_CON(GP0_1, 0) |                \
+                                     PIN_CON_CON(GP0_2, 0) |                \
+                                     PIN_CON_CON(GP0_3, 0) |                \
+                                     PIN_CON_CON(GP0_LED_BLUE, 0) |         \
+                                     PIN_CON_CON(GP0_LED_GREEN, 0) |        \
+                                     PIN_CON_CON(GP0_6, 0) |                \
+                                     PIN_CON_CON(GP0_NPOR, 0))
+#define VAL_GP0OEN                  (PIN_OEN_INPUT(GP0_0) |                 \
+                                     PIN_OEN_INPUT(GP0_1) |                 \
+                                     PIN_OEN_INPUT(GP0_2) |                 \
+                                     PIN_OEN_INPUT(GP0_3) |                 \
+                                     PIN_OEN_OUTPUT(GP0_LED_BLUE) |         \
+                                     PIN_OEN_OUTPUT(GP0_LED_GREEN) |        \
+                                     PIN_OEN_INPUT(GP0_6) |                 \
+                                     PIN_OEN_INPUT(GP0_NPOR))
+#define VAL_GP0PUL                  (PIN_PUL_PULLUP(GP0_0) |                \
+                                     PIN_PUL_PULLUP(GP0_1) |                \
+                                     PIN_PUL_PULLUP(GP0_2) |                \
+                                     PIN_PUL_PULLUP(GP0_3) |                \
+                                     PIN_PUL_FLOATING(GP0_LED_BLUE) |       \
+                                     PIN_PUL_FLOATING(GP0_LED_GREEN) |      \
+                                     PIN_PUL_PULLUP(GP0_6) |                \
+                                     PIN_PUL_PULLUP(GP0_NPOR))
+#define VAL_GP0OCE                  (PIN_OCE_NORMAL(GP0_0) |                \
+                                     PIN_OCE_NORMAL(GP0_1) |                \
+                                     PIN_OCE_NORMAL(GP0_2) |                \
+                                     PIN_OCE_NORMAL(GP0_3) |                \
+                                     PIN_OCE_NORMAL(GP0_LED_BLUE) |         \
+                                     PIN_OCE_NORMAL(GP0_LED_GREEN) |        \
+                                     PIN_OCE_NORMAL(GP0_6) |                \
+                                     PIN_OCE_NORMAL(GP0_NPOR))
+/*
+ * P1 setup:
+ *
+ * P1.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P1.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P1.2  - PIN2                     (CON0, GPIO - input pullup).
+ * P1.3  - PIN3                     (CON0, GPIO - input pullup).
+ * P1.4  - PIN4                     (CON0, GPIO - input pullup).
+ * P1.5  - PIN5                     (CON0, GPIO - input pullup).
+ * P1.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P1.7  - PIN7                     (CON0, GPIO - input pullup).
+ */
+#define VAL_GP1CON                  (PIN_CON_CON(GP1_0, 0) |                \
+                                     PIN_CON_CON(GP1_1, 0) |                \
+                                     PIN_CON_CON(GP1_2, 0) |                \
+                                     PIN_CON_CON(GP1_3, 0) |                \
+                                     PIN_CON_CON(GP1_4, 0) |                \
+                                     PIN_CON_CON(GP1_5, 0) |                \
+                                     PIN_CON_CON(GP1_6, 0) |                \
+                                     PIN_CON_CON(GP1_7, 0))                                     
+#define VAL_GP1OEN                  (PIN_OEN_INPUT(GP1_0) |                 \
+                                     PIN_OEN_INPUT(GP1_1) |                 \
+                                     PIN_OEN_INPUT(GP1_2) |                 \
+                                     PIN_OEN_INPUT(GP1_3) |                 \
+                                     PIN_OEN_INPUT(GP1_4) |                 \
+                                     PIN_OEN_INPUT(GP1_5) |                 \
+                                     PIN_OEN_INPUT(GP1_6) |                 \
+                                     PIN_OEN_INPUT(GP1_7))                                     
+#define VAL_GP1PUL                  (PIN_PUL_PULLUP(GP1_0) |                \
+                                     PIN_PUL_PULLUP(GP1_1) |                \
+                                     PIN_PUL_PULLUP(GP1_2) |                \
+                                     PIN_PUL_PULLUP(GP1_3) |                \
+                                     PIN_PUL_PULLUP(GP1_4) |                \
+                                     PIN_PUL_PULLUP(GP1_5) |                \
+                                     PIN_PUL_PULLUP(GP1_6) |                \
+                                     PIN_PUL_PULLUP(GP1_7))
+#define VAL_GP1OCE                  (PIN_OCE_NORMAL(GP1_0) |                \
+                                     PIN_OCE_NORMAL(GP1_1) |                \
+                                     PIN_OCE_NORMAL(GP1_2) |                \
+                                     PIN_OCE_NORMAL(GP1_3) |                \
+                                     PIN_OCE_NORMAL(GP1_4) |                \
+                                     PIN_OCE_NORMAL(GP1_5) |                \
+                                     PIN_OCE_NORMAL(GP1_6) |                \
+                                     PIN_OCE_NORMAL(GP1_7))
+/*
+ * P2 setup:
+ *
+ * P2.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P2.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P2.2  - BUTTON                   (CON0, GPIO - input floating).
+ * P2.3  - SWCLK                    (CON0, SWCLK).
+ * P2.4  - SWD                      (CON0, SWD).
+ * P2.5  - PIN5                     (CON0, GPIO - input pullup).
+ * P2.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P2.7  - PIN7                     (CON0, GPIO - input pullup).
+ */
+#define VAL_GP2CON                  (PIN_CON_CON(GP2_0, 0) |                \
+                                     PIN_CON_CON(GP2_1, 0) |                \
+                                     PIN_CON_CON(GP2_BUTTON, 0) |           \
+                                     PIN_CON_CON(GP2_SWCLK, 0) |            \
+                                     PIN_CON_CON(GP2_SWD, 0) |              \
+                                     PIN_CON_CON(GP2_5, 0) |                \
+                                     PIN_CON_CON(GP2_6, 0) |                \
+                                     PIN_CON_CON(GP2_7, 0))
+#define VAL_GP2OEN                  (PIN_OEN_INPUT(GP2_0) |                 \
+                                     PIN_OEN_INPUT(GP2_1) |                 \
+                                     PIN_OEN_INPUT(GP2_BUTTON) |            \
+                                     PIN_OEN_INPUT(GP2_SWCLK) |             \
+                                     PIN_OEN_INPUT(GP2_SWD) |               \
+                                     PIN_OEN_INPUT(GP2_5) |                 \
+                                     PIN_OEN_INPUT(GP2_6) |                 \
+                                     PIN_OEN_INPUT(GP2_7))
+#define VAL_GP2PUL                  (PIN_PUL_PULLUP(GP2_0) |                \
+                                     PIN_PUL_PULLUP(GP2_1) |                \
+                                     PIN_PUL_FLOATING(GP2_BUTTON) |         \
+                                     PIN_PUL_PULLUP(GP2_SWCLK) |            \
+                                     PIN_PUL_PULLUP(GP2_SWD) |              \
+                                     PIN_PUL_PULLUP(GP2_5) |                \
+                                     PIN_PUL_PULLUP(GP2_6) |                \
+                                     PIN_PUL_PULLUP(GP2_7))
+#define VAL_GP2OCE                  (PIN_OCE_NORMAL(GP2_0) |                \
+                                     PIN_OCE_NORMAL(GP2_1) |                \
+                                     PIN_OCE_NORMAL(GP2_BUTTON) |           \
+                                     PIN_OCE_NORMAL(GP2_SWCLK) |            \
+                                     PIN_OCE_NORMAL(GP2_SWD) |              \
+                                     PIN_OCE_NORMAL(GP2_5) |                \
+                                     PIN_OCE_NORMAL(GP2_6) |                \
+                                     PIN_OCE_NORMAL(GP2_7))
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios/os/hal/boards/ADICUP360/board.mk b/lib/chibios/os/hal/boards/ADICUP360/board.mk
new file mode 100644
index 000000000..77933f52e
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADICUP360/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ADICUP360/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ADICUP360
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.c b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.c
new file mode 100644
index 000000000..4b2fbb6df
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.c
@@ -0,0 +1,154 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#include "hal.h"
+#include "aducm_gp.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of ADUCM36x GP port setup.
+ */
+typedef struct {
+  uint32_t              con;
+  uint32_t              oen;
+  uint32_t              pul;
+  uint32_t              oce;
+} gp_setup_t;
+/**
+ * @brief   Type of ADUCM36x GPIO initialization data.
+ */
+typedef struct {
+  gp_setup_t            GP0Data;
+  gp_setup_t            GP1Data;
+  gp_setup_t            GP2Data;
+} gp_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gp_config_t gp_default_config = {
+  {VAL_GP0CON, VAL_GP0OEN, VAL_GP0PUL, VAL_GP0OCE},
+  {VAL_GP1CON, VAL_GP1OEN, VAL_GP1PUL, VAL_GP1OCE},
+  {VAL_GP2CON, VAL_GP2OEN, VAL_GP2PUL, VAL_GP2OCE}
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gp_init(aducm_gp_t *gpp, const gp_setup_t *config) {
+  gpp->CON  = config->con;
+  gpp->OEN  = config->oen;
+  gpp->PUL  = config->pul;
+  gpp->OCE  = config->oce;
+}
+static void aducm_gpio_init(void) {
+  /* Initializing all the defined GP ports.*/
+  gp_init(GP0, &gp_default_config.GP0Data);
+  gp_init(GP1, &gp_default_config.GP1Data);
+  gp_init(GP2, &gp_default_config.GP2Data);
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GP ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  aducm_gpio_init();
+  aducm_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @note    You can add your board-specific code here.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.h b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.h
new file mode 100644
index 000000000..9ffc74f85
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.h
@@ -0,0 +1,271 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#ifndef BOARD_H
+#define BOARD_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/*
+ * Setup for Analgo Devices EVAL-ADuCM410EBZ board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_EV_ADUCM410QSPZ_U1
+#define BOARD_NAME                  "Analog Devices EVAL-ADuCM410EBZ"
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(ADUCM_EXTCLK)
+#define ADUCM_EXTCLK                0U
+#endif
+/*
+ * MCU type as defined in the ADI header.
+ */
+#define ADUCM410
+/*
+ * IO pins assignments.
+ */
+#define GP0_0                       0U
+#define GP0_1                       1U
+#define GP0_2                       2U
+#define GP0_3                       3U
+#define GP0_LED_BLUE                4U
+#define GP0_LED_GREEN               5U
+#define GP0_6                       6U
+#define GP0_7                       7U
+#define GP0_NPOR                    7U
+#define GP1_0                       0U
+#define GP1_1                       1U
+#define GP1_2                       2U
+#define GP1_3                       3U
+#define GP1_4                       4U
+#define GP1_5                       5U
+#define GP1_6                       6U
+#define GP1_7                       7U
+#define GP2_0                       0U
+#define GP2_1                       1U
+#define GP2_BUTTON                  2U
+#define GP2_SWCLK                   3U
+#define GP2_SWD                     4U
+#define GP2_5                       5U
+#define GP2_6                       6U
+#define GP2_7                       7U
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED_BLUE               PAL_LINE(GP0, 4U)
+#define LINE_LED_GREEN              PAL_LINE(GP0, 5U)
+#define LINE_NPOR                   PAL_LINE(GP0, 7U)
+#define LINE_BUTTON                 PAL_LINE(GP2, 2U)
+#define LINE_SWCLK                  PAL_LINE(GP2, 3U)
+#define LINE_SWD                    PAL_LINE(GP2, 4U)
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the ADUCM360 Reference Manual for details.
+ */
+#define PIN_CON_CON(n, v)           ((v) << (n * 2U))
+#define PIN_OEN_INPUT(n)            (0U << (n))
+#define PIN_OEN_OUTPUT(n)           (1U << (n))
+#define PIN_PUL_FLOATING(n)         (0U << (n))
+#define PIN_PUL_PULLUP(n)           (1U << (n))
+#define PIN_OCE_NORMAL(n)           (0U << (n))
+#define PIN_OCE_HIGHZ(n)            (1U << (n))
+/*
+ * P0 setup:
+ *
+ * P0.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P0.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P0.2  - PIN2                     (CON0, GPIO - input pullup).
+ * P0.3  - PIN3                     (CON0, GPIO - input pullup).
+ * P0.4  - LED_BLUE                 (CON0, GPIO - output floating).
+ * P0.5  - LED_GREEN                (CON0, GPIO - output floating).
+ * P0.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P0.7  - NPOR                     (CON0, NPOR).
+ */
+#define VAL_GP0CON                  (PIN_CON_CON(GP0_0, 0) |                \
+                                     PIN_CON_CON(GP0_1, 0) |                \
+                                     PIN_CON_CON(GP0_2, 0) |                \
+                                     PIN_CON_CON(GP0_3, 0) |                \
+                                     PIN_CON_CON(GP0_LED_BLUE, 0) |         \
+                                     PIN_CON_CON(GP0_LED_GREEN, 0) |        \
+                                     PIN_CON_CON(GP0_6, 0) |                \
+                                     PIN_CON_CON(GP0_NPOR, 0))
+#define VAL_GP0OEN                  (PIN_OEN_INPUT(GP0_0) |                 \
+                                     PIN_OEN_INPUT(GP0_1) |                 \
+                                     PIN_OEN_INPUT(GP0_2) |                 \
+                                     PIN_OEN_INPUT(GP0_3) |                 \
+                                     PIN_OEN_OUTPUT(GP0_LED_BLUE) |         \
+                                     PIN_OEN_OUTPUT(GP0_LED_GREEN) |        \
+                                     PIN_OEN_INPUT(GP0_6) |                 \
+                                     PIN_OEN_INPUT(GP0_NPOR))
+#define VAL_GP0PUL                  (PIN_PUL_PULLUP(GP0_0) |                \
+                                     PIN_PUL_PULLUP(GP0_1) |                \
+                                     PIN_PUL_PULLUP(GP0_2) |                \
+                                     PIN_PUL_PULLUP(GP0_3) |                \
+                                     PIN_PUL_FLOATING(GP0_LED_BLUE) |       \
+                                     PIN_PUL_FLOATING(GP0_LED_GREEN) |      \
+                                     PIN_PUL_PULLUP(GP0_6) |                \
+                                     PIN_PUL_PULLUP(GP0_NPOR))
+#define VAL_GP0OCE                  (PIN_OCE_NORMAL(GP0_0) |                \
+                                     PIN_OCE_NORMAL(GP0_1) |                \
+                                     PIN_OCE_NORMAL(GP0_2) |                \
+                                     PIN_OCE_NORMAL(GP0_3) |                \
+                                     PIN_OCE_NORMAL(GP0_LED_BLUE) |         \
+                                     PIN_OCE_NORMAL(GP0_LED_GREEN) |        \
+                                     PIN_OCE_NORMAL(GP0_6) |                \
+                                     PIN_OCE_NORMAL(GP0_NPOR))
+/*
+ * P1 setup:
+ *
+ * P1.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P1.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P1.2  - PIN2                     (CON0, GPIO - input pullup).
+ * P1.3  - PIN3                     (CON0, GPIO - input pullup).
+ * P1.4  - PIN4                     (CON0, GPIO - input pullup).
+ * P1.5  - PIN5                     (CON0, GPIO - input pullup).
+ * P1.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P1.7  - PIN7                     (CON0, GPIO - input pullup).
+ */
+#define VAL_GP1CON                  (PIN_CON_CON(GP1_0, 0) |                \
+                                     PIN_CON_CON(GP1_1, 0) |                \
+                                     PIN_CON_CON(GP1_2, 0) |                \
+                                     PIN_CON_CON(GP1_3, 0) |                \
+                                     PIN_CON_CON(GP1_4, 0) |                \
+                                     PIN_CON_CON(GP1_5, 0) |                \
+                                     PIN_CON_CON(GP1_6, 0) |                \
+                                     PIN_CON_CON(GP1_7, 0))                                     
+#define VAL_GP1OEN                  (PIN_OEN_INPUT(GP1_0) |                 \
+                                     PIN_OEN_INPUT(GP1_1) |                 \
+                                     PIN_OEN_INPUT(GP1_2) |                 \
+                                     PIN_OEN_INPUT(GP1_3) |                 \
+                                     PIN_OEN_INPUT(GP1_4) |                 \
+                                     PIN_OEN_INPUT(GP1_5) |                 \
+                                     PIN_OEN_INPUT(GP1_6) |                 \
+                                     PIN_OEN_INPUT(GP1_7))                                     
+#define VAL_GP1PUL                  (PIN_PUL_PULLUP(GP1_0) |                \
+                                     PIN_PUL_PULLUP(GP1_1) |                \
+                                     PIN_PUL_PULLUP(GP1_2) |                \
+                                     PIN_PUL_PULLUP(GP1_3) |                \
+                                     PIN_PUL_PULLUP(GP1_4) |                \
+                                     PIN_PUL_PULLUP(GP1_5) |                \
+                                     PIN_PUL_PULLUP(GP1_6) |                \
+                                     PIN_PUL_PULLUP(GP1_7))
+#define VAL_GP1OCE                  (PIN_OCE_NORMAL(GP1_0) |                \
+                                     PIN_OCE_NORMAL(GP1_1) |                \
+                                     PIN_OCE_NORMAL(GP1_2) |                \
+                                     PIN_OCE_NORMAL(GP1_3) |                \
+                                     PIN_OCE_NORMAL(GP1_4) |                \
+                                     PIN_OCE_NORMAL(GP1_5) |                \
+                                     PIN_OCE_NORMAL(GP1_6) |                \
+                                     PIN_OCE_NORMAL(GP1_7))
+/*
+ * P2 setup:
+ *
+ * P2.0  - PIN0                     (CON0, GPIO - input pullup).
+ * P2.1  - PIN1                     (CON0, GPIO - input pullup).
+ * P2.2  - BUTTON                   (CON0, GPIO - input floating).
+ * P2.3  - SWCLK                    (CON0, SWCLK).
+ * P2.4  - SWD                      (CON0, SWD).
+ * P2.5  - PIN5                     (CON0, GPIO - input pullup).
+ * P2.6  - PIN6                     (CON0, GPIO - input pullup).
+ * P2.7  - PIN7                     (CON0, GPIO - input pullup).
+ */
+#define VAL_GP2CON                  (PIN_CON_CON(GP2_0, 0) |                \
+                                     PIN_CON_CON(GP2_1, 0) |                \
+                                     PIN_CON_CON(GP2_BUTTON, 0) |           \
+                                     PIN_CON_CON(GP2_SWCLK, 0) |            \
+                                     PIN_CON_CON(GP2_SWD, 0) |              \
+                                     PIN_CON_CON(GP2_5, 0) |                \
+                                     PIN_CON_CON(GP2_6, 0) |                \
+                                     PIN_CON_CON(GP2_7, 0))
+#define VAL_GP2OEN                  (PIN_OEN_INPUT(GP2_0) |                 \
+                                     PIN_OEN_INPUT(GP2_1) |                 \
+                                     PIN_OEN_INPUT(GP2_BUTTON) |            \
+                                     PIN_OEN_INPUT(GP2_SWCLK) |             \
+                                     PIN_OEN_INPUT(GP2_SWD) |               \
+                                     PIN_OEN_INPUT(GP2_5) |                 \
+                                     PIN_OEN_INPUT(GP2_6) |                 \
+                                     PIN_OEN_INPUT(GP2_7))
+#define VAL_GP2PUL                  (PIN_PUL_PULLUP(GP2_0) |                \
+                                     PIN_PUL_PULLUP(GP2_1) |                \
+                                     PIN_PUL_FLOATING(GP2_BUTTON) |         \
+                                     PIN_PUL_PULLUP(GP2_SWCLK) |            \
+                                     PIN_PUL_PULLUP(GP2_SWD) |              \
+                                     PIN_PUL_PULLUP(GP2_5) |                \
+                                     PIN_PUL_PULLUP(GP2_6) |                \
+                                     PIN_PUL_PULLUP(GP2_7))
+#define VAL_GP2OCE                  (PIN_OCE_NORMAL(GP2_0) |                \
+                                     PIN_OCE_NORMAL(GP2_1) |                \
+                                     PIN_OCE_NORMAL(GP2_BUTTON) |           \
+                                     PIN_OCE_NORMAL(GP2_SWCLK) |            \
+                                     PIN_OCE_NORMAL(GP2_SWD) |              \
+                                     PIN_OCE_NORMAL(GP2_5) |                \
+                                     PIN_OCE_NORMAL(GP2_6) |                \
+                                     PIN_OCE_NORMAL(GP2_7))
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.mk b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.mk
new file mode 100644
index 000000000..50f02f4b3
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/ADI_EVAL_ADUCM410EBZ/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/ADI_EVAL_ADUCM410EBZ
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.c b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.c
new file mode 100644
index 000000000..edd60ed55
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.c
@@ -0,0 +1,75 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+  {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+  {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+  {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+  {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+}
diff --git a/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.h b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.h
new file mode 100644
index 000000000..5ebbc7ebd
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.h
@@ -0,0 +1,127 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Arduino Leonardo board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_LEONARDO
+#define BOARD_NAME "Arduino Leonardo"
+/*
+ * IO pins assignments.
+ */
+#define BOARD_LED1  7
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED1   PAL_LINE(IOPORT3, 7U)
+/*
+ * Port A setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRA  0x00
+#define VAL_PORTA 0xFF
+/*
+ * Port B setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRB  0x00
+#define VAL_PORTB 0xFF
+/*
+ * Port C setup.
+ * All inputs except PC7 which has a LED connected.
+ */
+#define VAL_DDRC  0x80
+#define VAL_PORTC 0xFF
+/*
+ * Port D setup.
+ * All inputs with pull-ups except PD5, TXLED.
+ */
+#define VAL_DDRD  0x10
+#define VAL_PORTD 0xFF
+/*
+ * Port E setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRE  0x00
+#define VAL_PORTE 0xFF
+/*
+ * Port F setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0xFF
+/*
+ * Port G setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0xFF
+/*
+ * Port H setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRH  0x00
+#define VAL_PORTH 0xFF
+/*
+ * Port J setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRJ  0x00
+#define VAL_PORTJ 0xFF
+/*
+ * Port K setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRK  0x00
+#define VAL_PORTK 0xFF
+/*
+ * Port L setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRL  0x00
+#define VAL_PORTL 0xFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.mk b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.mk
new file mode 100644
index 000000000..f704efcfd
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_LEONARDO/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_LEONARDO/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_LEONARDO
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.c b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.c
new file mode 100644
index 000000000..edd60ed55
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.c
@@ -0,0 +1,75 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+  {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+  {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+  {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+  {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+}
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.h b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.h
new file mode 100644
index 000000000..8647a0b82
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.h
@@ -0,0 +1,128 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Arduino Mega board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_MEGA
+#define BOARD_NAME "Arduino Mega"
+/*
+ * IO pins assignments.
+ */
+#define PORTB_LED1  7
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED1   PAL_LINE(IOPORT2, 7U)
+/*
+ * Port A setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRA    0x00
+#define VAL_PORTA   0xFF
+/*
+ * Port B setup.
+ * All inputs except PB7 which has a LED connected.
+ */
+#define VAL_DDRB    0x80
+#define VAL_PORTB   0xFF
+/*
+ * Port C setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRC    0x00
+#define VAL_PORTC   0xFF
+/*
+ * Port D setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRD    0x00
+#define VAL_PORTD   0xFF
+/*
+ * Port E setup.
+ * All inputs except PE1 (Serial TX0).
+ */
+#define VAL_DDRE    0x02
+#define VAL_PORTE   0xFF
+/*
+ * Port F setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRF    0x00
+#define VAL_PORTF   0xFF
+/*
+ * Port G setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRG    0x00
+#define VAL_PORTG   0xFF
+/*
+ * Port H setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRH    0x00
+#define VAL_PORTH   0xFF
+/*
+ * Port J setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRJ    0x00
+#define VAL_PORTJ   0xFF
+/*
+ * Port K setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRK    0x00
+#define VAL_PORTK   0xFF
+/*
+ * Port L setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRL    0x00
+#define VAL_PORTL   0xFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.mk b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.mk
new file mode 100644
index 000000000..299e6acae
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MEGA/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_MEGA/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_MEGA
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MINI/board.c b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.c
new file mode 100644
index 000000000..47ee782c1
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.c
@@ -0,0 +1,50 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EIMSK  = 0x00;
+}
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MINI/board.h b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.h
new file mode 100644
index 000000000..dd4bcfe6d
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.h
@@ -0,0 +1,71 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Arduino Uno or  board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_MINI
+#define BOARD_NAME "Arduino Mini"
+/*
+ * IO pins assignments.
+ */
+#define PORTB_LED1       5
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED1   PAL_LINE(IOPORT2, 5U)
+/*
+ * Port B setup.
+ * All inputs except PB5 which has a LED connected.
+ */
+#define VAL_DDRB  0x20
+#define VAL_PORTB 0xFF
+/*
+ * Port C setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+/*
+ * Port D setup.
+ * All inputs except PD1 (Serial TX0).
+ */
+#define VAL_DDRD  0x02
+#define VAL_PORTD 0xFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/ARDUINO_MINI/board.mk b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.mk
new file mode 100644
index 000000000..1e32b9124
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_MINI/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_MINI/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_MINI
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ARDUINO_NANO/board.c b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.c
new file mode 100644
index 000000000..47ee782c1
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.c
@@ -0,0 +1,50 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EIMSK  = 0x00;
+}
diff --git a/lib/chibios/os/hal/boards/ARDUINO_NANO/board.h b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.h
new file mode 100644
index 000000000..361d4bf50
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.h
@@ -0,0 +1,71 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Arduino Uno or  board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_NANO
+#define BOARD_NAME "Arduino Nano"
+/*
+ * IO pins assignments.
+ */
+#define PORTB_LED1       5
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED1   PAL_LINE(IOPORT2, 5U)
+/*
+ * Port B setup.
+ * All inputs except PB5 which has a LED connected.
+ */
+#define VAL_DDRB  0x20
+#define VAL_PORTB 0xFF
+/*
+ * Port C setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+/*
+ * Port D setup.
+ * All inputs except PD1 (Serial TX0).
+ */
+#define VAL_DDRD  0x02
+#define VAL_PORTD 0xFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/ARDUINO_NANO/board.mk b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.mk
new file mode 100644
index 000000000..5f195171b
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_NANO/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_NANO/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_NANO
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/ARDUINO_UNO/board.c b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.c
new file mode 100644
index 000000000..47ee782c1
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.c
@@ -0,0 +1,50 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EIMSK  = 0x00;
+}
diff --git a/lib/chibios/os/hal/boards/ARDUINO_UNO/board.h b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.h
new file mode 100644
index 000000000..5215c21cb
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.h
@@ -0,0 +1,71 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Arduino Uno or  board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_ARDUINO_UNO
+#define BOARD_NAME "Arduino Uno"
+/*
+ * IO pins assignments.
+ */
+#define PORTB_LED1       5
+/*
+ * IO lines assignments.
+ */
+#define LINE_LED1   PAL_LINE(IOPORT2, 5U)
+/*
+ * Port B setup.
+ * All inputs except PB5 which has a LED connected.
+ */
+#define VAL_DDRB  0x20
+#define VAL_PORTB 0xFF
+/*
+ * Port C setup.
+ * All inputs with pull-ups.
+ */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+/*
+ * Port D setup.
+ * All inputs except PD1 (Serial TX0).
+ */
+#define VAL_DDRD  0x02
+#define VAL_PORTD 0xFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/ARDUINO_UNO/board.mk b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.mk
new file mode 100644
index 000000000..fd3b9e66e
--- /dev/null
+++ b/lib/chibios/os/hal/boards/ARDUINO_UNO/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ARDUINO_UNO/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ARDUINO_UNO
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.c b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.c
new file mode 100644
index 000000000..c50b440cb
--- /dev/null
+++ b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.c
@@ -0,0 +1,72 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+  {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+  {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+  {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+  {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  cli();
+}
diff --git a/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.h b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.h
new file mode 100644
index 000000000..61ffcba33
--- /dev/null
+++ b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.h
@@ -0,0 +1,49 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef BOARD_H
+#define BOARD_H
+/*
+ * Setup for the Digispark ATtiny 167  board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_NAME "Digispark Pro board ATtiny167"
+/* All inputs.  */
+#define VAL_DDRA  0x00
+#define VAL_PORTA 0xFF
+/* All inputs except PB1 which has a LED connected. */
+#define VAL_DDRB  0x02
+#define VAL_PORTB 0xFF
+#define PORTB_LED1       1
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.mk b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.mk
new file mode 100644
index 000000000..4c140def4
--- /dev/null
+++ b/lib/chibios/os/hal/boards/DIGISPARK_ATTINY_167/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/DIGISPARK_ATTINY_167/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/DIGISPARK_ATTINY_167
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.c b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
new file mode 100644
index 000000000..0059a7849
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
@@ -0,0 +1,52 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  lpc111x_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+}
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.h b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.h
new file mode 100644
index 000000000..9d9fe92af
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.h
@@ -0,0 +1,81 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Embedded Artists LPCXpresso LPC11C24
+ * board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11C24
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC11C24"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_LED)
+#define VAL_GPIO0DATA           0x00000000
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            0x00000000
+#define VAL_GPIO1DATA           0x00000000
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW_ISP            1
+#define GPIO0_LED               7
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk
new file mode 100644
index 000000000..ddea84f93
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_11C24/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_11C24/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_11C24
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
new file mode 100644
index 000000000..fcd983669
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
@@ -0,0 +1,58 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  lpc111x_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->R_PIO1_2 = 0xC1;           /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO1_9 = 0xC0;             /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO1_10 = 0xC0;            /* Disables pull-up on LED3G output.*/
+}
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h
new file mode 100644
index 000000000..547fdd5c7
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.h
@@ -0,0 +1,96 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1114
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1114"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_LED2              7
+#define GPIO1_LED3B             2
+#define GPIO1_SW4               4
+#define GPIO1_LED3R             9
+#define GPIO1_LED3G             10
+#define GPIO1_SPI0SEL           11
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk
new file mode 100644
index 000000000..f8b4a408f
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1114/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1114
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
new file mode 100644
index 000000000..7527e53ac
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
@@ -0,0 +1,65 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+  {VAL_GPIO0DATA, VAL_GPIO0DIR},
+  {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  lpc_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0x80;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->TRST_PIO0_14 = 0x81;       /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO0_21 = 0x80;            /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO0_22 = 0x80;            /* Disables pull-up on LED3G output.*/
+  /* SSP0 mapping.*/
+  LPC_IOCON->PIO1_29 = 0x81;            /* SCK0 without resistors.          */
+  LPC_IOCON->PIO0_8  = 0x81;            /* MISO0 without resistors.         */
+  LPC_IOCON->PIO0_9  = 0x81;            /* MOSI0 without resistors.         */
+  /* USART mapping.*/
+  LPC_IOCON->PIO0_18 = 0x81;            /* RDX without resistors.           */
+  LPC_IOCON->PIO0_19 = 0x81;            /* TDX without resistors.           */
+}
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h
new file mode 100644
index 000000000..1abfcfb28
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.h
@@ -0,0 +1,88 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1114 daughter
+ * board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC11U14
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC11U14"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * SCK0 connection on this board.
+ */
+#define LPC11xx_SPI_SCK0_SELECTOR SCK0_IS_PIO2_11
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL)   |             \
+                                PAL_PORT_BIT(GPIO0_USB_DPCTL) |             \
+                                PAL_PORT_BIT(GPIO0_LED2)      |             \
+                                PAL_PORT_BIT(GPIO0_LED3B)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3R)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3G)     |             \
+                                PAL_PORT_BIT(GPIO0_SPI0SEL)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL)   |             \
+                                PAL_PORT_BIT(GPIO0_LED2)      |             \
+                                PAL_PORT_BIT(GPIO0_LED3B)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3R)     |             \
+                                PAL_PORT_BIT(GPIO0_LED3G)     |             \
+                                PAL_PORT_BIT(GPIO0_SPI0SEL)
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            0x00000000
+#define VAL_GPIO1DATA           0x00000000
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_USB_VBUS          3
+#define GPIO0_USB_DPCTL         6
+#define GPIO0_LED2              7
+#define GPIO0_SW4               16
+#define GPIO0_LED3B             14
+#define GPIO0_LED3R             21
+#define GPIO0_LED3G             22
+#define GPIO0_SPI0SEL           23
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk
new file mode 100644
index 000000000..23b610268
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_11U14/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_11U14
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
new file mode 100644
index 000000000..223cd6704
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
@@ -0,0 +1,58 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  LPC13xx_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   * NOTE: PIO1_2 is associated also to the JTAG, if you need to use JTAG
+   *       you must comment that line first.
+   */
+  LPC_IOCON->PIO0_7 = 0xC0;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->R_PIO1_2 = 0xC1;           /* Disables pull-up on LED3B output
+                                           and makes it GPIO1_2.            */
+  LPC_IOCON->PIO1_9 = 0xC0;             /* Disables pull-up on LED3R output.*/
+  LPC_IOCON->PIO1_10 = 0xC0;            /* Disables pull-up on LED3G output.*/
+}
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h
new file mode 100644
index 000000000..b86b11042
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.h
@@ -0,0 +1,91 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Embedded Artists LPCXpresso Base Board with LPC1343 daughter
+ * board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_BB_LPC1343
+#define BOARD_NAME "Embedded Artists LPCXpresso Base Board + LPC1343"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+#define VAL_GPIO0DATA           PAL_PORT_BIT(GPIO0_OLEDSEL) |               \
+                                PAL_PORT_BIT(GPIO0_LED2)
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED3B)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3R)   |               \
+                                PAL_PORT_BIT(GPIO1_LED3G)   |               \
+                                PAL_PORT_BIT(GPIO1_SPI0SEL)
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            0x00000000
+#define VAL_GPIO2DATA           0x00000000
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            0x00000000
+#define VAL_GPIO3DATA           0x00000000
+/*
+ * Pin definitions.
+ */
+#define GPIO0_SW3               1
+#define GPIO0_OLEDSEL           2
+#define GPIO0_LED2              7
+#define GPIO1_LED3B             2
+#define GPIO1_SW4               4
+#define GPIO1_LED3R             9
+#define GPIO1_LED3G             10
+#define GPIO1_SPI0SEL           11
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk
new file mode 100644
index 000000000..92d2d7615
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1343/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_BB_1343
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
new file mode 100644
index 000000000..296d6d686
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
@@ -0,0 +1,135 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {VAL_GPIO0DATA, VAL_GPIO0DIR};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void){
+  lpc8xx_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void){
+  /* Enable clocks to IOCON & SWM */
+  LPC_SYSCON->SYSAHBCLKCTRL |= ((1<<18)|(1<<7));
+   
+#if defined VAL_PIO0_0
+  LPC_IOCON->PIO0_0 =  PIN_RSVD|VAL_PIO0_0;
+#endif
+#if defined VAL_PIO0_1
+  LPC_IOCON->PIO0_1 =  PIN_RSVD|VAL_PIO0_1;
+#endif
+#if defined VAL_PIO0_2
+  LPC_IOCON->PIO0_2 =  PIN_RSVD|VAL_PIO0_2;
+#endif
+#if defined VAL_PIO0_3
+  LPC_IOCON->PIO0_3 =  PIN_RSVD|VAL_PIO0_3;
+#endif
+#if defined VAL_PIO0_4
+  LPC_IOCON->PIO0_4 =  PIN_RSVD|VAL_PIO0_4;
+#endif
+#if defined VAL_PIO0_5
+  LPC_IOCON->PIO0_5 =  PIN_RSVD|VAL_PIO0_5;
+#endif
+#if defined VAL_PIO0_6
+  LPC_IOCON->PIO0_6 =  PIN_RSVD|VAL_PIO0_6;
+#endif
+#if defined VAL_PIO0_7
+  LPC_IOCON->PIO0_7 =  PIN_RSVD|VAL_PIO0_7;
+#endif
+#if defined VAL_PIO0_8
+  LPC_IOCON->PIO0_8 =  PIN_RSVD|VAL_PIO0_8;
+#endif
+#if defined VAL_PIO0_9
+  LPC_IOCON->PIO0_9 =  PIN_RSVD|VAL_PIO0_9;
+#endif
+#if defined VAL_PIO0_10
+  LPC_IOCON->PIO0_10 =  PIN_RSVD|VAL_PIO0_10;
+#endif
+#if defined VAL_PIO0_11
+  LPC_IOCON->PIO0_11 =  PIN_RSVD|VAL_PIO0_11;
+#endif
+#if defined VAL_PIO0_12
+  LPC_IOCON->PIO0_12 =  PIN_RSVD|VAL_PIO0_12;
+#endif
+#if defined VAL_PIO0_13
+  LPC_IOCON->PIO0_13 =  PIN_RSVD|VAL_PIO0_13;
+#endif
+#if defined VAL_PIO0_14
+  LPC_IOCON->PIO0_14 =  PIN_RSVD|VAL_PIO0_14;
+#endif
+#if defined VAL_PIO0_15
+  LPC_IOCON->PIO0_15 =  PIN_RSVD|VAL_PIO0_15;
+#endif
+#if defined VAL_PIO0_16
+  LPC_IOCON->PIO0_16 =  PIN_RSVD|VAL_PIO0_16;
+#endif
+#if defined VAL_PIO0_17
+  LPC_IOCON->PIO0_17 =  PIN_RSVD|VAL_PIO0_17;
+#endif
+#if defined VAL_PINASSIGN0
+  LPC_SWM->PINASSIGN0 = VAL_PINASSIGN0;
+#endif
+#if defined VAL_PINASSIGN1
+  LPC_SWM->PINASSIGN1 = VAL_PINASSIGN1;
+#endif
+#if defined VAL_PINASSIGN2
+  LPC_SWM->PINASSIGN2 = VAL_PINASSIGN2;
+#endif
+#if defined VAL_PINASSIGN3
+  LPC_SWM->PINASSIGN3 = VAL_PINASSIGN3;
+#endif
+#if defined VAL_PINASSIGN4
+  LPC_SWM->PINASSIGN4 = VAL_PINASSIGN4;
+#endif
+#if defined VAL_PINASSIGN5
+  LPC_SWM->PINASSIGN5 = VAL_PINASSIGN5;
+#endif
+#if defined VAL_PINASSIGN6
+  LPC_SWM->PINASSIGN6 = VAL_PINASSIGN6;
+#endif
+#if defined VAL_PINASSIGN7
+  LPC_SWM->PINASSIGN7 = VAL_PINASSIGN7;
+#endif
+#if defined VAL_PINASSIGN8
+  LPC_SWM->PINASSIGN8 = VAL_PINASSIGN8;
+#endif
+  /* Disable clocks to IOCON & SWM */
+  LPC_SYSCON->SYSAHBCLKCTRL &= ~((1<<18)|(1<<7));
+}
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h
new file mode 100644
index 000000000..559ac7a04
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Embedded Artists LPCXpresso LPC812 board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_EA_LPC812
+#define BOARD_NAME "Embedded Artists LPCXpresso LPC812"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the LPC8xx Reference Manual for details.
+ */
+/* Pull-up/down  */
+#define PIN_MODE_NOPULL               (0<<3)
+#define PIN_MODE_PULLDOWN             (1<<3)
+#define PIN_MODE_PULLUP               (2<<3)
+#define PIN_MODE_REPEATER             (3<<3)
+/* Hysteresis */
+#define PIN_HYS_EN                    (1<<5)
+/* Invert Input */
+#define PIN_INV_INPUT                 (1<<6)
+/* Reserved bits */
+#define PIN_RSVD                      (1<<7)
+/* I2C Mode */
+#define PIN_I2CMODE_STD               (0<<8)
+#define PIN_I2CMODE_STDIO             (1<<8)
+#define PIN_I2CMODE_FAST              (2<<8)
+/* Open Drain */
+#define PIN_OPEN_DRAIN                (1<<10)
+/* Input Filter Sample Clocks */
+#define PIN_SMODE_FILTER(n)           ((n)<<11)
+/* Input Filter clock divider */
+#define PIN_CLKDIV_FILTER(n)          ((n)<<13)
+/*
+ * Pin definitions.
+ */
+#define LED_RED                        7
+#define LED_BLUE                      16
+#define LED_GREEN                     17
+/*
+ * GPIO 0 initial setup.
+ */
+/*#define VAL_PIO0_0              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_1              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_2              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_3              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_4              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_5              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_6              PIN_MODE_PULLUP*/
+#define VAL_PIO0_7              PIN_MODE_NOPULL
+/*#define VAL_PIO0_8              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_9              PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_10             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_11             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_12             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_13             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_14             PIN_MODE_PULLUP*/
+/*#define VAL_PIO0_15             PIN_MODE_PULLUP*/
+#define VAL_PIO0_16             PIN_MODE_NOPULL
+#define VAL_PIO0_17             PIN_MODE_NOPULL
+    /* UART0: TXD = P0.4, RXD  = P0.0)*/
+#define VAL_PINASSIGN0            ((0xFFFF0000) | (0<<8) | (4))
+/*#define VAL_PINASSIGN1            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN2            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN3            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN4            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN5            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN6            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN7            0xFFFFFFFF*/
+/*#define VAL_PINASSIGN8            0xFFFFFFFF*/
+#define VAL_GPIO0DIR            (PAL_PORT_BIT(LED_RED)   |           \
+                                 PAL_PORT_BIT(LED_BLUE)   |          \
+                                 PAL_PORT_BIT(LED_GREEN))
+                                
+#define VAL_GPIO0DATA           (PAL_PORT_BIT(LED_RED)   |           \
+                                 PAL_PORT_BIT(LED_BLUE)   |          \
+                                 PAL_PORT_BIT(LED_GREEN))
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk
new file mode 100644
index 000000000..60953f3f7
--- /dev/null
+++ b/lib/chibios/os/hal/boards/EA_LPCXPRESSO_LPC812/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_LPC812/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/EA_LPCXPRESSO_LPC812
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.c b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.c
new file mode 100644
index 000000000..e0d7b4c4a
--- /dev/null
+++ b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.c
@@ -0,0 +1,98 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  stm32_clock_init();
+}
+#if HAL_USE_MMC_SPI
+/*
+ * Card detection through the card internal pull-up on D3.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  return !palReadPad(GPIOC, GPIOC_SPI3_SD_CD);
+}
+/*
+ * Card write protection detection is not possible, the card is always
+ * reported as not protected.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  return FALSE;
+}
+#endif
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Several I/O pins are re-mapped:
+   *   USART3 to the PD8/PD9 pins.
+   *   I2C1 to the PB8/PB9 pins.
+   *   SPI3 to the PC10/PC11/PC12 pins.
+   */
+  //AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_FULLREMAP |
+  //              AFIO_MAPR_I2C1_REMAP |
+  //              AFIO_MAPR_SPI3_REMAP |
+  //              AFIO_MAPR_ETH_REMAP;
+  /*
+     * Several I/O pins are re-mapped:
+     *   .
+     */
+    AFIO->MAPR |= AFIO_MAPR_ETH_REMAP |
+                  AFIO_MAPR_I2C1_REMAP |
+                  AFIO_MAPR_SPI3_REMAP |
+                  AFIO_MAPR_CAN_REMAP_REMAP3 |
+                  AFIO_MAPR_USART1_REMAP |
+                  AFIO_MAPR_USART2_REMAP;
+}
diff --git a/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.h b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.h
new file mode 100644
index 000000000..8c106e810
--- /dev/null
+++ b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.h
@@ -0,0 +1,254 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the GoldBull STM32F107 V3 evaluation board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_GOLDBULL_STM32F107VC
+#define BOARD_NAME              "GoldBull STM32F107VC V3"
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            25000000
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F107xC
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID            MII_DP83848I_ID
+#define BOARD_PHY_RMII
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_SWITCH_WKUP       0
+#define GPIOB_SWITCH_USER       2
+#define GPIOC_SWITCH_TAMPER     13
+#define GPIOC_SPI3_SD_CS        3
+#define GPIOC_SPI3_SD_CD        2
+#define GPIOD_LED3              2
+#define GPIOD_LED4              3
+#define GPIOD_LED5              4
+#define GPIOD_LED6              7
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA0  - Normal input      (WKUP BUTTON).
+ * PA1  - Normal input      (ETH_RMII_REF_CLK).
+ * PA2  - Alternate output  (ETH_RMII_MDIO).
+ * PA3  - Input with PU     (TP_IRQ).
+ * PA4  - Push Pull output  (TP_CS).
+ * PA5  - Alternate output  (SPI1 SCK).
+ * PA6  - Input with PU     (SPI1 MISO).
+ * PA7  - Alternate output  (SPI1 MOSI).
+ * PA8  - Alternate output  (MCO).
+ * PA9  - Normal input      (OTG_VBUS).
+ * PA10 - Normal input      (OTG_ID).
+ * PA11 - Normal input      (OTG_DM).
+ * PA12 - Normal input      (OTG_DP).
+ * PA13 - Normal input      (TMS).
+ * PA14 - Normal input      (TCK).
+ * PA15 - Normal input      (TDI).
+ */
+#define VAL_GPIOACRL            0xB8B38B44      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x4444444B      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+/*
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ */
+/*
+ * Port B setup:
+ * PB0  - Input with PU     (unconnected).
+ * PB1  - Input with PU     (unconnected).
+ * PB2  - Normal input      (BOOT1, KEY_USER).
+ * PB3  - Normal input      (TDO).
+ * PB4  - Normal input      (TRST).
+ * PB5  - Input with PU     (CAN2 RX).
+ * PB6  - Alternate output  (USART1 TX, remapped).
+ * PB7  - Input with PU     (USART1 RX, remapped).
+ * PB8  - Alternate O.D.    (I2C1 SCL, remapped).
+ * PB9  - Alternate O.D.    (I2C1 SDA, remapped).
+ * PB10 - Input with PU     (BL_CNT).
+ * PB11 - Alternate output  (ETH_RMII_TX_EN).
+ * PB12 - Alternate output  (ETH_RMII_TXD0).
+ * PB13 - Alternate output  (ETH_RMII_TXD1).
+ * PB14 - Input with PU     (unconnected).
+ * PB15 - Input with PU     (unconnected).
+ */
+#define VAL_GPIOBCRL            0x8B844488      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88BBB8FF      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+/*
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ */
+/*
+ * Port C setup:
+ * PC0  - Analog input      (ADC_IN).
+ * PC1  - Alternate output  (ETH_MDC).
+ * PC2  - Input with PU     (SD_CD).
+ * PC3  - Push Pull output  (SD_CS).
+ * PC4  - Push Pull output  (OTG_PW_ON).
+ * PC5  - Push Pull output  (SF_CS).
+ * PC6  - Push Pull output  (LCD_RD).
+ * PC7  - Push Pull output  (LCD_WR).
+ * PC8  - Push Pull output  (LCD_RS).
+ * PC9  - Push Pull output  (LCD_CS).
+ * PC10 - Alternate output  (SPI3 SCK).
+ * PC11 - Input with PU     (SPI3 MISO).
+ * PC12 - Alternate output  (SPI3 MOSI).
+ * PC13 - Normal input      (KEY_TAMPER).
+ * PC14 - Normal input      (OSC32 IN).
+ * PC15 - Normal input      (OSC32 OUT).
+ */
+#define VAL_GPIOCCRL            0x333338B0      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x444B8B33      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+/*
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ */
+/*
+ * Port D setup:
+ * PD0  - Input with PU     (CAN1_RX, remapped).
+ * PD1  - Alternate output  (CAN1_TX, remapped).
+ * PD2  - Push Pull output  (LED3).
+ * PD3  - Push Pull output  (LED4).
+ * PD4  - Push Pull output  (LED5).
+ * PD5  - Alternate output  (USART2 TX, remapped).
+ * PD6  - Input with PU     (USART2 RX, remapped).
+ * PD7  - Push Pull output  (LED6).
+ * PD8  - Normal input      (ETH_RMII_CRS_DV, remapped).
+ * PD9  - Normal input      (ETH_RMII_RXD0, remapped).
+ * PD10 - Normal input      (ETH_RMII_RXD1, remapped).
+ * PD11 - Input with PU     (JOY_UP).
+ * PD12 - Input with PU     (JOY_DOWN).
+ * PD13 - Input with PU     (JOY_LEFT).
+ * PD14 - Input with PU     (JOY_RIGHT).
+ * PD15 - Input with PU     (JOY_SEL).
+ */
+#define VAL_GPIODCRL            0x38B333B8      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888444      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.mk b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.mk
new file mode 100644
index 000000000..fd1570a67
--- /dev/null
+++ b/lib/chibios/os/hal/boards/GOLDBULL_STM32_F107VC/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/GOLDBULL_STM32_F107VC/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/GOLDBULL_STM32_F107VC
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.c b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.c
new file mode 100644
index 000000000..236dde472
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.c
@@ -0,0 +1,49 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH},
+  {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH},
+  {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH},
+  {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH},
+  {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  stm32_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.h b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.h
new file mode 100644
index 000000000..ca9a860b2
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.h
@@ -0,0 +1,193 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the LeafLabs Maple Mini.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_MAPLEMINI_STM32_F103
+#define BOARD_NAME              "LeafLabs Maple Mini"
+/*
+ * Board frequencies.
+ */
+#define STM32_LSECLK            32768
+#define STM32_HSECLK            8000000
+/*
+ * MCU type, supported types are defined in ./os/hal/platforms/hal_lld.h.
+ */
+#define STM32F103xB
+/*
+ * IO pins assignments
+ *
+ * numbering is sorted by onboard/connectors, as from the schematics in
+ * https://github.com/leaflabs/maplemini
+ */
+/* on-board */
+#define GPIOB_LED               1
+#define GPIOB_USB_DISC          9
+#define GPIOD_OSC_IN            0
+#define GPIOD_OSC_OUT           1
+/* J1 connector */
+// pin 1:       AV+
+// pin 2:       AV-
+// pin 3:       VBAT
+#define GPIOC_TAMPER_RTC        13      // pin 4
+#define GPIOC_OSC32_IN          14      // pin 5
+#define GPIOC_OSD32_OUT         15      // pin 6
+// pin 7:       RESET
+#define GPIOA_USART2_CTS        0       // pin 8
+#define GPIOA_USART2_RTS        1       // pin 9
+#define GPIOA_USART2_TX         2       // pin 10
+#define GPIOA_USART2_RX         3       // pin 11
+#define GPIOA_SPI1_NSS          4       // pin 12
+#define GPIOA_SPI1_SCK          5       // pin 13
+#define GPIOA_SPI1_MISO         6       // pin 14
+#define GPIOA_SPI1_MOSI         7       // pin 15
+#define GPIOB_ADC12_IN8         0       // pin 16
+#define GPIOB_BOOT1             2       // pin 17
+#define GPIOB_I2C2_SCL          10      // pin 18
+#define GPIOB_I2C2_SDA          11      // pin 19
+// pin 20: VIN
+/* J2 connector */
+#define GPIOB_SPI2_NSS          12      // pin 1
+#define GPIOB_SPI2_SCK          13      // pin 2
+#define GPIOB_SPI2_MISO         14      // pin 3
+#define GPIOB_SPI2_MOSI         15      // pin 4
+#define GPIOA_USART1_CK         8       // pin 5
+#define GPIOA_USART1_TX         9       // pin 6
+#define GPIOA_USART1_RX         10      // pin 7
+#define GPIOA_USBDM             11      // pin 8
+#define GPIOA_USBDP             12      // pin 9
+#define GPIOA_JTMS              13      // pin 10
+#define GPIOA_JTCK              14      // pin 11
+#define GPIOA_JTDI              15      // pin 12
+#define GPIOB_JTDO              3       // pin 13
+#define GPIOB_JTRST             4       // pin 14
+#define GPIOB_I2C1_SMBA         5       // pin 15
+#define GPIOB_I2C1_SCL          6       // pin 16
+#define GPIOB_I2C1_SDA          7       // pin 17
+#define GPIOB_BOOT0_BUTTON      8       // pin 18
+// pin 19: GND
+// pin 20: VCC
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ *
+ * The digits have the following meaning:
+ *   0 - Analog input.
+ *   1 - Push Pull output 10MHz.
+ *   2 - Push Pull output 2MHz.
+ *   3 - Push Pull output 50MHz.
+ *   4 - Digital input.
+ *   5 - Open Drain output 10MHz.
+ *   6 - Open Drain output 2MHz.
+ *   7 - Open Drain output 50MHz.
+ *   8 - Digital input with PullUp or PullDown resistor depending on ODR.
+ *   9 - Alternate Push Pull output 10MHz.
+ *   A - Alternate Push Pull output 2MHz.
+ *   B - Alternate Push Pull output 50MHz.
+ *   C - Reserved.
+ *   D - Alternate Open Drain output 10MHz.
+ *   E - Alternate Open Drain output 2MHz.
+ *   F - Alternate Open Drain output 50MHz.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+/*
+ * Port A setup.
+ * Everything input with pull-up except:
+ * PA2  - Alternate output  (USART2 TX).
+ * PA3  - Normal input      (USART2 RX).
+ * PA9  - Alternate output  (USART1 TX).
+ * PA10 - Normal input      (USART1 RX).
+ */
+#define VAL_GPIOACRL            0x88884B88      /*  PA7...PA0 */
+#define VAL_GPIOACRH            0x888884B8      /* PA15...PA8 */
+#define VAL_GPIOAODR            0xFFFFFFFF
+/*
+ * Port B setup.
+ * Everything input with pull-up except:
+ * PB1    - Push Pull output  (LED).
+ * PB9    - Push Pull output  (USB switch).
+ */
+#define VAL_GPIOBCRL            0x88888838      /*  PB7...PB0 */
+#define VAL_GPIOBCRH            0x88888838      /* PB15...PB8 */
+#define VAL_GPIOBODR            0xFFFFFFFF
+/*
+ * Port C setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOCCRL            0x88888888      /*  PC7...PC0 */
+#define VAL_GPIOCCRH            0x88888888      /* PC15...PC8 */
+#define VAL_GPIOCODR            0xFFFFFFFF
+/*
+ * Port D setup.
+ * Everything input with pull-up except:
+ * PD0  - Normal input (XTAL).
+ * PD1  - Normal input (XTAL).
+ */
+#define VAL_GPIODCRL            0x88888844      /*  PD7...PD0 */
+#define VAL_GPIODCRH            0x88888888      /* PD15...PD8 */
+#define VAL_GPIODODR            0xFFFFFFFF
+/*
+ * Port E setup.
+ * Everything input with pull-up except:
+ */
+#define VAL_GPIOECRL            0x88888888      /*  PE7...PE0 */
+#define VAL_GPIOECRH            0x88888888      /* PE15...PE8 */
+#define VAL_GPIOEODR            0xFFFFFFFF
+/*
+ * USB bus activation macro, required by the USB driver.
+ */
+#define usb_lld_connect_bus(usbp) palClearPad(GPIOB, GPIOB_USB_DISC)
+/*
+ * USB bus de-activation macro, required by the USB driver.
+ */
+#define usb_lld_disconnect_bus(usbp) palSetPad(GPIOB, GPIOB_USB_DISC)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.mk b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.mk
new file mode 100644
index 000000000..95ae22e83
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MAPLEMINI_STM32_F103/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/MAPLEMINI_STM32_F103/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/MAPLEMINI_STM32_F103
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.c b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.c
new file mode 100644
index 000000000..9ff3f758c
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.c
@@ -0,0 +1,266 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#include "hal.h"
+#include "stm32_gpio.h"
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_setup_t          PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_setup_t          PKData;
+#endif
+} gpio_config_t;
+/**
+ * @brief   STM32 GPIO static initialization data.
+ */
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
+  {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+   VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+  {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+   VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+  {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+   VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+  {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+   VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+  {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+   VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+  {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+   VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+  {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+   VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+  {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+   VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+  {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}
+#endif
+};
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+static void stm32_gpio_init(void) {
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB1(STM32_GPIO_EN_MASK);
+  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
+#endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+  gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+  gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+/**
+ * @brief   Early initialization code.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
+ */
+void __early_init(void) {
+  stm32_gpio_init();
+  stm32_clock_init();
+}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief   MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return true;
+}
+/**
+ * @brief   MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  /* CHTODO: Fill the implementation.*/
+  return false;
+}
+#endif
+/**
+ * @brief   Board-specific initialization code.
+ * @note    You can add your board-specific code here.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.h b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.h
new file mode 100644
index 000000000..1372d16c5
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.h
@@ -0,0 +1,1359 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+#ifndef BOARD_H
+#define BOARD_H
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+/*
+ * Setup for Mikroe Clicker 2 for STM32 board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_MIKROE_CLICKER2_STM32
+#define BOARD_NAME                  "Mikroe Clicker 2 for STM32"
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK                32768U
+#endif
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK                25000000U
+#endif
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD                   300U
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F407xx
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0                  0U
+#define GPIOA_PIN1                  1U
+#define GPIOA_MB1_AN                2U
+#define GPIOA_MB2_AN                3U
+#define GPIOA_PIN4                  4U
+#define GPIOA_PIN5                  5U
+#define GPIOA_PIN6                  6U
+#define GPIOA_PIN7                  7U
+#define GPIOA_I2C3_SCL              8U
+#define GPIOA_VBUS_FS               9U
+#define GPIOA_BUTTON2               10U
+#define GPIOA_OTG_FS_DM             11U
+#define GPIOA_OTG_FS_DP             12U
+#define GPIOA_SWDIO                 13U
+#define GPIOA_SWCLK                 14U
+#define GPIOA_PIN15                 15U
+#define GPIOB_PIN0                  0U
+#define GPIOB_PIN1                  1U
+#define GPIOB_PIN2                  2U
+#define GPIOB_PIN3                  3U
+#define GPIOB_PIN4                  4U
+#define GPIOB_PIN5                  5U
+#define GPIOB_PIN6                  6U
+#define GPIOB_PIN7                  7U
+#define GPIOB_PIN8                  8U
+#define GPIOB_PIN9                  9U
+#define GPIOB_I2C2_SCL              10U
+#define GPIOB_I2C2_SDA              11U
+#define GPIOB_PIN12                 12U
+#define GPIOB_SPI2_SCK              13U
+#define GPIOB_SPI2_MISO             14U
+#define GPIOB_SPI2_MOSI             15U
+#define GPIOC_PIN0                  0U
+#define GPIOC_PIN1                  1U
+#define GPIOC_PIN2                  2U
+#define GPIOC_PIN3                  3U
+#define GPIOC_PIN4                  4U
+#define GPIOC_PIN5                  5U
+#define GPIOC_PIN6                  6U
+#define GPIOC_PIN7                  7U
+#define GPIOC_PIN8                  8U
+#define GPIOC_I2C3_SDA              9U
+#define GPIOC_SPI3_SCK              10U
+#define GPIOC_SPI3_MISO             11U
+#define GPIOC_SPI3_MOSI             12U
+#define GPIOC_PIN13                 13U
+#define GPIOC_PIN14                 14U
+#define GPIOC_PIN15                 15U
+#define GPIOD_PIN0                  0U
+#define GPIOD_PIN1                  1U
+#define GPIOD_PIN2                  2U
+#define GPIOD_PIN3                  3U
+#define GPIOD_PIN4                  4U
+#define GPIOD_USART2_TX             5U
+#define GPIOD_USART2_RX             6U
+#define GPIOD_PIN7                  7U
+#define GPIOD_USART3_TX             8U
+#define GPIOD_USART3_RX             9U
+#define GPIOD_PIN10                 10U
+#define GPIOD_PIN11                 11U
+#define GPIOD_MB2_PWM               12U
+#define GPIOD_PIN13                 13U
+#define GPIOD_PIN14                 14U
+#define GPIOD_PIN15                 15U
+#define GPIOE_BUTTON1               0U
+#define GPIOE_PIN1                  1U
+#define GPIOE_PIN2                  2U
+#define GPIOE_PIN3                  3U
+#define GPIOE_PIN4                  4U
+#define GPIOE_PIN5                  5U
+#define GPIOE_PIN6                  6U
+#define GPIOE_MB1_RST               7U
+#define GPIOE_MB1_CS                8U
+#define GPIOE_MB1_PWM               9U
+#define GPIOE_MB1_INT               10U
+#define GPIOE_MB2_CS                11U
+#define GPIOE_LED1                  12U
+#define GPIOE_MB2_RST               13U
+#define GPIOE_MB2_INT               14U
+#define GPIOE_LED2                  15U
+#define GPIOF_PIN0                  0U
+#define GPIOF_PIN1                  1U
+#define GPIOF_PIN2                  2U
+#define GPIOF_PIN3                  3U
+#define GPIOF_PIN4                  4U
+#define GPIOF_PIN5                  5U
+#define GPIOF_PIN6                  6U
+#define GPIOF_PIN7                  7U
+#define GPIOF_PIN8                  8U
+#define GPIOF_PIN9                  9U
+#define GPIOF_PIN10                 10U
+#define GPIOF_PIN11                 11U
+#define GPIOF_PIN12                 12U
+#define GPIOF_PIN13                 13U
+#define GPIOF_PIN14                 14U
+#define GPIOF_PIN15                 15U
+#define GPIOG_PIN0                  0U
+#define GPIOG_PIN1                  1U
+#define GPIOG_PIN2                  2U
+#define GPIOG_PIN3                  3U
+#define GPIOG_PIN4                  4U
+#define GPIOG_PIN5                  5U
+#define GPIOG_PIN6                  6U
+#define GPIOG_PIN7                  7U
+#define GPIOG_PIN8                  8U
+#define GPIOG_PIN9                  9U
+#define GPIOG_PIN10                 10U
+#define GPIOG_PIN11                 11U
+#define GPIOG_PIN12                 12U
+#define GPIOG_PIN13                 13U
+#define GPIOG_PIN14                 14U
+#define GPIOG_PIN15                 15U
+#define GPIOH_PIN0                  0U
+#define GPIOH_PIN1                  1U
+#define GPIOH_PIN2                  2U
+#define GPIOH_PIN3                  3U
+#define GPIOH_PIN4                  4U
+#define GPIOH_PIN5                  5U
+#define GPIOH_PIN6                  6U
+#define GPIOH_PIN7                  7U
+#define GPIOH_PIN8                  8U
+#define GPIOH_PIN9                  9U
+#define GPIOH_PIN10                 10U
+#define GPIOH_PIN11                 11U
+#define GPIOH_PIN12                 12U
+#define GPIOH_PIN13                 13U
+#define GPIOH_PIN14                 14U
+#define GPIOH_PIN15                 15U
+#define GPIOI_PIN0                  0U
+#define GPIOI_PIN1                  1U
+#define GPIOI_PIN2                  2U
+#define GPIOI_PIN3                  3U
+#define GPIOI_PIN4                  4U
+#define GPIOI_PIN5                  5U
+#define GPIOI_PIN6                  6U
+#define GPIOI_PIN7                  7U
+#define GPIOI_PIN8                  8U
+#define GPIOI_PIN9                  9U
+#define GPIOI_PIN10                 10U
+#define GPIOI_PIN11                 11U
+#define GPIOI_PIN12                 12U
+#define GPIOI_PIN13                 13U
+#define GPIOI_PIN14                 14U
+#define GPIOI_PIN15                 15U
+/*
+ * IO lines assignments.
+ */
+#define LINE_MB1_AN                 PAL_LINE(GPIOA, 2U)
+#define LINE_MB2_AN                 PAL_LINE(GPIOA, 3U)
+#define LINE_I2C3_SCL               PAL_LINE(GPIOA, 8U)
+#define LINE_VBUS_FS                PAL_LINE(GPIOA, 9U)
+#define LINE_BUTTON2                PAL_LINE(GPIOA, 10U)
+#define LINE_OTG_FS_DM              PAL_LINE(GPIOA, 11U)
+#define LINE_OTG_FS_DP              PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO                  PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK                  PAL_LINE(GPIOA, 14U)
+#define LINE_I2C2_SCL               PAL_LINE(GPIOB, 10U)
+#define LINE_I2C2_SDA               PAL_LINE(GPIOB, 11U)
+#define LINE_SPI2_SCK               PAL_LINE(GPIOB, 13U)
+#define LINE_SPI2_MISO              PAL_LINE(GPIOB, 14U)
+#define LINE_SPI2_MOSI              PAL_LINE(GPIOB, 15U)
+#define LINE_I2C3_SDA               PAL_LINE(GPIOC, 9U)
+#define LINE_SPI3_SCK               PAL_LINE(GPIOC, 10U)
+#define LINE_SPI3_MISO              PAL_LINE(GPIOC, 11U)
+#define LINE_SPI3_MOSI              PAL_LINE(GPIOC, 12U)
+#define LINE_USART2_TX              PAL_LINE(GPIOD, 5U)
+#define LINE_USART2_RX              PAL_LINE(GPIOD, 6U)
+#define LINE_USART3_TX              PAL_LINE(GPIOD, 8U)
+#define LINE_USART3_RX              PAL_LINE(GPIOD, 9U)
+#define LINE_MB2_PWM                PAL_LINE(GPIOD, 12U)
+#define LINE_BUTTON1                PAL_LINE(GPIOE, 0U)
+#define LINE_MB1_RST                PAL_LINE(GPIOE, 7U)
+#define LINE_MB1_CS                 PAL_LINE(GPIOE, 8U)
+#define LINE_MB1_PWM                PAL_LINE(GPIOE, 9U)
+#define LINE_MB1_INT                PAL_LINE(GPIOE, 10U)
+#define LINE_MB2_CS                 PAL_LINE(GPIOE, 11U)
+#define LINE_LED1                   PAL_LINE(GPIOE, 12U)
+#define LINE_MB2_RST                PAL_LINE(GPIOE, 13U)
+#define LINE_MB2_INT                PAL_LINE(GPIOE, 14U)
+#define LINE_LED2                   PAL_LINE(GPIOE, 15U)
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n)           (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n)          (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n)       (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n)          (3U << ((n) * 2U))
+#define PIN_ODR_LOW(n)              (0U << (n))
+#define PIN_ODR_HIGH(n)             (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n)       (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n)      (1U << (n))
+#define PIN_OSPEED_VERYLOW(n)       (0U << ((n) * 2U))
+#define PIN_OSPEED_LOW(n)           (1U << ((n) * 2U))
+#define PIN_OSPEED_MEDIUM(n)        (2U << ((n) * 2U))
+#define PIN_OSPEED_HIGH(n)          (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n)       (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n)         (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n)       (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v)           ((v) << (((n) % 8U) * 4U))
+/*
+ * GPIOA setup:
+ *
+ * PA0  - PIN0                      (input pullup).
+ * PA1  - PIN1                      (input pullup).
+ * PA2  - MB1_AN                    (analog).
+ * PA3  - MB2_AN                    (analog).
+ * PA4  - PIN4                      (input pullup).
+ * PA5  - PIN5                      (input pullup).
+ * PA6  - PIN6                      (input pullup).
+ * PA7  - PIN7                      (input pullup).
+ * PA8  - I2C3_SCL                  (alternate 4).
+ * PA9  - VBUS_FS                   (input floating).
+ * PA10 - BUTTON2                   (input floating).
+ * PA11 - OTG_FS_DM                 (alternate 10).
+ * PA12 - OTG_FS_DP                 (alternate 10).
+ * PA13 - SWDIO                     (alternate 0).
+ * PA14 - SWCLK                     (alternate 0).
+ * PA15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOA_MODER             (PIN_MODE_INPUT(GPIOA_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN1) |           \
+                                     PIN_MODE_ANALOG(GPIOA_MB1_AN) |        \
+                                     PIN_MODE_ANALOG(GPIOA_MB2_AN) |        \
+                                     PIN_MODE_INPUT(GPIOA_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOA_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOA_I2C3_SCL) |   \
+                                     PIN_MODE_INPUT(GPIOA_VBUS_FS) |        \
+                                     PIN_MODE_INPUT(GPIOA_BUTTON2) |        \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) |  \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWDIO) |      \
+                                     PIN_MODE_ALTERNATE(GPIOA_SWCLK) |      \
+                                     PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MB1_AN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_MB2_AN) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_I2C3_SCL) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_VBUS_FS) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_BUTTON2) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR           (PIN_OSPEED_HIGH(GPIOA_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_MB1_AN) |        \
+                                     PIN_OSPEED_HIGH(GPIOA_MB2_AN) |        \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOA_I2C3_SCL) |      \
+                                     PIN_OSPEED_HIGH(GPIOA_VBUS_FS) |       \
+                                     PIN_OSPEED_HIGH(GPIOA_BUTTON2) |       \
+                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DM) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_OTG_FS_DP) |     \
+                                     PIN_OSPEED_HIGH(GPIOA_SWDIO) |         \
+                                     PIN_OSPEED_HIGH(GPIOA_SWCLK) |         \
+                                     PIN_OSPEED_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR             (PIN_PUPDR_PULLUP(GPIOA_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN1) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_MB1_AN) |     \
+                                     PIN_PUPDR_FLOATING(GPIOA_MB2_AN) |     \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOA_I2C3_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOA_VBUS_FS) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_BUTTON2) |    \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) |  \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWDIO) |      \
+                                     PIN_PUPDR_FLOATING(GPIOA_SWCLK) |      \
+                                     PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR               (PIN_ODR_HIGH(GPIOA_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOA_MB1_AN) |           \
+                                     PIN_ODR_HIGH(GPIOA_MB2_AN) |           \
+                                     PIN_ODR_HIGH(GPIOA_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOA_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOA_I2C3_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOA_VBUS_FS) |          \
+                                     PIN_ODR_HIGH(GPIOA_BUTTON2) |          \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DM) |        \
+                                     PIN_ODR_HIGH(GPIOA_OTG_FS_DP) |        \
+                                     PIN_ODR_HIGH(GPIOA_SWDIO) |            \
+                                     PIN_ODR_HIGH(GPIOA_SWCLK) |            \
+                                     PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL              (PIN_AFIO_AF(GPIOA_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOA_MB1_AN, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_MB2_AN, 0U) |        \
+                                     PIN_AFIO_AF(GPIOA_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOA_PIN7, 0U))
+#define VAL_GPIOA_AFRH              (PIN_AFIO_AF(GPIOA_I2C3_SCL, 4U) |      \
+                                     PIN_AFIO_AF(GPIOA_VBUS_FS, 0U) |       \
+                                     PIN_AFIO_AF(GPIOA_BUTTON2, 0U) |       \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10U) |    \
+                                     PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10U) |    \
+                                     PIN_AFIO_AF(GPIOA_SWDIO, 0U) |         \
+                                     PIN_AFIO_AF(GPIOA_SWCLK, 0U) |         \
+                                     PIN_AFIO_AF(GPIOA_PIN15, 0U))
+/*
+ * GPIOB setup:
+ *
+ * PB0  - PIN0                      (input pullup).
+ * PB1  - PIN1                      (input pullup).
+ * PB2  - PIN2                      (input pullup).
+ * PB3  - PIN3                      (input pullup).
+ * PB4  - PIN4                      (input pullup).
+ * PB5  - PIN5                      (input pullup).
+ * PB6  - PIN6                      (input pullup).
+ * PB7  - PIN7                      (input pullup).
+ * PB8  - PIN8                      (input pullup).
+ * PB9  - PIN9                      (input pullup).
+ * PB10 - I2C2_SCL                  (alternate 4).
+ * PB11 - I2C2_SDA                  (alternate 4).
+ * PB12 - PIN12                     (input pullup).
+ * PB13 - SPI2_SCK                  (alternate 5).
+ * PB14 - SPI2_MISO                 (alternate 14).
+ * PB15 - SPI2_MOSI                 (alternate 5).
+ */
+#define VAL_GPIOB_MODER             (PIN_MODE_INPUT(GPIOB_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOB_PIN9) |           \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C2_SCL) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_I2C2_SDA) |   \
+                                     PIN_MODE_INPUT(GPIOB_PIN12) |          \
+                                     PIN_MODE_ALTERNATE(GPIOB_SPI2_SCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOB_SPI2_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOB_SPI2_MOSI))
+#define VAL_GPIOB_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_I2C2_SCL) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_I2C2_SDA) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SPI2_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOB_SPI2_MOSI))
+#define VAL_GPIOB_OSPEEDR           (PIN_OSPEED_HIGH(GPIOB_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN9) |          \
+                                     PIN_OSPEED_HIGH(GPIOB_I2C2_SCL) |      \
+                                     PIN_OSPEED_HIGH(GPIOB_I2C2_SDA) |      \
+                                     PIN_OSPEED_HIGH(GPIOB_PIN12) |         \
+                                     PIN_OSPEED_HIGH(GPIOB_SPI2_SCK) |      \
+                                     PIN_OSPEED_HIGH(GPIOB_SPI2_MISO) |     \
+                                     PIN_OSPEED_HIGH(GPIOB_SPI2_MOSI))
+#define VAL_GPIOB_PUPDR             (PIN_PUPDR_PULLUP(GPIOB_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN9) |         \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C2_SCL) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_I2C2_SDA) |   \
+                                     PIN_PUPDR_PULLUP(GPIOB_PIN12) |        \
+                                     PIN_PUPDR_FLOATING(GPIOB_SPI2_SCK) |   \
+                                     PIN_PUPDR_FLOATING(GPIOB_SPI2_MISO) |  \
+                                     PIN_PUPDR_FLOATING(GPIOB_SPI2_MOSI))
+#define VAL_GPIOB_ODR               (PIN_ODR_HIGH(GPIOB_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOB_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOB_I2C2_SCL) |         \
+                                     PIN_ODR_HIGH(GPIOB_I2C2_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOB_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOB_SPI2_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOB_SPI2_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOB_SPI2_MOSI))
+#define VAL_GPIOB_AFRL              (PIN_AFIO_AF(GPIOB_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN7, 0U))
+#define VAL_GPIOB_AFRH              (PIN_AFIO_AF(GPIOB_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_PIN9, 0U) |          \
+                                     PIN_AFIO_AF(GPIOB_I2C2_SCL, 4U) |      \
+                                     PIN_AFIO_AF(GPIOB_I2C2_SDA, 4U) |      \
+                                     PIN_AFIO_AF(GPIOB_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOB_SPI2_SCK, 5U) |      \
+                                     PIN_AFIO_AF(GPIOB_SPI2_MISO, 14U) |    \
+                                     PIN_AFIO_AF(GPIOB_SPI2_MOSI, 5U))
+/*
+ * GPIOC setup:
+ *
+ * PC0  - PIN0                      (input pullup).
+ * PC1  - PIN1                      (input pullup).
+ * PC2  - PIN2                      (input pullup).
+ * PC3  - PIN3                      (input pullup).
+ * PC4  - PIN4                      (input pullup).
+ * PC5  - PIN5                      (input pullup).
+ * PC6  - PIN6                      (input pullup).
+ * PC7  - PIN7                      (input pullup).
+ * PC8  - PIN8                      (input pullup).
+ * PC9  - I2C3_SDA                  (alternate 4).
+ * PC10 - SPI3_SCK                  (alternate 6).
+ * PC11 - SPI3_MISO                 (alternate 6).
+ * PC12 - SPI3_MOSI                 (alternate 6).
+ * PC13 - PIN13                     (input pullup).
+ * PC14 - PIN14                     (input pullup).
+ * PC15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOC_MODER             (PIN_MODE_INPUT(GPIOC_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOC_PIN8) |           \
+                                     PIN_MODE_ALTERNATE(GPIOC_I2C3_SDA) |   \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) |   \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) |  \
+                                     PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) |  \
+                                     PIN_MODE_INPUT(GPIOC_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_I2C3_SDA) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_SCK) |   \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MISO) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_SPI3_MOSI) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR           (PIN_OSPEED_HIGH(GPIOC_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOC_I2C3_SDA) |      \
+                                     PIN_OSPEED_HIGH(GPIOC_SPI3_SCK) |      \
+                                     PIN_OSPEED_HIGH(GPIOC_SPI3_MISO) |     \
+                                     PIN_OSPEED_HIGH(GPIOC_SPI3_MOSI) |     \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR             (PIN_PUPDR_PULLUP(GPIOC_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN8) |         \
+                                     PIN_PUPDR_FLOATING(GPIOC_I2C3_SDA) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI3_SCK) |   \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI3_MISO) |  \
+                                     PIN_PUPDR_FLOATING(GPIOC_SPI3_MOSI) |  \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR               (PIN_ODR_HIGH(GPIOC_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOC_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOC_I2C3_SDA) |         \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_SCK) |         \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_MISO) |        \
+                                     PIN_ODR_HIGH(GPIOC_SPI3_MOSI) |        \
+                                     PIN_ODR_HIGH(GPIOC_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL              (PIN_AFIO_AF(GPIOC_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_PIN7, 0U))
+#define VAL_GPIOC_AFRH              (PIN_AFIO_AF(GPIOC_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOC_I2C3_SDA, 4U) |      \
+                                     PIN_AFIO_AF(GPIOC_SPI3_SCK, 6U) |      \
+                                     PIN_AFIO_AF(GPIOC_SPI3_MISO, 6U) |     \
+                                     PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6U) |     \
+                                     PIN_AFIO_AF(GPIOC_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOC_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOC_PIN15, 0U))
+/*
+ * GPIOD setup:
+ *
+ * PD0  - PIN0                      (input pullup).
+ * PD1  - PIN1                      (input pullup).
+ * PD2  - PIN2                      (input pullup).
+ * PD3  - PIN3                      (input pullup).
+ * PD4  - PIN4                      (input pullup).
+ * PD5  - USART2_TX                 (alternate 7).
+ * PD6  - USART2_RX                 (alternate 7).
+ * PD7  - PIN7                      (input pullup).
+ * PD8  - USART3_TX                 (alternate 7).
+ * PD9  - USART3_RX                 (alternate 7).
+ * PD10 - PIN10                     (input pullup).
+ * PD11 - PIN11                     (input pullup).
+ * PD12 - MB2_PWM                   (alternate 2).
+ * PD13 - PIN13                     (input pullup).
+ * PD14 - PIN14                     (input pullup).
+ * PD15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOD_MODER             (PIN_MODE_INPUT(GPIOD_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOD_PIN4) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_TX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART2_RX) |  \
+                                     PIN_MODE_INPUT(GPIOD_PIN7) |           \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART3_TX) |  \
+                                     PIN_MODE_ALTERNATE(GPIOD_USART3_RX) |  \
+                                     PIN_MODE_INPUT(GPIOD_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN11) |          \
+                                     PIN_MODE_ALTERNATE(GPIOD_MB2_PWM) |    \
+                                     PIN_MODE_INPUT(GPIOD_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_TX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART2_RX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART3_TX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_USART3_RX) |  \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_MB2_PWM) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR           (PIN_OSPEED_HIGH(GPIOD_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_USART2_TX) |     \
+                                     PIN_OSPEED_HIGH(GPIOD_USART2_RX) |     \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOD_USART3_TX) |     \
+                                     PIN_OSPEED_HIGH(GPIOD_USART3_RX) |     \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN10) |         \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN11) |         \
+                                     PIN_OSPEED_HIGH(GPIOD_MB2_PWM) |       \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR             (PIN_PUPDR_PULLUP(GPIOD_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN4) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_TX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART2_RX) |  \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN7) |         \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART3_TX) |  \
+                                     PIN_PUPDR_FLOATING(GPIOD_USART3_RX) |  \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN11) |        \
+                                     PIN_PUPDR_FLOATING(GPIOD_MB2_PWM) |    \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR               (PIN_ODR_HIGH(GPIOD_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOD_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOD_USART2_TX) |        \
+                                     PIN_ODR_HIGH(GPIOD_USART2_RX) |        \
+                                     PIN_ODR_HIGH(GPIOD_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOD_USART3_TX) |        \
+                                     PIN_ODR_HIGH(GPIOD_USART3_RX) |        \
+                                     PIN_ODR_HIGH(GPIOD_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOD_MB2_PWM) |          \
+                                     PIN_ODR_HIGH(GPIOD_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL              (PIN_AFIO_AF(GPIOD_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOD_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOD_USART2_TX, 7U) |     \
+                                     PIN_AFIO_AF(GPIOD_USART2_RX, 7U) |     \
+                                     PIN_AFIO_AF(GPIOD_PIN7, 0U))
+#define VAL_GPIOD_AFRH              (PIN_AFIO_AF(GPIOD_USART3_TX, 7U) |     \
+                                     PIN_AFIO_AF(GPIOD_USART3_RX, 7U) |     \
+                                     PIN_AFIO_AF(GPIOD_PIN10, 0U) |         \
+                                     PIN_AFIO_AF(GPIOD_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOD_MB2_PWM, 2U) |       \
+                                     PIN_AFIO_AF(GPIOD_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOD_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOD_PIN15, 0U))
+/*
+ * GPIOE setup:
+ *
+ * PE0  - BUTTON1                   (input floating).
+ * PE1  - PIN1                      (input pullup).
+ * PE2  - PIN2                      (input pullup).
+ * PE3  - PIN3                      (input pullup).
+ * PE4  - PIN4                      (input pullup).
+ * PE5  - PIN5                      (input pullup).
+ * PE6  - PIN6                      (input pullup).
+ * PE7  - MB1_RST                   (output pushpull maximum).
+ * PE8  - MB1_CS                    (output pushpull maximum).
+ * PE9  - MB1_PWM                   (alternate 1).
+ * PE10 - MB1_INT                   (input floating).
+ * PE11 - MB2_CS                    (output pushpull maximum).
+ * PE12 - LED1                      (output pushpull maximum).
+ * PE13 - MB2_RST                   (output pushpull maximum).
+ * PE14 - MB2_INT                   (input floating).
+ * PE15 - LED2                      (output pushpull maximum).
+ */
+#define VAL_GPIOE_MODER             (PIN_MODE_INPUT(GPIOE_BUTTON1) |        \
+                                     PIN_MODE_INPUT(GPIOE_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOE_PIN6) |           \
+                                     PIN_MODE_OUTPUT(GPIOE_MB1_RST) |       \
+                                     PIN_MODE_OUTPUT(GPIOE_MB1_CS) |        \
+                                     PIN_MODE_ALTERNATE(GPIOE_MB1_PWM) |    \
+                                     PIN_MODE_INPUT(GPIOE_MB1_INT) |        \
+                                     PIN_MODE_OUTPUT(GPIOE_MB2_CS) |        \
+                                     PIN_MODE_OUTPUT(GPIOE_LED1) |          \
+                                     PIN_MODE_OUTPUT(GPIOE_MB2_RST) |       \
+                                     PIN_MODE_INPUT(GPIOE_MB2_INT) |        \
+                                     PIN_MODE_OUTPUT(GPIOE_LED2))
+#define VAL_GPIOE_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOE_BUTTON1) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB1_RST) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB1_CS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB1_PWM) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB1_INT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB2_CS) |     \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB2_RST) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_MB2_INT) |    \
+                                     PIN_OTYPE_PUSHPULL(GPIOE_LED2))
+#define VAL_GPIOE_OSPEEDR           (PIN_OSPEED_HIGH(GPIOE_BUTTON1) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_MB1_RST) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_MB1_CS) |        \
+                                     PIN_OSPEED_HIGH(GPIOE_MB1_PWM) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_MB1_INT) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_MB2_CS) |        \
+                                     PIN_OSPEED_HIGH(GPIOE_LED1) |          \
+                                     PIN_OSPEED_HIGH(GPIOE_MB2_RST) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_MB2_INT) |       \
+                                     PIN_OSPEED_HIGH(GPIOE_LED2))
+#define VAL_GPIOE_PUPDR             (PIN_PUPDR_FLOATING(GPIOE_BUTTON1) |    \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOE_PIN6) |         \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB1_RST) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB1_CS) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB1_PWM) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB1_INT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB2_CS) |     \
+                                     PIN_PUPDR_FLOATING(GPIOE_LED1) |       \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB2_RST) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_MB2_INT) |    \
+                                     PIN_PUPDR_FLOATING(GPIOE_LED2))
+#define VAL_GPIOE_ODR               (PIN_ODR_HIGH(GPIOE_BUTTON1) |          \
+                                     PIN_ODR_HIGH(GPIOE_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOE_PIN6) |             \
+                                     PIN_ODR_LOW(GPIOE_MB1_RST) |           \
+                                     PIN_ODR_HIGH(GPIOE_MB1_CS) |           \
+                                     PIN_ODR_HIGH(GPIOE_MB1_PWM) |          \
+                                     PIN_ODR_HIGH(GPIOE_MB1_INT) |          \
+                                     PIN_ODR_HIGH(GPIOE_MB2_CS) |           \
+                                     PIN_ODR_LOW(GPIOE_LED1) |              \
+                                     PIN_ODR_LOW(GPIOE_MB2_RST) |           \
+                                     PIN_ODR_HIGH(GPIOE_MB2_INT) |          \
+                                     PIN_ODR_LOW(GPIOE_LED2))
+#define VAL_GPIOE_AFRL              (PIN_AFIO_AF(GPIOE_BUTTON1, 0U) |       \
+                                     PIN_AFIO_AF(GPIOE_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_MB1_RST, 0U))
+#define VAL_GPIOE_AFRH              (PIN_AFIO_AF(GPIOE_MB1_CS, 0U) |        \
+                                     PIN_AFIO_AF(GPIOE_MB1_PWM, 1U) |       \
+                                     PIN_AFIO_AF(GPIOE_MB1_INT, 0U) |       \
+                                     PIN_AFIO_AF(GPIOE_MB2_CS, 0U) |        \
+                                     PIN_AFIO_AF(GPIOE_LED1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOE_MB2_RST, 0U) |       \
+                                     PIN_AFIO_AF(GPIOE_MB2_INT, 0U) |       \
+                                     PIN_AFIO_AF(GPIOE_LED2, 0U))
+/*
+ * GPIOF setup:
+ *
+ * PF0  - PIN0                      (input pullup).
+ * PF1  - PIN1                      (input pullup).
+ * PF2  - PIN2                      (input pullup).
+ * PF3  - PIN3                      (input pullup).
+ * PF4  - PIN4                      (input pullup).
+ * PF5  - PIN5                      (input pullup).
+ * PF6  - PIN6                      (input pullup).
+ * PF7  - PIN7                      (input pullup).
+ * PF8  - PIN8                      (input pullup).
+ * PF9  - PIN9                      (input pullup).
+ * PF10 - PIN10                     (input pullup).
+ * PF11 - PIN11                     (input pullup).
+ * PF12 - PIN12                     (input pullup).
+ * PF13 - PIN13                     (input pullup).
+ * PF14 - PIN14                     (input pullup).
+ * PF15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOF_MODER             (PIN_MODE_INPUT(GPIOF_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOF_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR           (PIN_OSPEED_HIGH(GPIOF_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN9) |          \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN10) |         \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN11) |         \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN12) |         \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR             (PIN_PUPDR_PULLUP(GPIOF_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOF_PIN15))
+#define VAL_GPIOF_ODR               (PIN_ODR_HIGH(GPIOF_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOF_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL              (PIN_AFIO_AF(GPIOF_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN7, 0U))
+#define VAL_GPIOF_AFRH              (PIN_AFIO_AF(GPIOF_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN9, 0U) |          \
+                                     PIN_AFIO_AF(GPIOF_PIN10, 0U) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOF_PIN15, 0U))
+/*
+ * GPIOG setup:
+ *
+ * PG0  - PIN0                      (input pullup).
+ * PG1  - PIN1                      (input pullup).
+ * PG2  - PIN2                      (input pullup).
+ * PG3  - PIN3                      (input pullup).
+ * PG4  - PIN4                      (input pullup).
+ * PG5  - PIN5                      (input pullup).
+ * PG6  - PIN6                      (input pullup).
+ * PG7  - PIN7                      (input pullup).
+ * PG8  - PIN8                      (input pullup).
+ * PG9  - PIN9                      (input pullup).
+ * PG10 - PIN10                     (input pullup).
+ * PG11 - PIN11                     (input pullup).
+ * PG12 - PIN12                     (input pullup).
+ * PG13 - PIN13                     (input pullup).
+ * PG14 - PIN14                     (input pullup).
+ * PG15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOG_MODER             (PIN_MODE_INPUT(GPIOG_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOG_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOG_PIN15))
+#define VAL_GPIOG_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
+#define VAL_GPIOG_OSPEEDR           (PIN_OSPEED_HIGH(GPIOG_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN9) |          \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN10) |         \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN11) |         \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN12) |         \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_PUPDR             (PIN_PUPDR_PULLUP(GPIOG_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOG_PIN15))
+#define VAL_GPIOG_ODR               (PIN_ODR_HIGH(GPIOG_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOG_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOG_PIN15))
+#define VAL_GPIOG_AFRL              (PIN_AFIO_AF(GPIOG_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN7, 0U))
+#define VAL_GPIOG_AFRH              (PIN_AFIO_AF(GPIOG_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN9, 0U) |          \
+                                     PIN_AFIO_AF(GPIOG_PIN10, 0U) |         \
+                                     PIN_AFIO_AF(GPIOG_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOG_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOG_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOG_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOG_PIN15, 0U))
+/*
+ * GPIOH setup:
+ *
+ * PH0  - PIN0                      (input pullup).
+ * PH1  - PIN1                      (input pullup).
+ * PH2  - PIN2                      (input pullup).
+ * PH3  - PIN3                      (input pullup).
+ * PH4  - PIN4                      (input pullup).
+ * PH5  - PIN5                      (input pullup).
+ * PH6  - PIN6                      (input pullup).
+ * PH7  - PIN7                      (input pullup).
+ * PH8  - PIN8                      (input pullup).
+ * PH9  - PIN9                      (input pullup).
+ * PH10 - PIN10                     (input pullup).
+ * PH11 - PIN11                     (input pullup).
+ * PH12 - PIN12                     (input pullup).
+ * PH13 - PIN13                     (input pullup).
+ * PH14 - PIN14                     (input pullup).
+ * PH15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOH_MODER             (PIN_MODE_INPUT(GPIOH_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOH_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOH_PIN15))
+#define VAL_GPIOH_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOH_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
+#define VAL_GPIOH_OSPEEDR           (PIN_OSPEED_HIGH(GPIOH_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN9) |          \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN10) |         \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN11) |         \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN12) |         \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_PUPDR             (PIN_PUPDR_PULLUP(GPIOH_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOH_PIN15))
+#define VAL_GPIOH_ODR               (PIN_ODR_HIGH(GPIOH_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOH_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOH_PIN15))
+#define VAL_GPIOH_AFRL              (PIN_AFIO_AF(GPIOH_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN7, 0U))
+#define VAL_GPIOH_AFRH              (PIN_AFIO_AF(GPIOH_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN9, 0U) |          \
+                                     PIN_AFIO_AF(GPIOH_PIN10, 0U) |         \
+                                     PIN_AFIO_AF(GPIOH_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOH_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOH_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOH_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOH_PIN15, 0U))
+/*
+ * GPIOI setup:
+ *
+ * PI0  - PIN0                      (input pullup).
+ * PI1  - PIN1                      (input pullup).
+ * PI2  - PIN2                      (input pullup).
+ * PI3  - PIN3                      (input pullup).
+ * PI4  - PIN4                      (input pullup).
+ * PI5  - PIN5                      (input pullup).
+ * PI6  - PIN6                      (input pullup).
+ * PI7  - PIN7                      (input pullup).
+ * PI8  - PIN8                      (input pullup).
+ * PI9  - PIN9                      (input pullup).
+ * PI10 - PIN10                     (input pullup).
+ * PI11 - PIN11                     (input pullup).
+ * PI12 - PIN12                     (input pullup).
+ * PI13 - PIN13                     (input pullup).
+ * PI14 - PIN14                     (input pullup).
+ * PI15 - PIN15                     (input pullup).
+ */
+#define VAL_GPIOI_MODER             (PIN_MODE_INPUT(GPIOI_PIN0) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN1) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN2) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN3) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN4) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN5) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN6) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN7) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN8) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN9) |           \
+                                     PIN_MODE_INPUT(GPIOI_PIN10) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN11) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN12) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN13) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN14) |          \
+                                     PIN_MODE_INPUT(GPIOI_PIN15))
+#define VAL_GPIOI_OTYPER            (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN1) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN2) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN3) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN4) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN5) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN6) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN7) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN8) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN9) |       \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN10) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN11) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN12) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN13) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN14) |      \
+                                     PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
+#define VAL_GPIOI_OSPEEDR           (PIN_OSPEED_HIGH(GPIOI_PIN0) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN1) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN2) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN3) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN4) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN5) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN6) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN7) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN8) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN9) |          \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN10) |         \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN11) |         \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN12) |         \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN13) |         \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN14) |         \
+                                     PIN_OSPEED_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_PUPDR             (PIN_PUPDR_PULLUP(GPIOI_PIN0) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN1) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN2) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN3) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN4) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN5) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN6) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN7) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN8) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN9) |         \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN10) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN11) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN12) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN13) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN14) |        \
+                                     PIN_PUPDR_PULLUP(GPIOI_PIN15))
+#define VAL_GPIOI_ODR               (PIN_ODR_HIGH(GPIOI_PIN0) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN1) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN2) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN3) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN4) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN5) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN6) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN7) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN8) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN9) |             \
+                                     PIN_ODR_HIGH(GPIOI_PIN10) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN11) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN12) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN13) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN14) |            \
+                                     PIN_ODR_HIGH(GPIOI_PIN15))
+#define VAL_GPIOI_AFRL              (PIN_AFIO_AF(GPIOI_PIN0, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN1, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN2, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN3, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN4, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN5, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN6, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN7, 0U))
+#define VAL_GPIOI_AFRH              (PIN_AFIO_AF(GPIOI_PIN8, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN9, 0U) |          \
+                                     PIN_AFIO_AF(GPIOI_PIN10, 0U) |         \
+                                     PIN_AFIO_AF(GPIOI_PIN11, 0U) |         \
+                                     PIN_AFIO_AF(GPIOI_PIN12, 0U) |         \
+                                     PIN_AFIO_AF(GPIOI_PIN13, 0U) |         \
+                                     PIN_AFIO_AF(GPIOI_PIN14, 0U) |         \
+                                     PIN_AFIO_AF(GPIOI_PIN15, 0U))
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.mk b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.mk
new file mode 100644
index 000000000..ade34733b
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = $(CHIBIOS)/os/hal/boards/MIKROE_CLICKER2_STM32/board.c
+# Required include directories
+BOARDINC = $(CHIBIOS)/os/hal/boards/MIKROE_CLICKER2_STM32
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.chcfg b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.chcfg
new file mode 100644
index 000000000..126d37c84
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.chcfg
@@ -0,0 +1,1193 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- STM32F4xx board Template -->
+<board
+  xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
+  xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+  <configuration_settings>
+    <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+    <output_path>..</output_path>
+    <hal_version>5.0.x</hal_version>
+  </configuration_settings>
+  <board_name>Mikroe Clicker 2 for STM32</board_name>
+  <board_id>MIKROE_CLICKER2_STM32</board_id>
+  <board_functions></board_functions>
+  <subtype>STM32F407xx</subtype>
+  <clocks 
+    HSEFrequency="25000000" 
+    HSEBypass="false" 
+    LSEFrequency="32768" 
+    LSEBypass="false" 
+    VDD="300" />  
+  <ports>
+    <GPIOA>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID="MB1_AN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Analog"
+        Alternate="0" />
+      <pin3
+        ID="MB2_AN"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Analog"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="I2C3_SCL"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin9
+        ID="VBUS_FS "
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="BUTTON2"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID="OTG_FS_DM"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin12
+        ID="OTG_FS_DP"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="10" />
+      <pin13
+        ID="SWDIO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin14
+        ID="SWCLK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOA>
+    <GPIOB>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID="I2C2_SCL"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin11
+        ID="I2C2_SDA"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID="SPI2_SCK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+      <pin14
+        ID="SPI2_MISO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="14" />
+      <pin15
+        ID="SPI2_MOSI"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="5" />
+    </GPIOB>
+    <GPIOC>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID="I2C3_SDA"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="4" />
+      <pin10
+        ID="SPI3_SCK"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin11
+        ID="SPI3_MISO"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin12
+        ID="SPI3_MOSI"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="6" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOC>
+    <GPIOD>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID="USART2_TX"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin6
+        ID="USART2_RX"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID="USART3_TX"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin9
+        ID="USART3_RX"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="7" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID="MB2_PWM"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="2" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOD>
+    <GPIOE>
+      <pin0
+        ID="BUTTON1"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID="MB1_RST"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin8
+        ID="MB1_CS"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin9
+        ID="MB1_PWM"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Alternate"
+        Alternate="1" />
+      <pin10
+        ID="MB1_INT"
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID='MB2_CS'
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin12
+        ID="LED1"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin13
+        ID='MB2_RST'
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+      <pin14
+        ID='MB2_INT'
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID="LED2"
+        Type="PushPull"
+        Level="Low"
+        Speed="Maximum"
+        Resistor="Floating"
+        Mode="Output"
+        Alternate="0" />
+    </GPIOE>
+    <GPIOF>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOF>
+    <GPIOG>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOG>
+    <GPIOH>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOH>
+    <GPIOI>
+      <pin0
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin1
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin2
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin3
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin4
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin5
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin6
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin7
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin8
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin9
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin10
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin11
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin12
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin13
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin14
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+      <pin15
+        ID=""
+        Type="PushPull"
+        Level="High"
+        Speed="Maximum"
+        Resistor="PullUp"
+        Mode="Input"
+        Alternate="0" />
+    </GPIOI>
+  </ports>
+</board>
diff --git a/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.fmpp b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.fmpp
new file mode 100644
index 000000000..41754c141
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MIKROE_CLICKER2_STM32/cfg/board.fmpp
@@ -0,0 +1,15 @@
+sourceRoot: ../../../../../tools/ftl/processors/boards/stm32f4xx/templates
+outputRoot: ..
+dataRoot: .
+freemarkerLinks: {
+    lib: ../../../../../tools/ftl/libs
+}
+data : {
+  doc1:xml (
+    board.chcfg
+    {
+    }
+  )
+}
diff --git a/lib/chibios/os/hal/boards/MT-DB-X4/board.c b/lib/chibios/os/hal/boards/MT-DB-X4/board.c
new file mode 100644
index 000000000..c97fe5280
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MT-DB-X4/board.c
@@ -0,0 +1,68 @@
+/*
+    ChibiOS - Copyright (C) 2017 Theodore Ateba
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+#if defined(PORTH)
+  {VAL_PORTH, VAL_DDRH},
+#endif
+#if defined(PORTJ)
+  {VAL_PORTJ, VAL_DDRJ},
+#endif
+#if defined(PORTK)
+  {VAL_PORTK, VAL_DDRK},
+#endif
+#if defined(PORTL)
+  {VAL_PORTL, VAL_DDRL},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/lib/chibios/os/hal/boards/MT-DB-X4/board.h b/lib/chibios/os/hal/boards/MT-DB-X4/board.h
new file mode 100644
index 000000000..2b508f0f8
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MT-DB-X4/board.h
@@ -0,0 +1,86 @@
+/*
+    ChibiOS - Copyright (C) 2017 Theodore Ateba
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef BOARD_H
+#define BOARD_H
+/*
+ * Setup for the Mattair board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_MT_DB_X4
+#define BOARD_NAME  "MT-DB-X4 board"
+/* All inputs with pull-ups */
+#define VAL_DDRA    0x00
+#define VAL_PORTA   0xFF
+/* All inputs. */
+#define VAL_DDRB    0x00
+#define VAL_PORTB   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRC    0x00
+#define VAL_PORTC   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRD    0x00
+#define VAL_PORTD   0xFF
+/* All inputs except PE1 wich has a LED connected. */
+#define VAL_DDRE    0x02
+#define VAL_PORTE   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRF    0x00
+#define VAL_PORTF   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRG    0x00
+#define VAL_PORTG   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRH    0x00
+#define VAL_PORTH   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRJ    0x00
+#define VAL_PORTJ   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRK    0x00
+#define VAL_PORTK   0xFF
+/* All inputs with pull-ups */
+#define VAL_DDRL    0x00
+#define VAL_PORTL   0xFF
+#define PORTE_LED   1
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* BOARD_H */
diff --git a/lib/chibios/os/hal/boards/MT-DB-X4/board.mk b/lib/chibios/os/hal/boards/MT-DB-X4/board.mk
new file mode 100644
index 000000000..46b221a60
--- /dev/null
+++ b/lib/chibios/os/hal/boards/MT-DB-X4/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/MT-DB-X4/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/MT-DB-X4
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.c b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.c
new file mode 100644
index 000000000..65c164809
--- /dev/null
+++ b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.c
@@ -0,0 +1,60 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+  {VAL_GPIO0DATA, VAL_GPIO0DIR},
+  {VAL_GPIO1DATA, VAL_GPIO1DIR}
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+__inline void __early_init(void) {
+  lpc_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+__inline void boardInit(void) {
+  /* LCD */
+  LPC_IOCON->TMS_PIO0_12  = 0x91;       /* LCD_EN: GPIO - pull-up     */
+  LPC_IOCON->TDO_PIO0_13  = 0x81;       /* LCD_RW: GPIO - No pull-up  */
+  LPC_IOCON->TRST_PIO0_14 = 0x81;       /* LCD_RS: GPIO - No pull-up  */
+  /* USART */
+  LPC_IOCON->PIO0_18 = 0x81;            /* RDX: RXD - No pull-up      */
+  LPC_IOCON->PIO0_19 = 0x81;            /* TDX: TXD - No pull-up      */
+  /* Test LEDs */
+  LPC_IOCON->PIO0_22 = 0x80;            /* LED_TEST1: GPIO - No pull-up */
+  LPC_IOCON->PIO0_23 = 0x80;            /* LED_TEST2: GPIO - No pull-up */
+}
diff --git a/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.h b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.h
new file mode 100644
index 000000000..15d9dce2a
--- /dev/null
+++ b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.h
@@ -0,0 +1,125 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for NGX BlueBoard LPC11U14.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_NGX_BB_LPC11U14
+#define BOARD_NAME "NGX BlueBoard LPC11U14"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * Pin definitions.
+ */
+ 
+/* GPIO Port0 */
+#define BUTTON_ISP_PORT       GPIO0
+#define BUTTON_ISP            1
+#define LCD_ERD_PORT          GPIO0
+#define LCD_ERD               12
+#define LCD_RWR_PORT          GPIO0
+#define LCD_RWR               13
+#define LCD_RS_PORT           GPIO0
+#define LCD_RS                14
+#define LED_PORT              GPIO0
+#define LED_TEST1             22
+#define LED_TEST2             23
+/* GPIO Port1 */
+#define LCD_RST_PORT          GPIO1
+#define LCD_RST               0
+#define LCD_CS_PORT           GPIO1
+#define LCD_CS                13
+#define LCD_BL_PORT           GPIO1
+#define LCD_BL                14
+#define LCD_VCCEN_PORT        GPIO1
+#define LCD_VCCEN             14
+#define WHEEL_SENSOR_PORT     GPIO0
+#define WHEEL_SENSOR          21
+#define LCD_DATA_PORT         GPIO1
+#define LCD_D0                19
+#define LCD_D1                20
+#define LCD_D2                21
+#define LCD_D3                22
+#define LCD_D4                26
+#define LCD_D5                27
+#define LCD_D6                28
+#define LCD_D7                31
+#define LCD_DATA_MASK           PAL_PORT_BIT(LCD_D0)  | \
+                                PAL_PORT_BIT(LCD_D1)  | \
+                                PAL_PORT_BIT(LCD_D2)  | \
+                                PAL_PORT_BIT(LCD_D3)  | \
+                                PAL_PORT_BIT(LCD_D4)  | \
+                                PAL_PORT_BIT(LCD_D5)  | \
+                                PAL_PORT_BIT(LCD_D6)  | \
+                                PAL_PORT_BIT(LCD_D7)
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            PAL_PORT_BIT(LCD_ERD)   | \
+                                PAL_PORT_BIT(LCD_RWR)   | \
+                                PAL_PORT_BIT(LCD_RS)    | \
+                                PAL_PORT_BIT(LED_TEST1) | \
+                                PAL_PORT_BIT(LED_TEST2)
+                                
+#define VAL_GPIO0DATA           PAL_PORT_BIT(LCD_ERD)   | \
+                                PAL_PORT_BIT(LCD_RWR)   | \
+                                PAL_PORT_BIT(LED_TEST1) | \
+                                PAL_PORT_BIT(LED_TEST2)
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(LCD_RST) | \
+                                PAL_PORT_BIT(LCD_CS)  | \
+                                PAL_PORT_BIT(LCD_BL)  | \
+                                LCD_DATA_MASK
+                                
+#define VAL_GPIO1DATA           0x00000000
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif
+#endif
diff --git a/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.mk b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.mk
new file mode 100644
index 000000000..33e91044b
--- /dev/null
+++ b/lib/chibios/os/hal/boards/NGX_BB_LPC11U14/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/NGX_BB_LPC11U14/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/NGX_BB_LPC11U14
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.c b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.c
new file mode 100644
index 000000000..e41d9809a
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.c
@@ -0,0 +1,89 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+  CH_IRQ_PROLOGUE();
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+  CH_IRQ_EPILOGUE();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+  /*
+   * Enables Idle mode for SLEEP instruction.
+   */
+  SMCR   = (1 << SE);
+  /*
+   * Timer 0 setup.
+   */
+  TCCR0A = (1 << WGM01)  | (0 << WGM00)  |              /* CTC mode.        */
+           (0 << COM0A1) | (0 << COM0A0) |              /* OC0A disabled.   */
+           (0 << CS02)   | (1 << CS01)   | (1 << CS00); /* CLK/64 clock.    */
+  OCR0A  = F_CPU / 64 / CH_FREQUENCY - 1;
+  TCNT0  = 0;                                           /* Reset counter.   */
+  TIFR0  = (1 << OCF0A);                                /* Reset pending.   */
+  TIMSK0 = (1 << OCIE0A);                               /* IRQ on compare.  */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.h b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.h
new file mode 100644
index 000000000..b87bc472d
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.h
@@ -0,0 +1,99 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Olimex AVR-CAN proto board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_CAN
+#define BOARD_NAME "Olimex AVR-CAN"
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRA  0x00
+#define VAL_PORTA 0xFF
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB  0x00
+#define VAL_PORTB 0xFF
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRC  0x00
+#define VAL_PORTC 0xFF
+/*       PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
+ *        IN  IN OUT  IN OUT  IN  IN  IN
+ * DDRD    0   0   1   0   1   0   0   0
+ *        PU HiZ VAL  PU VAL HiZ HiZ HiZ
+ * PORTD   1   0  ?1   1   1   0   0   0
+ */
+#define VAL_DDRD  0x28
+#define VAL_PORTD 0xB8
+/*       PE7 PE6 BUT LED PE3 PE2 PE1 PE0
+ *        IN  IN  IN OUT  IN  IN OUT  IN
+ * DDRE    0   0   0   1   0   0   1   0
+ *        PU  PU HiZ VAL  PU  PU VAL HiZ
+ * PORTE   1   1   0   1   1   1   1   0
+ */
+#define VAL_DDRE  0x12
+#define VAL_PORTE 0xDE
+/*       TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ *         x   x   x   x  IN  IN  IN  IN
+ * DDRF    0   0   0   0   0   0   0   0
+ *         x   x   x   x  PU  PU  PU  PU
+ * PORTF   0   0   0   0   1   1   1   1
+ *
+ */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0x0F
+/*         x   x   x   x   x PG2 PG1 PG0
+ *         x   x   x   x   x  IN  IN  IN
+ * DDRG    0   0   0   0   0   0   0   0
+ *         x   x   x   x   x  PU  PU  PU
+ * PORTG   0   0   0   0   0   1   1   1
+ *
+ */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0x07
+#define PORTE_LED               4
+#define PORTE_BUTTON            5
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.mk b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.mk
new file mode 100644
index 000000000..d9aad6e5a
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_CAN/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_CAN/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_CAN
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.c b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.c
new file mode 100644
index 000000000..4aeae736b
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.c
@@ -0,0 +1,92 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(PORTA)
+  {VAL_PORTA, VAL_DDRA},
+#endif
+#if defined(PORTB)
+  {VAL_PORTB, VAL_DDRB},
+#endif
+#if defined(PORTC)
+  {VAL_PORTC, VAL_DDRC},
+#endif
+#if defined(PORTD)
+  {VAL_PORTD, VAL_DDRD},
+#endif
+#if defined(PORTE)
+  {VAL_PORTE, VAL_DDRE},
+#endif
+#if defined(PORTF)
+  {VAL_PORTF, VAL_DDRF},
+#endif
+#if defined(PORTG)
+  {VAL_PORTG, VAL_DDRG},
+#endif
+};
+#endif /* HAL_USE_PAL */
+/**
+ * @brief   Timer0 interrupt handler.
+ */
+CH_IRQ_HANDLER(TIMER0_COMP_vect) {
+  CH_IRQ_PROLOGUE();
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+  CH_IRQ_EPILOGUE();
+}
+/**
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * External interrupts setup, all disabled initially.
+   */
+  EICRA  = 0x00;
+  EICRB  = 0x00;
+  EIMSK  = 0x00;
+  /*
+   * Enables Idle mode for SLEEP instruction.
+   */
+  MCUCR  = (1 << SE);
+  /*
+   * Timer 0 setup.
+   */
+  TCCR0  = (1 << WGM01) | (0 << WGM00) |                /* CTC mode.        */
+           (0 << COM01) | (0 << COM00) |                /* OC0A disabled.   */
+           (1 << CS02)  | (0 << CS01)  | (0 << CS00);   /* CLK/64 clock.    */
+  OCR0   = F_CPU / 64 / CH_FREQUENCY - 1;
+  TCNT0  = 0;                                           /* Reset counter.   */
+  TIFR   = (1 << OCF0);                                 /* Reset pending.   */
+  TIMSK  = (1 << OCIE0);                                /* IRQ on compare.  */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.h b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.h
new file mode 100644
index 000000000..2526949de
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.h
@@ -0,0 +1,124 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Olimex AVR-MT-128 proto board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_AVR_MT_128
+#define BOARD_NAME "Olimex AVR-MT-128"
+/*       PA7 RLY  DS  B5  B4  B3  B2  B1
+ *        IN OUT  IN  IN  IN  IN  IN  IN
+ * DDRA    0   1   0   0   0   0   0   0
+ *        PU VAL HiZ HiZ HiZ HiZ HiZ HiZ
+ * PORTA   1   0   0   0   0   0   0   0
+ */
+#define VAL_DDRA  0x40
+#define VAL_PORTA 0x80
+/*
+ * All inputs with pullups.
+ */
+#define VAL_DDRB  0x00
+#define VAL_PORTB 0xFF
+/*        D7  D6  D5  D4 PC3   E R/W  RS
+ *        OUT OUT OUT OUT IN OUT OUT OUT
+ * DDRC    1   1   1   1   0   1   1   1
+ *        PU  PU  PU  PU  PU VAL VAL VAL
+ * PORTC   0   0   0   0   1   0   0   0
+ */
+#define VAL_DDRC  0xF7
+#define VAL_PORTC 0x08
+/*       PD7 PD6 PD5 PD4 TXD RXD PD1 PD0
+ *        IN  IN  IN  IN OUT  IN  IN  IN
+ * DDRD    0   0   0   0   1   0   0   0
+ *        PU  PU  PU  PU VAL HiZ  PU  PU
+ * PORTD   1   1   1   1   1   0   1   1
+ */
+#define VAL_DDRD  0x08
+#define VAL_PORTD 0xFB
+/*       PE7 PE6 BZ2 BZ2 PE3 PE2 PE1 PE0
+ *        IN  IN OUT OUT  IN  IN OUT  IN
+ * DDRE    0   0   1   1   0   0   1   0
+ *        PU  PU VAL VAL  PU  PU VAL  PU
+ * PORTE   1   1   1   1   1   1   1   1
+ */
+#define VAL_DDRE  0x32
+#define VAL_PORTE 0xFF
+/*       TDI TDO TMS TCK PF3 PF2 PF1 PF0
+ *         x   x   x   x  IN  IN  IN  IN
+ * DDRF    0   0   0   0   0   0   0   0
+ *         x   x   x   x  PU  PU  PU  PU
+ * PORTF   0   0   0   0   1   1   1   1
+ *
+ */
+#define VAL_DDRF  0x00
+#define VAL_PORTF 0x0F
+/*         x   x   x   x   x PG2 PG1 PG0
+ *         x   x   x   x   x  IN  IN  IN
+ * DDRG    0   0   0   0   0   0   0   0
+ *         x   x   x   x   x  PU  PU  PU
+ * PORTG   0   0   0   0   0   1   1   1
+ *
+ */
+#define VAL_DDRG  0x00
+#define VAL_PORTG 0x07
+#define PORTA_BUTTON1           0
+#define PORTA_BUTTON2           1
+#define PORTA_BUTTON3           2
+#define PORTA_BUTTON4           3
+#define PORTA_BUTTON5           4
+#define PORTA_DALLAS            5
+#define PORTA_RELAY             6
+#define PORTC_44780_RS_MASK     (1 << 0)
+#define PORTC_44780_RW_MASK     (1 << 1)
+#define PORTC_44780_E_MASK      (1 << 2)
+#define PORTC_44780_D4_MASK     (1 << 4)
+#define PORTC_44780_D5_MASK     (1 << 5)
+#define PORTC_44780_D6_MASK     (1 << 6)
+#define PORTC_44780_D7_MASK     (1 << 7)
+#define PORTC_44780_DATA_MASK   (PORTC_44780_D4_MASK | PORTC_44780_D5_MASK | \
+                                 PORTC_44780_D6_MASK | PORTC_44780_D7_MASK)
+#define PORTE_BUZZ1             (1 << 4)
+#define PORTE_BUZZ2             (1 << 5)
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.mk b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.mk
new file mode 100644
index 000000000..902aad520
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_AVR_MT_128/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_MT_128/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_AVR_MT_128
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.c b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.c
new file mode 100644
index 000000000..81656d4e3
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.c
@@ -0,0 +1,53 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  lpc122x_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   */
+  LPC_IOCON->PIO1_4 = 0x80;             /* Disables pull-up on LED2 output. */
+  LPC_IOCON->PIO1_5 = 0x80;             /* Disables pull-up on LED1 output  */
+  LPC_IOCON->PIO1_6 = 0x80;             /* Disables pull-up on Buzzer output  */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.h b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.h
new file mode 100644
index 000000000..002a2cfad
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.h
@@ -0,0 +1,94 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for Olimex LPC-P1227 board.
+ *
+ */
+/*
+ * Board identifiers.
+ */
+#define OLIMEX_LPC_P1227
+#define BOARD_NAME "Olimex LPC-P1227"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            0x00000000
+#define VAL_GPIO0DATA           0x00000000
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_LED1)   |                 \
+                                PAL_PORT_BIT(GPIO1_LED2)   |                 \
+                                PAL_PORT_BIT(GPIO1_BUZZER)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_LED1)
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            PAL_PORT_BIT(GPIO2_LCD_DC)   |               \
+                                PAL_PORT_BIT(GPIO2_LCD_SS)   |               \
+                                PAL_PORT_BIT(GPIO2_LCD_RES)
+#define VAL_GPIO2DATA           PAL_PORT_BIT(GPIO2_LCD_SS)
+/*
+ * Pin definitions.
+ */
+#define GPIO1_LED1              5
+#define GPIO1_LED2              4
+#define GPIO1_SW_WAKEUP         3
+#define GPIO1_BUZZER            6
+#define GPIO2_SW_USER1          12
+#define GPIO2_SW_USER2          11
+#define GPIO2_SW_USER3          10
+#define GPIO2_LCD_DC            15
+#define GPIO2_LCD_SS            14
+#define GPIO2_LCD_RES           13
+/* LCD3310 pins */
+#define LCD3310_RES_PIN   GPIO2_LCD_RES
+#define LCD3310_RES_PORT  GPIO2
+#define LCD3310_DC_PIN    GPIO2_LCD_DC
+#define LCD3310_DC_PORT   GPIO2
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.mk b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.mk
new file mode 100644
index 000000000..0b49d51e0
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1227/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC-P1227/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC-P1227
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.c b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.c
new file mode 100644
index 000000000..534752001
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.c
@@ -0,0 +1,51 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config = {
+ {VAL_GPIO0DATA, VAL_GPIO0DIR},
+ {VAL_GPIO1DATA, VAL_GPIO1DIR},
+ {VAL_GPIO2DATA, VAL_GPIO2DIR},
+ {VAL_GPIO3DATA, VAL_GPIO3DIR},
+};
+#endif
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  LPC13xx_clock_init();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * Extra, board-specific, initializations.
+   */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.h b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.h
new file mode 100644
index 000000000..1eae8715a
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.h
@@ -0,0 +1,104 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Olimex LPC-P1343 proto board.
+ */
+/*
+ * Board identifiers.
+ */
+#define BOARD_OLIMEX_LPC_P1343
+#define BOARD_NAME "Olimex LPC-P1343"
+/*
+ * Board frequencies.
+ */
+#define SYSOSCCLK               12000000
+/*
+ * GPIO 0 initial setup.
+ */
+#define VAL_GPIO0DIR            0x00000000
+#define VAL_GPIO0DATA           0x00000000
+/*
+ * GPIO 1 initial setup.
+ */
+#define VAL_GPIO1DIR            PAL_PORT_BIT(GPIO1_SW2)
+#define VAL_GPIO1DATA           PAL_PORT_BIT(GPIO1_SW2)
+/*
+ * GPIO 2 initial setup.
+ */
+#define VAL_GPIO2DIR            PAL_PORT_BIT(GPIO2_SW1)     | \
+                                PAL_PORT_BIT(GPIO2_LED5)    | \
+                                PAL_PORT_BIT(GPIO2_LED6)    | \
+                                PAL_PORT_BIT(GPIO2_LED7)    | \
+                                PAL_PORT_BIT(GPIO2_LED8)
+#define VAL_GPIO2DATA           PAL_PORT_BIT(GPIO2_LED5)    | \
+                                PAL_PORT_BIT(GPIO2_LED6)    | \
+                                PAL_PORT_BIT(GPIO2_LED7)    | \
+                                PAL_PORT_BIT(GPIO2_LED8)
+/*
+ * GPIO 3 initial setup.
+ */
+#define VAL_GPIO3DIR            PAL_PORT_BIT(GPIO3_LED1)    | \
+                                PAL_PORT_BIT(GPIO3_LED2)    | \
+                                PAL_PORT_BIT(GPIO3_LED3)    | \
+                                PAL_PORT_BIT(GPIO3_LED4)
+#define VAL_GPIO3DATA           PAL_PORT_BIT(GPIO3_LED1)    | \
+                                PAL_PORT_BIT(GPIO3_LED2)    | \
+                                PAL_PORT_BIT(GPIO3_LED3)    | \
+                                PAL_PORT_BIT(GPIO3_LED4)
+/*
+ * Pin definitions.
+ */
+#define GPIO1_SW2               4
+#define GPIO1_SPI0SEL           11
+#define GPIO2_SW1               9
+#define GPIO3_LED1              0
+#define GPIO3_LED2              1
+#define GPIO3_LED3              2
+#define GPIO3_LED4              3
+#define GPIO2_LED5              4
+#define GPIO2_LED6              5
+#define GPIO2_LED7              6
+#define GPIO2_LED8              7
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.mk b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.mk
new file mode 100644
index 000000000..629e92be6
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P1343/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P1343/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P1343
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.c b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.c
new file mode 100644
index 000000000..5060e41ab
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.c
@@ -0,0 +1,94 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+#define VAL_TC0_PRESCALER 0
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  VAL_PINSEL0,
+  VAL_PINSEL1,
+  VAL_PINSEL2,
+  {VAL_FIO0PIN, VAL_FIO0DIR},
+  {VAL_FIO1PIN, VAL_FIO1DIR}
+};
+#endif
+/*
+ * Timer 0 IRQ handling here.
+ */
+static CH_IRQ_HANDLER(T0IrqHandler) {
+  CH_IRQ_PROLOGUE();
+  T0IR = 1;             /* Clear interrupt on match MR0. */
+  chSysLockFromISR();
+  chSysTimerHandlerI();
+  chSysUnlockFromISR();
+  VICVectAddr = 0;
+  CH_IRQ_EPILOGUE();
+}
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  lpc214x_clock_init();
+}
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  return !palReadPad(IOPORT2, PB_CP1);
+}
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  return palReadPad(IOPORT2, PB_WP1);
+}
+#endif
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * System Timer initialization, 1ms intervals.
+   */
+  SetVICVector(T0IrqHandler, 0, SOURCE_Timer0);
+  VICIntEnable = INTMASK(SOURCE_Timer0);
+  TC *timer = T0Base;
+  timer->TC_PR = VAL_TC0_PRESCALER;
+  timer->TC_MR0 = (PCLK / CH_CFG_ST_FREQUENCY) / (VAL_TC0_PRESCALER + 1);
+  timer->TC_MCR = 3;    /* Interrupt and clear TC on match MR0. */
+  timer->TC_TCR = 2;    /* Reset counter and prescaler. */
+  timer->TC_TCR = 1;    /* Timer enabled. */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.h b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.h
new file mode 100644
index 000000000..3fe3f4d1d
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.h
@@ -0,0 +1,92 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Olimex LPC-P2148 proto board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_LPC_P2148
+#define BOARD_NAME "Olimex LPC-P2148"
+/*
+ * The following values are implementation dependent. You may change them in
+ * order to match your HW.
+ */
+#define FOSC 12000000
+#define CCLK 48000000
+#define PCLK 12000000
+/*
+ * Pins configuration for Olimex LPC-P2148.
+ *
+ * PINSEL0
+ *  P0  P0  P0  P0  P0  P0  RXD TXD SSE MOS MIS SCK SDA SCL RXD TXD
+ *  15  14  13  12  11  10  1   1   L0  I0  O0  0   0   0   0   0
+ *  00  00  00  00  00  00  01  01  01  01  01  01  01  01  01  01
+ * FIO0DIR (15...0)
+ *  IN  IN  OUT OUT OUT OUT --  --  --  --  --  --  --  --  --  --
+ *  0   0   1   1   1   1   0   0   0   0   0   0   0   0   0   0
+ *
+ * PINSEL1
+ *  P0  AD  P0  P0  --  --  AO  --  VB  P0  P0  P0  MOS MIS SCK P0
+ *  31  03  29  28  --  --  UT  --  US  22  21  20  I1  O1  1   16
+ *  00  01  00  00  00  00  10  00  01  00  00  00  10  10  10  00
+ * FIO0DIR (31...16)
+ *  OUT --  OUT OUT --  --  --  --  --  OUT OUT OUT --  --  --  IN
+ *  1   0   1   1   0   0   0   0   0   1   1   1   0   0   0   0
+ *
+ * FIO1DIR (31...16)
+ *  --  --  --  --  --  IN  IN  OUT OUT OUT OUT OUT OUT OUT OUT OUT
+ *  0   0   0   0   0   0   0   1   1   1   1   1   1   1   1   1
+ */
+#define VAL_PINSEL0 0x00055555
+#define VAL_PINSEL1 0x100840A8
+#define VAL_PINSEL2 0x00000004  /* Do not modify */
+#define VAL_FIO0DIR 0xB0703C00
+#define VAL_FIO1DIR 0x01FF0000
+#define VAL_FIO0PIN 0xFFFFFFFF
+#define VAL_FIO1PIN 0xFFFFFFFF
+#define PA_LED1         10
+#define PA_LED2         11
+#define PA_BUZZ1        12
+#define PA_BUZZ2        13
+#define PA_BSL          14
+#define PA_BUTTON1      15
+#define PA_BUTTON2      16
+#define PA_SSEL1        20
+#define PA_LEDUSB       31
+#define PB_WP1          24
+#define PB_CP1          25
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.mk b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.mk
new file mode 100644
index 000000000..4ac25257e
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/board.mk
@@ -0,0 +1,9 @@
+# List of all the mandatory board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P2148/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_LPC_P2148
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c
new file mode 100644
index 000000000..165bd7a1e
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.c
@@ -0,0 +1,110 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+/*
+ * Buzzer driver for Olimex LPC-P2148.
+ * Uses the timer 1 for wave generation and a Virtual Timer for the sound
+ * duration.
+ * The driver also generates an event when the sound is done and the buzzer
+ * goes silent.
+ */
+#include "hal.h"
+#include "buzzer.h"
+EventSource BuzzerSilentEventSource;
+#define StartCounter(t) ((t)->TC_EMR = 0xF1, (t)->TC_TCR = 1)
+#define StopCounter(t)  ((t)->TC_EMR = 0, (t)->TC_TCR = 2)
+/**
+ * @brief Buzzer driver initialization.
+ */
+void buzzInit(void) {
+  chEvtInit(&BuzzerSilentEventSource);
+  /*
+   * Switches P0.12 and P0.13 to MAT1.0 and MAT1.1 functions.
+   * Enables Timer1 clock.
+   */
+  PINSEL0 &= 0xF0FFFFFF;
+  PINSEL0 |= 0x0A000000;
+  PCONP = (PCONP & PCALL) | PCTIM1;
+  /*
+   * Timer setup.
+   */
+  TC *tc = T1Base;
+  StopCounter(tc);
+  tc->TC_CTCR = 0;                      /* Clock source is PCLK.        */
+  tc->TC_PR   = 0;                      /* Prescaler disabled.          */
+  tc->TC_MCR  = 2;                      /* Clear TC on match MR0.       */
+}
+/**
+ * @brief Stops the sound.
+ *
+ * @param[in] p pointer to the timer
+ */
+static void stop(void *p) {
+  StopCounter((TC *)p);
+  chSysLockFromIsr();
+  chEvtBroadcastI(&BuzzerSilentEventSource);
+  chSysUnlockFromIsr();
+}
+/**
+ * @brief Plays a tone asynchronously.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlay(uint32_t freq, systime_t duration) {
+  static VirtualTimer bvt;
+  TC *tc = T1Base;
+  chSysLock();
+  if (chVTIsArmedI(&bvt)) {             /* If a sound is already being  */
+    chVTResetI(&bvt);                   /* played then aborts it.       */
+    StopCounter(tc);
+  }
+  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+  StartCounter(tc);
+  chVTSetI(&bvt, duration, stop, tc);
+  chSysUnlock();
+}
+/**
+ * @brief Plays a tone.
+ *
+ * @param[in] freq approximated tone frequency
+ * @param[in] duration tone duration in systicks
+ */
+void buzzPlayWait(uint32_t freq, systime_t duration) {
+  TC *tc = T1Base;
+  StopCounter(tc);
+  tc->TC_MR0 = tc->TC_MR1 = (PCLK / (freq * 2));
+  StartCounter(tc);
+  chThdSleep(duration);
+  StopCounter(tc);
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h
new file mode 100644
index 000000000..998d31feb
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_LPC_P2148/buzzer.h
@@ -0,0 +1,32 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BUZZER_H_
+#define _BUZZER_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void buzzInit(void);
+  void buzzPlay(uint32_t freq, systime_t duration);
+  void buzzPlayWait(uint32_t freq, systime_t duration);
+#ifdef __cplusplus
+}
+#endif
+extern EventSource BuzzerSilentEventSource;
+#endif /* _BUZZER_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.c b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.c
new file mode 100644
index 000000000..aeb937762
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.c
@@ -0,0 +1,79 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+#if defined(__MSP430_HAS_PORT1__) || defined(__MSP430_HAS_PORT1_R__)
+  {VAL_P1OUT, VAL_P1DIR},
+#endif
+#if defined(__MSP430_HAS_PORT2__) || defined(__MSP430_HAS_PORT2_R__)
+  {VAL_P2OUT, VAL_P2DIR},
+#endif
+#if defined(__MSP430_HAS_PORT3__) || defined(__MSP430_HAS_PORT3_R__)
+  {VAL_P3OUT, VAL_P3DIR},
+#endif
+#if defined(__MSP430_HAS_PORT4__) || defined(__MSP430_HAS_PORT4_R__)
+  {VAL_P4OUT, VAL_P4DIR},
+#endif
+#if defined(__MSP430_HAS_PORT5__) || defined(__MSP430_HAS_PORT5_R__)
+  {VAL_P5OUT, VAL_P5DIR},
+#endif
+#if defined(__MSP430_HAS_PORT6__) || defined(__MSP430_HAS_PORT6_R__)
+  {VAL_P6OUT, VAL_P6DIR},
+#endif
+};
+#endif
+CH_IRQ_HANDLER(TIMERA0) {
+  CH_IRQ_PROLOGUE();
+  chSysLockFromIsr();
+  chSysTimerHandlerI();
+  chSysUnlockFromIsr();
+  CH_IRQ_EPILOGUE();
+}
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+#if USE_MSP430_USART0
+  P3SEL |= (1 << 4) | (1 << 5);
+#endif
+#if USE_MSP430_USART1
+  P3SEL |= (1 << 6) | (1 << 7);
+#endif
+  /*
+   * Timer 0 setup, uses SMCLK as source.
+   */
+  TACCR0 = SMCLK / 4 / CH_FREQUENCY - 1;/* Counter limit.               */
+  TACTL = TACLR;                        /* Clean start.                 */
+  TACTL = TASSEL_2 | ID_2 | MC_1;       /* Src=SMCLK, ID=4, cmp=TACCR0. */
+  TACCTL0 = CCIE;                       /* Interrupt on compare.        */
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.h b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.h
new file mode 100644
index 000000000..44a37d928
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.h
@@ -0,0 +1,80 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * Setup for the Olimex MSP430-P1611 proto board.
+ */
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_MSP430_P1611
+#define BOARD_NAME "Olimex MSP430-P1611"
+/*
+ * Clock constants.
+ */
+#define LFXT1CLK        32768
+#define XT2CLK          8000000
+#define DCOCLK          750000
+/*
+ * Pin definitions for the Olimex MSP430-P1611 board.
+ */
+#define P3_O_TXD0               4
+#define P3_O_TXD0_MASK          (1 << P3_O_TXD0)
+#define P3_I_RXD0               5
+#define P3_I_RXD0_MASK          (1 << P3_I_RXD0)
+#define P6_O_LED                0
+#define P6_O_LED_MASK           (1 << P6_O_LED)
+#define P6_I_BUTTON             1
+#define P6_I_BUTTON_MASK        (1 << P6_I_BUTTON)
+/*
+ * Initial I/O ports settings.
+ */
+#define VAL_P1OUT       0x00
+#define VAL_P1DIR       0xFF
+#define VAL_P2OUT       0x00
+#define VAL_P2DIR       0xFF
+#define VAL_P3OUT       P3_O_TXD0_MASK
+#define VAL_P3DIR       ~P3_I_RXD0_MASK
+#define VAL_P4OUT       0x00
+#define VAL_P4DIR       0xFF
+#define VAL_P5OUT       0x00
+#define VAL_P5DIR       0xFF
+#define VAL_P6OUT       P6_O_LED_MASK
+#define VAL_P6DIR       ~P6_I_BUTTON_MASK
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+#endif /* _BOARD_H_ */
diff --git a/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.mk b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.mk
new file mode 100644
index 000000000..df191c076
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_MSP430_P1611/board.mk
@@ -0,0 +1,9 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_MSP430_P1611/board.c
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_MSP430_P1611
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/lib/chibios/os/hal/boards/OLIMEX_SAM7_EX256/board.c b/lib/chibios/os/hal/boards/OLIMEX_SAM7_EX256/board.c
new file mode 100644
index 000000000..21ca13149
--- /dev/null
+++ b/lib/chibios/os/hal/boards/OLIMEX_SAM7_EX256/board.c
@@ -0,0 +1,136 @@
+/*
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+        http://www.apache.org/licenses/LICENSE-2.0
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+  {VAL_PIOA_ODSR, VAL_PIOA_OSR, VAL_PIOA_PUSR},
+#if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+    (SAM7_PLATFORM == SAM7X512) || (SAM7_PLATFORM == SAM7A3)
+  {VAL_PIOB_ODSR, VAL_PIOB_OSR, VAL_PIOB_PUSR}
+#endif
+};
+#endif
+/*
+ * SYS IRQ handling here.
+ */
+static CH_IRQ_HANDLER(SYSIrqHandler) {
+  CH_IRQ_PROLOGUE();
+  if (AT91C_BASE_PITC->PITC_PISR & AT91C_PITC_PITS) {
+    (void) AT91C_BASE_PITC->PITC_PIVR;
+    chSysLockFromIsr();
+    chSysTimerHandlerI();
+    chSysUnlockFromIsr();
+  }
+  
+#if USE_SAM7_DBGU_UART
+  if (AT91C_BASE_DBGU->DBGU_CSR &
+      (AT91C_US_RXRDY | AT91C_US_TXRDY | AT91C_US_PARE | AT91C_US_FRAME |
+       AT91C_US_OVRE | AT91C_US_RXBRK)) {
+    sd_lld_serve_interrupt(&SDDBG);
+  }
+#endif
+  AT91C_BASE_AIC->AIC_EOICR = 0;
+  CH_IRQ_EPILOGUE();
+}
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+  
+  /* Watchdog disabled.*/
+  AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS;
+  
+  at91sam7_clock_init();
+}
+#if HAL_USE_MMC_SPI
+/* Board-related functions related to the MMC_SPI driver.*/
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+  (void)mmcp;
+  return !palReadPad(IOPORT2, PIOB_MMC_CP);
+}
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+  (void)mmcp;
+  return palReadPad(IOPORT2, PIOB_MMC_WP);
+}
+#endif
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+  /*
+   * LCD pins setup.
+   */
+  palClearPad(IOPORT2, PIOB_LCD_BL);
+  palSetPadMode(IOPORT2, PIOB_LCD_BL, PAL_MODE_OUTPUT_PUSHPULL);
+  palSetPad(IOPORT1, PIOA_LCD_RESET);
+  palSetPadMode(IOPORT1, PIOA_LCD_RESET, PAL_MODE_OUTPUT_PUSHPULL);
+  /*
+   * Joystick and buttons setup.
+   */
+  palSetGroupMode(IOPORT1,
+                  PIOA_B1_MASK | PIOA_B2_MASK | PIOA_B3_MASK |
+                  PIOA_B4_MASK | PIOA_B5_MASK,
+                  0,
+                  PAL_MODE_INPUT);
+  palSetGroupMode(IOPORT2, PIOB_SW1_MASK | PIOB_SW2_MASK, 0, PAL_MODE_INPUT);
+  /*
+   * MMC/SD slot setup.
+   */
+  palSetGroupMode(IOPORT2,
+                  PIOB_MMC_WP_MASK | PIOB_MMC_CP_MASK,
+                  0,
+                  PAL_MODE_INPUT);
+  /*
+   * PIT Initialization.
+   */
+  AIC_ConfigureIT(AT91C_ID_SYS,
+                  AT91C_AIC_SRCTYPE_HIGH_LEVEL | (AT91C_AIC_PRIOR_HIGHEST - 1),
+                  SYSIrqHandler);
+  AIC_EnableIT(AT91C_ID_SYS);
+  AT91C_BASE_PITC->PITC_PIMR = (MCK / 16 / CH_FREQUENCY) - 1;
+  AT91C_BASE_PITC->PITC_PIMR |= AT91C_PITC_PITEN | AT91C_PITC_PITIEN;
+  /*
+   * RTS/CTS pins enabled for USART0 only.
+   */
+  AT91C_BASE_PIOA->PIO_PDR   = AT91C_PA3_RTS0 | AT91C_PA4_CTS0;
+  AT91C_BASE_PIOA->PIO_ASR   = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+  AT91C_BASE_PIOA->PIO_PPUDR = AT91C_PIO_PA3 | AT91C_PIO_PA4;
+}
diff --git a/lib/chibios/os/hal/boards/OLIMEX_SAM7_EX256/board.h b/lib/chibios/os/hal/boards/OLIMEX_SAM7_EX256/board.h